1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_STATE
14 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
15 select ARCH_ENABLE_MEMORY_HOTPLUG
16 select ARCH_ENABLE_MEMORY_HOTREMOVE
17 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
18 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
19 select ARCH_HAS_CACHE_LINE_SIZE
20 select ARCH_HAS_DEBUG_VIRTUAL
21 select ARCH_HAS_DEBUG_VM_PGTABLE
22 select ARCH_HAS_DMA_PREP_COHERENT
23 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
24 select ARCH_HAS_FAST_MULTIPLIER
25 select ARCH_HAS_FORTIFY_SOURCE
26 select ARCH_HAS_GCOV_PROFILE_ALL
27 select ARCH_HAS_GIGANTIC_PAGE
29 select ARCH_HAS_KEEPINITRD
30 select ARCH_HAS_MEMBARRIER_SYNC_CORE
31 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
32 select ARCH_HAS_PTE_DEVMAP
33 select ARCH_HAS_PTE_SPECIAL
34 select ARCH_HAS_SETUP_DMA_OPS
35 select ARCH_HAS_SET_DIRECT_MAP
36 select ARCH_HAS_SET_MEMORY
38 select ARCH_HAS_STRICT_KERNEL_RWX
39 select ARCH_HAS_STRICT_MODULE_RWX
40 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
41 select ARCH_HAS_SYNC_DMA_FOR_CPU
42 select ARCH_HAS_SYSCALL_WRAPPER
43 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
44 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
45 select ARCH_HAS_ZONE_DMA_SET if EXPERT
46 select ARCH_HAVE_ELF_PROT
47 select ARCH_HAVE_NMI_SAFE_CMPXCHG
48 select ARCH_INLINE_READ_LOCK if !PREEMPTION
49 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
50 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
51 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
52 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
53 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
54 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
56 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
57 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
58 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
60 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
61 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
62 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
64 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
65 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
66 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
67 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
68 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
70 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
74 select ARCH_KEEP_MEMBLOCK
75 select ARCH_USE_CMPXCHG_LOCKREF
76 select ARCH_USE_GNU_PROPERTY
77 select ARCH_USE_MEMTEST
78 select ARCH_USE_QUEUED_RWLOCKS
79 select ARCH_USE_QUEUED_SPINLOCKS
80 select ARCH_USE_SYM_ANNOTATIONS
81 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
82 select ARCH_SUPPORTS_HUGETLBFS
83 select ARCH_SUPPORTS_MEMORY_FAILURE
84 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
85 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
86 select ARCH_SUPPORTS_LTO_CLANG_THIN
87 select ARCH_SUPPORTS_CFI_CLANG
88 select ARCH_SUPPORTS_ATOMIC_RMW
89 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
90 select ARCH_SUPPORTS_NUMA_BALANCING
91 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
92 select ARCH_WANT_DEFAULT_BPF_JIT
93 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
94 select ARCH_WANT_FRAME_POINTERS
95 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
96 select ARCH_WANT_LD_ORPHAN_WARN
97 select ARCH_WANTS_NO_INSTR
98 select ARCH_HAS_UBSAN_SANITIZE_ALL
100 select ARM_ARCH_TIMER
102 select AUDIT_ARCH_COMPAT_GENERIC
103 select ARM_GIC_V2M if PCI
105 select ARM_GIC_V3_ITS if PCI
107 select BUILDTIME_TABLE_SORT
108 select CLONE_BACKWARDS
110 select CPU_PM if (SUSPEND || CPU_IDLE)
112 select DCACHE_WORD_ACCESS
113 select DMA_DIRECT_REMAP
116 select GENERIC_ALLOCATOR
117 select GENERIC_ARCH_TOPOLOGY
118 select GENERIC_CLOCKEVENTS_BROADCAST
119 select GENERIC_CPU_AUTOPROBE
120 select GENERIC_CPU_VULNERABILITIES
121 select GENERIC_EARLY_IOREMAP
122 select GENERIC_FIND_FIRST_BIT
123 select GENERIC_IDLE_POLL_SETUP
124 select GENERIC_IRQ_IPI
125 select GENERIC_IRQ_PROBE
126 select GENERIC_IRQ_SHOW
127 select GENERIC_IRQ_SHOW_LEVEL
128 select GENERIC_LIB_DEVMEM_IS_ALLOWED
129 select GENERIC_PCI_IOMAP
130 select GENERIC_PTDUMP
131 select GENERIC_SCHED_CLOCK
132 select GENERIC_SMP_IDLE_THREAD
133 select GENERIC_TIME_VSYSCALL
134 select GENERIC_GETTIMEOFDAY
135 select GENERIC_VDSO_TIME_NS
136 select HANDLE_DOMAIN_IRQ
137 select HARDIRQS_SW_RESEND
141 select HAVE_ACPI_APEI if (ACPI && EFI)
142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
143 select HAVE_ARCH_AUDITSYSCALL
144 select HAVE_ARCH_BITREVERSE
145 select HAVE_ARCH_COMPILER_H
146 select HAVE_ARCH_HUGE_VMAP
147 select HAVE_ARCH_JUMP_LABEL
148 select HAVE_ARCH_JUMP_LABEL_RELATIVE
149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
153 select HAVE_ARCH_KFENCE
154 select HAVE_ARCH_KGDB
155 select HAVE_ARCH_MMAP_RND_BITS
156 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
157 select HAVE_ARCH_PREL32_RELOCATIONS
158 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
159 select HAVE_ARCH_SECCOMP_FILTER
160 select HAVE_ARCH_STACKLEAK
161 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
162 select HAVE_ARCH_TRACEHOOK
163 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
164 select HAVE_ARCH_VMAP_STACK
165 select HAVE_ARM_SMCCC
166 select HAVE_ASM_MODVERSIONS
168 select HAVE_C_RECORDMCOUNT
169 select HAVE_CMPXCHG_DOUBLE
170 select HAVE_CMPXCHG_LOCAL
171 select HAVE_CONTEXT_TRACKING
172 select HAVE_DEBUG_KMEMLEAK
173 select HAVE_DMA_CONTIGUOUS
174 select HAVE_DYNAMIC_FTRACE
175 select HAVE_DYNAMIC_FTRACE_WITH_REGS \
176 if $(cc-option,-fpatchable-function-entry=2)
177 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
178 if DYNAMIC_FTRACE_WITH_REGS
179 select HAVE_EFFICIENT_UNALIGNED_ACCESS
181 select HAVE_FTRACE_MCOUNT_RECORD
182 select HAVE_FUNCTION_TRACER
183 select HAVE_FUNCTION_ERROR_INJECTION
184 select HAVE_FUNCTION_GRAPH_TRACER
185 select HAVE_GCC_PLUGINS
186 select HAVE_HW_BREAKPOINT if PERF_EVENTS
187 select HAVE_IRQ_TIME_ACCOUNTING
189 select HAVE_PATA_PLATFORM
190 select HAVE_PERF_EVENTS
191 select HAVE_PERF_REGS
192 select HAVE_PERF_USER_STACK_DUMP
193 select HAVE_REGS_AND_STACK_ACCESS_API
194 select HAVE_FUNCTION_ARG_ACCESS_API
195 select HAVE_FUTEX_CMPXCHG if FUTEX
196 select MMU_GATHER_RCU_TABLE_FREE
198 select HAVE_STACKPROTECTOR
199 select HAVE_SYSCALL_TRACEPOINTS
201 select HAVE_KRETPROBES
202 select HAVE_GENERIC_VDSO
203 select IOMMU_DMA if IOMMU_SUPPORT
205 select IRQ_FORCED_THREADING
206 select KASAN_VMALLOC if KASAN_GENERIC
207 select MODULES_USE_ELF_RELA
208 select NEED_DMA_MAP_STATE
209 select NEED_SG_DMA_LENGTH
211 select OF_EARLY_FLATTREE
212 select PCI_DOMAINS_GENERIC if PCI
213 select PCI_ECAM if (ACPI && PCI)
214 select PCI_SYSCALL if PCI
219 select SYSCTL_EXCEPTION_TRACE
220 select THREAD_INFO_IN_TASK
221 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
222 select TRACE_IRQFLAGS_SUPPORT
223 select TRACE_IRQFLAGS_NMI_SUPPORT
225 ARM 64-bit (AArch64) Linux support.
233 config ARM64_PAGE_SHIFT
235 default 16 if ARM64_64K_PAGES
236 default 14 if ARM64_16K_PAGES
239 config ARM64_CONT_PTE_SHIFT
241 default 5 if ARM64_64K_PAGES
242 default 7 if ARM64_16K_PAGES
245 config ARM64_CONT_PMD_SHIFT
247 default 5 if ARM64_64K_PAGES
248 default 5 if ARM64_16K_PAGES
251 config ARCH_MMAP_RND_BITS_MIN
252 default 14 if ARM64_64K_PAGES
253 default 16 if ARM64_16K_PAGES
256 # max bits determined by the following formula:
257 # VA_BITS - PAGE_SHIFT - 3
258 config ARCH_MMAP_RND_BITS_MAX
259 default 19 if ARM64_VA_BITS=36
260 default 24 if ARM64_VA_BITS=39
261 default 27 if ARM64_VA_BITS=42
262 default 30 if ARM64_VA_BITS=47
263 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
264 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
265 default 33 if ARM64_VA_BITS=48
266 default 14 if ARM64_64K_PAGES
267 default 16 if ARM64_16K_PAGES
270 config ARCH_MMAP_RND_COMPAT_BITS_MIN
271 default 7 if ARM64_64K_PAGES
272 default 9 if ARM64_16K_PAGES
275 config ARCH_MMAP_RND_COMPAT_BITS_MAX
281 config STACKTRACE_SUPPORT
284 config ILLEGAL_POINTER_VALUE
286 default 0xdead000000000000
288 config LOCKDEP_SUPPORT
295 config GENERIC_BUG_RELATIVE_POINTERS
297 depends on GENERIC_BUG
299 config GENERIC_HWEIGHT
305 config GENERIC_CALIBRATE_DELAY
308 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
314 config KERNEL_MODE_NEON
317 config FIX_EARLYCON_MEM
320 config PGTABLE_LEVELS
322 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
323 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
324 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
325 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
326 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
327 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
329 config ARCH_SUPPORTS_UPROBES
332 config ARCH_PROC_KCORE_TEXT
335 config BROKEN_GAS_INST
336 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
338 config KASAN_SHADOW_OFFSET
340 depends on KASAN_GENERIC || KASAN_SW_TAGS
341 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
342 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
343 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
344 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
345 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
346 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
347 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
348 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
349 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
350 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
351 default 0xffffffffffffffff
353 source "arch/arm64/Kconfig.platforms"
355 menu "Kernel Features"
357 menu "ARM errata workarounds via the alternatives framework"
359 config ARM64_WORKAROUND_CLEAN_CACHE
362 config ARM64_ERRATUM_826319
363 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
365 select ARM64_WORKAROUND_CLEAN_CACHE
367 This option adds an alternative code sequence to work around ARM
368 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
369 AXI master interface and an L2 cache.
371 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
372 and is unable to accept a certain write via this interface, it will
373 not progress on read data presented on the read data channel and the
376 The workaround promotes data cache clean instructions to
377 data cache clean-and-invalidate.
378 Please note that this does not necessarily enable the workaround,
379 as it depends on the alternative framework, which will only patch
380 the kernel if an affected CPU is detected.
384 config ARM64_ERRATUM_827319
385 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
387 select ARM64_WORKAROUND_CLEAN_CACHE
389 This option adds an alternative code sequence to work around ARM
390 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
391 master interface and an L2 cache.
393 Under certain conditions this erratum can cause a clean line eviction
394 to occur at the same time as another transaction to the same address
395 on the AMBA 5 CHI interface, which can cause data corruption if the
396 interconnect reorders the two transactions.
398 The workaround promotes data cache clean instructions to
399 data cache clean-and-invalidate.
400 Please note that this does not necessarily enable the workaround,
401 as it depends on the alternative framework, which will only patch
402 the kernel if an affected CPU is detected.
406 config ARM64_ERRATUM_824069
407 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
409 select ARM64_WORKAROUND_CLEAN_CACHE
411 This option adds an alternative code sequence to work around ARM
412 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
413 to a coherent interconnect.
415 If a Cortex-A53 processor is executing a store or prefetch for
416 write instruction at the same time as a processor in another
417 cluster is executing a cache maintenance operation to the same
418 address, then this erratum might cause a clean cache line to be
419 incorrectly marked as dirty.
421 The workaround promotes data cache clean instructions to
422 data cache clean-and-invalidate.
423 Please note that this option does not necessarily enable the
424 workaround, as it depends on the alternative framework, which will
425 only patch the kernel if an affected CPU is detected.
429 config ARM64_ERRATUM_819472
430 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
432 select ARM64_WORKAROUND_CLEAN_CACHE
434 This option adds an alternative code sequence to work around ARM
435 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
436 present when it is connected to a coherent interconnect.
438 If the processor is executing a load and store exclusive sequence at
439 the same time as a processor in another cluster is executing a cache
440 maintenance operation to the same address, then this erratum might
441 cause data corruption.
443 The workaround promotes data cache clean instructions to
444 data cache clean-and-invalidate.
445 Please note that this does not necessarily enable the workaround,
446 as it depends on the alternative framework, which will only patch
447 the kernel if an affected CPU is detected.
451 config ARM64_ERRATUM_832075
452 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
455 This option adds an alternative code sequence to work around ARM
456 erratum 832075 on Cortex-A57 parts up to r1p2.
458 Affected Cortex-A57 parts might deadlock when exclusive load/store
459 instructions to Write-Back memory are mixed with Device loads.
461 The workaround is to promote device loads to use Load-Acquire
463 Please note that this does not necessarily enable the workaround,
464 as it depends on the alternative framework, which will only patch
465 the kernel if an affected CPU is detected.
469 config ARM64_ERRATUM_834220
470 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
474 This option adds an alternative code sequence to work around ARM
475 erratum 834220 on Cortex-A57 parts up to r1p2.
477 Affected Cortex-A57 parts might report a Stage 2 translation
478 fault as the result of a Stage 1 fault for load crossing a
479 page boundary when there is a permission or device memory
480 alignment fault at Stage 1 and a translation fault at Stage 2.
482 The workaround is to verify that the Stage 1 translation
483 doesn't generate a fault before handling the Stage 2 fault.
484 Please note that this does not necessarily enable the workaround,
485 as it depends on the alternative framework, which will only patch
486 the kernel if an affected CPU is detected.
490 config ARM64_ERRATUM_1742098
491 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
495 This option removes the AES hwcap for aarch32 user-space to
496 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
498 Affected parts may corrupt the AES state if an interrupt is
499 taken between a pair of AES instructions. These instructions
500 are only present if the cryptography extensions are present.
501 All software should have a fallback implementation for CPUs
502 that don't implement the cryptography extensions.
506 config ARM64_ERRATUM_845719
507 bool "Cortex-A53: 845719: a load might read incorrect data"
511 This option adds an alternative code sequence to work around ARM
512 erratum 845719 on Cortex-A53 parts up to r0p4.
514 When running a compat (AArch32) userspace on an affected Cortex-A53
515 part, a load at EL0 from a virtual address that matches the bottom 32
516 bits of the virtual address used by a recent load at (AArch64) EL1
517 might return incorrect data.
519 The workaround is to write the contextidr_el1 register on exception
520 return to a 32-bit task.
521 Please note that this does not necessarily enable the workaround,
522 as it depends on the alternative framework, which will only patch
523 the kernel if an affected CPU is detected.
527 config ARM64_ERRATUM_843419
528 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
530 select ARM64_MODULE_PLTS if MODULES
532 This option links the kernel with '--fix-cortex-a53-843419' and
533 enables PLT support to replace certain ADRP instructions, which can
534 cause subsequent memory accesses to use an incorrect address on
535 Cortex-A53 parts up to r0p4.
539 config ARM64_LD_HAS_FIX_ERRATUM_843419
540 def_bool $(ld-option,--fix-cortex-a53-843419)
542 config ARM64_ERRATUM_1024718
543 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
546 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
548 Affected Cortex-A55 cores (all revisions) could cause incorrect
549 update of the hardware dirty bit when the DBM/AP bits are updated
550 without a break-before-make. The workaround is to disable the usage
551 of hardware DBM locally on the affected cores. CPUs not affected by
552 this erratum will continue to use the feature.
556 config ARM64_ERRATUM_1418040
557 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
561 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
562 errata 1188873 and 1418040.
564 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
565 cause register corruption when accessing the timer registers
566 from AArch32 userspace.
570 config ARM64_WORKAROUND_SPECULATIVE_AT
573 config ARM64_ERRATUM_1165522
574 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
576 select ARM64_WORKAROUND_SPECULATIVE_AT
578 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
580 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
581 corrupted TLBs by speculating an AT instruction during a guest
586 config ARM64_ERRATUM_1319367
587 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
589 select ARM64_WORKAROUND_SPECULATIVE_AT
591 This option adds work arounds for ARM Cortex-A57 erratum 1319537
592 and A72 erratum 1319367
594 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
595 speculating an AT instruction during a guest context switch.
599 config ARM64_ERRATUM_1530923
600 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
602 select ARM64_WORKAROUND_SPECULATIVE_AT
604 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
606 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
607 corrupted TLBs by speculating an AT instruction during a guest
612 config ARM64_WORKAROUND_REPEAT_TLBI
615 config ARM64_ERRATUM_2441007
616 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
618 select ARM64_WORKAROUND_REPEAT_TLBI
620 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
622 Under very rare circumstances, affected Cortex-A55 CPUs
623 may not handle a race between a break-before-make sequence on one
624 CPU, and another CPU accessing the same page. This could allow a
625 store to a page that has been unmapped.
627 Work around this by adding the affected CPUs to the list that needs
628 TLB sequences to be done twice.
632 config ARM64_ERRATUM_1286807
633 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
635 select ARM64_WORKAROUND_REPEAT_TLBI
637 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
639 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
640 address for a cacheable mapping of a location is being
641 accessed by a core while another core is remapping the virtual
642 address to a new physical page using the recommended
643 break-before-make sequence, then under very rare circumstances
644 TLBI+DSB completes before a read using the translation being
645 invalidated has been observed by other observers. The
646 workaround repeats the TLBI+DSB operation.
648 config ARM64_ERRATUM_1463225
649 bool "Cortex-A76: Software Step might prevent interrupt recognition"
652 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
654 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
655 of a system call instruction (SVC) can prevent recognition of
656 subsequent interrupts when software stepping is disabled in the
657 exception handler of the system call and either kernel debugging
658 is enabled or VHE is in use.
660 Work around the erratum by triggering a dummy step exception
661 when handling a system call from a task that is being stepped
662 in a VHE configuration of the kernel.
666 config ARM64_ERRATUM_1542419
667 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
670 This option adds a workaround for ARM Neoverse-N1 erratum
673 Affected Neoverse-N1 cores could execute a stale instruction when
674 modified by another CPU. The workaround depends on a firmware
677 Workaround the issue by hiding the DIC feature from EL0. This
678 forces user-space to perform cache maintenance.
682 config ARM64_ERRATUM_1508412
683 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
686 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
688 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
689 of a store-exclusive or read of PAR_EL1 and a load with device or
690 non-cacheable memory attributes. The workaround depends on a firmware
693 KVM guests must also have the workaround implemented or they can
696 Work around the issue by inserting DMB SY barriers around PAR_EL1
697 register reads and warning KVM users. The DMB barrier is sufficient
698 to prevent a speculative PAR_EL1 read.
702 config ARM64_ERRATUM_2441009
703 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
705 select ARM64_WORKAROUND_REPEAT_TLBI
707 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
709 Under very rare circumstances, affected Cortex-A510 CPUs
710 may not handle a race between a break-before-make sequence on one
711 CPU, and another CPU accessing the same page. This could allow a
712 store to a page that has been unmapped.
714 Work around this by adding the affected CPUs to the list that needs
715 TLB sequences to be done twice.
719 config ARM64_ERRATUM_2457168
720 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
721 depends on ARM64_AMU_EXTN
724 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
726 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
727 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
728 incorrectly giving a significantly higher output value.
730 Work around this problem by returning 0 when reading the affected counter in
731 key locations that results in disabling all users of this counter. This effect
732 is the same to firmware disabling affected counters.
736 config CAVIUM_ERRATUM_22375
737 bool "Cavium erratum 22375, 24313"
740 Enable workaround for errata 22375 and 24313.
742 This implements two gicv3-its errata workarounds for ThunderX. Both
743 with a small impact affecting only ITS table allocation.
745 erratum 22375: only alloc 8MB table size
746 erratum 24313: ignore memory access type
748 The fixes are in ITS initialization and basically ignore memory access
749 type and table size provided by the TYPER and BASER registers.
753 config CAVIUM_ERRATUM_23144
754 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
758 ITS SYNC command hang for cross node io and collections/cpu mapping.
762 config CAVIUM_ERRATUM_23154
763 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
766 The gicv3 of ThunderX requires a modified version for
767 reading the IAR status to ensure data synchronization
768 (access to icc_iar1_el1 is not sync'ed before and after).
772 config CAVIUM_ERRATUM_27456
773 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
776 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
777 instructions may cause the icache to become corrupted if it
778 contains data for a non-current ASID. The fix is to
779 invalidate the icache when changing the mm context.
783 config CAVIUM_ERRATUM_30115
784 bool "Cavium erratum 30115: Guest may disable interrupts in host"
787 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
788 1.2, and T83 Pass 1.0, KVM guest execution may disable
789 interrupts in host. Trapping both GICv3 group-0 and group-1
790 accesses sidesteps the issue.
794 config CAVIUM_TX2_ERRATUM_219
795 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
798 On Cavium ThunderX2, a load, store or prefetch instruction between a
799 TTBR update and the corresponding context synchronizing operation can
800 cause a spurious Data Abort to be delivered to any hardware thread in
803 Work around the issue by avoiding the problematic code sequence and
804 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
805 trap handler performs the corresponding register access, skips the
806 instruction and ensures context synchronization by virtue of the
811 config FUJITSU_ERRATUM_010001
812 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
815 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
816 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
817 accesses may cause undefined fault (Data abort, DFSC=0b111111).
818 This fault occurs under a specific hardware condition when a
819 load/store instruction performs an address translation using:
820 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
821 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
822 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
823 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
825 The workaround is to ensure these bits are clear in TCR_ELx.
826 The workaround only affects the Fujitsu-A64FX.
830 config HISILICON_ERRATUM_161600802
831 bool "Hip07 161600802: Erroneous redistributor VLPI base"
834 The HiSilicon Hip07 SoC uses the wrong redistributor base
835 when issued ITS commands such as VMOVP and VMAPP, and requires
836 a 128kB offset to be applied to the target address in this commands.
840 config QCOM_FALKOR_ERRATUM_1003
841 bool "Falkor E1003: Incorrect translation due to ASID change"
844 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
845 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
846 in TTBR1_EL1, this situation only occurs in the entry trampoline and
847 then only for entries in the walk cache, since the leaf translation
848 is unchanged. Work around the erratum by invalidating the walk cache
849 entries for the trampoline before entering the kernel proper.
851 config QCOM_FALKOR_ERRATUM_1009
852 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
854 select ARM64_WORKAROUND_REPEAT_TLBI
856 On Falkor v1, the CPU may prematurely complete a DSB following a
857 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
858 one more time to fix the issue.
862 config QCOM_QDF2400_ERRATUM_0065
863 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
866 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
867 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
868 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
872 config QCOM_FALKOR_ERRATUM_E1041
873 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
876 Falkor CPU may speculatively fetch instructions from an improper
877 memory location when MMU translation is changed from SCTLR_ELn[M]=1
878 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
882 config NVIDIA_CARMEL_CNP_ERRATUM
883 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
886 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
887 invalidate shared TLB entries installed by a different core, as it would
888 on standard ARM cores.
892 config SOCIONEXT_SYNQUACER_PREITS
893 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
896 Socionext Synquacer SoCs implement a separate h/w block to generate
897 MSI doorbell writes with non-zero values for the device ID.
906 default ARM64_4K_PAGES
908 Page size (translation granule) configuration.
910 config ARM64_4K_PAGES
913 This feature enables 4KB pages support.
915 config ARM64_16K_PAGES
918 The system will use 16KB pages support. AArch32 emulation
919 requires applications compiled with 16K (or a multiple of 16K)
922 config ARM64_64K_PAGES
925 This feature enables 64KB pages support (4KB by default)
926 allowing only two levels of page tables and faster TLB
927 look-up. AArch32 emulation requires applications compiled
928 with 64K aligned segments.
933 prompt "Virtual address space size"
934 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
935 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
936 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
938 Allows choosing one of multiple possible virtual address
939 space sizes. The level of translation table is determined by
940 a combination of page size and virtual address space size.
942 config ARM64_VA_BITS_36
943 bool "36-bit" if EXPERT
944 depends on ARM64_16K_PAGES
946 config ARM64_VA_BITS_39
948 depends on ARM64_4K_PAGES
950 config ARM64_VA_BITS_42
952 depends on ARM64_64K_PAGES
954 config ARM64_VA_BITS_47
956 depends on ARM64_16K_PAGES
958 config ARM64_VA_BITS_48
961 config ARM64_VA_BITS_52
963 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
965 Enable 52-bit virtual addressing for userspace when explicitly
966 requested via a hint to mmap(). The kernel will also use 52-bit
967 virtual addresses for its own mappings (provided HW support for
968 this feature is available, otherwise it reverts to 48-bit).
970 NOTE: Enabling 52-bit virtual addressing in conjunction with
971 ARMv8.3 Pointer Authentication will result in the PAC being
972 reduced from 7 bits to 3 bits, which may have a significant
973 impact on its susceptibility to brute-force attacks.
975 If unsure, select 48-bit virtual addressing instead.
979 config ARM64_FORCE_52BIT
980 bool "Force 52-bit virtual addresses for userspace"
981 depends on ARM64_VA_BITS_52 && EXPERT
983 For systems with 52-bit userspace VAs enabled, the kernel will attempt
984 to maintain compatibility with older software by providing 48-bit VAs
985 unless a hint is supplied to mmap.
987 This configuration option disables the 48-bit compatibility logic, and
988 forces all userspace addresses to be 52-bit on HW that supports it. One
989 should only enable this configuration option for stress testing userspace
990 memory management code. If unsure say N here.
994 default 36 if ARM64_VA_BITS_36
995 default 39 if ARM64_VA_BITS_39
996 default 42 if ARM64_VA_BITS_42
997 default 47 if ARM64_VA_BITS_47
998 default 48 if ARM64_VA_BITS_48
999 default 52 if ARM64_VA_BITS_52
1002 prompt "Physical address space size"
1003 default ARM64_PA_BITS_48
1005 Choose the maximum physical address range that the kernel will
1008 config ARM64_PA_BITS_48
1011 config ARM64_PA_BITS_52
1012 bool "52-bit (ARMv8.2)"
1013 depends on ARM64_64K_PAGES
1014 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1016 Enable support for a 52-bit physical address space, introduced as
1017 part of the ARMv8.2-LPA extension.
1019 With this enabled, the kernel will also continue to work on CPUs that
1020 do not support ARMv8.2-LPA, but with some added memory overhead (and
1021 minor performance overhead).
1025 config ARM64_PA_BITS
1027 default 48 if ARM64_PA_BITS_48
1028 default 52 if ARM64_PA_BITS_52
1032 default CPU_LITTLE_ENDIAN
1034 Select the endianness of data accesses performed by the CPU. Userspace
1035 applications will need to be compiled and linked for the endianness
1036 that is selected here.
1038 config CPU_BIG_ENDIAN
1039 bool "Build big-endian kernel"
1040 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1042 Say Y if you plan on running a kernel with a big-endian userspace.
1044 config CPU_LITTLE_ENDIAN
1045 bool "Build little-endian kernel"
1047 Say Y if you plan on running a kernel with a little-endian userspace.
1048 This is usually the case for distributions targeting arm64.
1053 bool "Multi-core scheduler support"
1055 Multi-core scheduler support improves the CPU scheduler's decision
1056 making when dealing with multi-core CPU chips at a cost of slightly
1057 increased overhead in some places. If unsure say N here.
1060 bool "SMT scheduler support"
1062 Improves the CPU scheduler's decision making when dealing with
1063 MultiThreading at a cost of slightly increased overhead in some
1064 places. If unsure say N here.
1067 int "Maximum number of CPUs (2-4096)"
1072 bool "Support for hot-pluggable CPUs"
1073 select GENERIC_IRQ_MIGRATION
1075 Say Y here to experiment with turning CPUs off and on. CPUs
1076 can be controlled through /sys/devices/system/cpu.
1078 # Common NUMA Features
1080 bool "NUMA Memory Allocation and Scheduler Support"
1081 select GENERIC_ARCH_NUMA
1082 select ACPI_NUMA if ACPI
1085 Enable NUMA (Non-Uniform Memory Access) support.
1087 The kernel will try to allocate memory used by a CPU on the
1088 local memory of the CPU and add some more
1089 NUMA awareness to the kernel.
1092 int "Maximum NUMA Nodes (as a power of 2)"
1097 Specify the maximum number of NUMA Nodes available on the target
1098 system. Increases memory reserved to accommodate various tables.
1100 config USE_PERCPU_NUMA_NODE_ID
1104 config HAVE_SETUP_PER_CPU_AREA
1108 config NEED_PER_CPU_EMBED_FIRST_CHUNK
1112 source "kernel/Kconfig.hz"
1114 config ARCH_SPARSEMEM_ENABLE
1116 select SPARSEMEM_VMEMMAP_ENABLE
1117 select SPARSEMEM_VMEMMAP
1119 config HW_PERF_EVENTS
1123 # Supported by clang >= 7.0
1124 config CC_HAVE_SHADOW_CALL_STACK
1125 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1128 bool "Enable paravirtualization code"
1130 This changes the kernel so it can modify itself when it is run
1131 under a hypervisor, potentially improving performance significantly
1132 over full virtualization.
1134 config PARAVIRT_TIME_ACCOUNTING
1135 bool "Paravirtual steal time accounting"
1138 Select this option to enable fine granularity task steal time
1139 accounting. Time spent executing other tasks in parallel with
1140 the current vCPU is discounted from the vCPU power. To account for
1141 that, there can be a small performance impact.
1143 If in doubt, say N here.
1146 depends on PM_SLEEP_SMP
1148 bool "kexec system call"
1150 kexec is a system call that implements the ability to shutdown your
1151 current kernel, and to start another kernel. It is like a reboot
1152 but it is independent of the system firmware. And like a reboot
1153 you can start any kernel with it, not just Linux.
1156 bool "kexec file based system call"
1158 select HAVE_IMA_KEXEC if IMA
1160 This is new version of kexec system call. This system call is
1161 file based and takes file descriptors as system call argument
1162 for kernel and initramfs as opposed to list of segments as
1163 accepted by previous system call.
1166 bool "Verify kernel signature during kexec_file_load() syscall"
1167 depends on KEXEC_FILE
1169 Select this option to verify a signature with loaded kernel
1170 image. If configured, any attempt of loading a image without
1171 valid signature will fail.
1173 In addition to that option, you need to enable signature
1174 verification for the corresponding kernel image type being
1175 loaded in order for this to work.
1177 config KEXEC_IMAGE_VERIFY_SIG
1178 bool "Enable Image signature verification support"
1180 depends on KEXEC_SIG
1181 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1183 Enable Image signature verification support.
1185 comment "Support for PE file signature verification disabled"
1186 depends on KEXEC_SIG
1187 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1190 bool "Build kdump crash kernel"
1192 Generate crash dump after being started by kexec. This should
1193 be normally only set in special crash dump kernels which are
1194 loaded in the main kernel with kexec-tools into a specially
1195 reserved region and then later executed after a crash by
1198 For more details see Documentation/admin-guide/kdump/kdump.rst
1202 depends on HIBERNATION
1209 bool "Xen guest support on ARM64"
1210 depends on ARM64 && OF
1214 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1216 config FORCE_MAX_ZONEORDER
1218 default "14" if ARM64_64K_PAGES
1219 default "12" if ARM64_16K_PAGES
1222 The kernel memory allocator divides physically contiguous memory
1223 blocks into "zones", where each zone is a power of two number of
1224 pages. This option selects the largest power of two that the kernel
1225 keeps in the memory allocator. If you need to allocate very large
1226 blocks of physically contiguous memory, then you may need to
1227 increase this value.
1229 This config option is actually maximum order plus one. For example,
1230 a value of 11 means that the largest free memory block is 2^10 pages.
1232 We make sure that we can allocate upto a HugePage size for each configuration.
1234 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1236 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1237 4M allocations matching the default size used by generic code.
1239 config UNMAP_KERNEL_AT_EL0
1240 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1243 Speculation attacks against some high-performance processors can
1244 be used to bypass MMU permission checks and leak kernel data to
1245 userspace. This can be defended against by unmapping the kernel
1246 when running in userspace, mapping it back in on exception entry
1247 via a trampoline page in the vector table.
1251 config MITIGATE_SPECTRE_BRANCH_HISTORY
1252 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1255 Speculation attacks against some high-performance processors can
1256 make use of branch history to influence future speculation.
1257 When taking an exception from user-space, a sequence of branches
1258 or a firmware call overwrites the branch history.
1260 config RODATA_FULL_DEFAULT_ENABLED
1261 bool "Apply r/o permissions of VM areas also to their linear aliases"
1264 Apply read-only attributes of VM areas to the linear alias of
1265 the backing pages as well. This prevents code or read-only data
1266 from being modified (inadvertently or intentionally) via another
1267 mapping of the same memory page. This additional enhancement can
1268 be turned off at runtime by passing rodata=[off|on] (and turned on
1269 with rodata=full if this option is set to 'n')
1271 This requires the linear region to be mapped down to pages,
1272 which may adversely affect performance in some cases.
1274 config ARM64_SW_TTBR0_PAN
1275 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1277 Enabling this option prevents the kernel from accessing
1278 user-space memory directly by pointing TTBR0_EL1 to a reserved
1279 zeroed area and reserved ASID. The user access routines
1280 restore the valid TTBR0_EL1 temporarily.
1282 config ARM64_TAGGED_ADDR_ABI
1283 bool "Enable the tagged user addresses syscall ABI"
1286 When this option is enabled, user applications can opt in to a
1287 relaxed ABI via prctl() allowing tagged addresses to be passed
1288 to system calls as pointer arguments. For details, see
1289 Documentation/arm64/tagged-address-abi.rst.
1292 bool "Kernel support for 32-bit EL0"
1293 depends on ARM64_4K_PAGES || EXPERT
1295 select OLD_SIGSUSPEND3
1296 select COMPAT_OLD_SIGACTION
1298 This option enables support for a 32-bit EL0 running under a 64-bit
1299 kernel at EL1. AArch32-specific components such as system calls,
1300 the user helper functions, VFP support and the ptrace interface are
1301 handled appropriately by the kernel.
1303 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1304 that you will only be able to execute AArch32 binaries that were compiled
1305 with page size aligned segments.
1307 If you want to execute 32-bit userspace applications, say Y.
1311 config KUSER_HELPERS
1312 bool "Enable kuser helpers page for 32-bit applications"
1315 Warning: disabling this option may break 32-bit user programs.
1317 Provide kuser helpers to compat tasks. The kernel provides
1318 helper code to userspace in read only form at a fixed location
1319 to allow userspace to be independent of the CPU type fitted to
1320 the system. This permits binaries to be run on ARMv4 through
1321 to ARMv8 without modification.
1323 See Documentation/arm/kernel_user_helpers.rst for details.
1325 However, the fixed address nature of these helpers can be used
1326 by ROP (return orientated programming) authors when creating
1329 If all of the binaries and libraries which run on your platform
1330 are built specifically for your platform, and make no use of
1331 these helpers, then you can turn this option off to hinder
1332 such exploits. However, in that case, if a binary or library
1333 relying on those helpers is run, it will not function correctly.
1335 Say N here only if you are absolutely certain that you do not
1336 need these helpers; otherwise, the safe option is to say Y.
1339 bool "Enable vDSO for 32-bit applications"
1340 depends on !CPU_BIG_ENDIAN
1341 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1342 select GENERIC_COMPAT_VDSO
1345 Place in the process address space of 32-bit applications an
1346 ELF shared object providing fast implementations of gettimeofday
1349 You must have a 32-bit build of glibc 2.22 or later for programs
1350 to seamlessly take advantage of this.
1352 config THUMB2_COMPAT_VDSO
1353 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1354 depends on COMPAT_VDSO
1357 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1358 otherwise with '-marm'.
1360 menuconfig ARMV8_DEPRECATED
1361 bool "Emulate deprecated/obsolete ARMv8 instructions"
1364 Legacy software support may require certain instructions
1365 that have been deprecated or obsoleted in the architecture.
1367 Enable this config to enable selective emulation of these
1374 config SWP_EMULATION
1375 bool "Emulate SWP/SWPB instructions"
1377 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1378 they are always undefined. Say Y here to enable software
1379 emulation of these instructions for userspace using LDXR/STXR.
1380 This feature can be controlled at runtime with the abi.swp
1381 sysctl which is disabled by default.
1383 In some older versions of glibc [<=2.8] SWP is used during futex
1384 trylock() operations with the assumption that the code will not
1385 be preempted. This invalid assumption may be more likely to fail
1386 with SWP emulation enabled, leading to deadlock of the user
1389 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1390 on an external transaction monitoring block called a global
1391 monitor to maintain update atomicity. If your system does not
1392 implement a global monitor, this option can cause programs that
1393 perform SWP operations to uncached memory to deadlock.
1397 config CP15_BARRIER_EMULATION
1398 bool "Emulate CP15 Barrier instructions"
1400 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1401 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1402 strongly recommended to use the ISB, DSB, and DMB
1403 instructions instead.
1405 Say Y here to enable software emulation of these
1406 instructions for AArch32 userspace code. When this option is
1407 enabled, CP15 barrier usage is traced which can help
1408 identify software that needs updating. This feature can be
1409 controlled at runtime with the abi.cp15_barrier sysctl.
1413 config SETEND_EMULATION
1414 bool "Emulate SETEND instruction"
1416 The SETEND instruction alters the data-endianness of the
1417 AArch32 EL0, and is deprecated in ARMv8.
1419 Say Y here to enable software emulation of the instruction
1420 for AArch32 userspace code. This feature can be controlled
1421 at runtime with the abi.setend sysctl.
1423 Note: All the cpus on the system must have mixed endian support at EL0
1424 for this feature to be enabled. If a new CPU - which doesn't support mixed
1425 endian - is hotplugged in after this feature has been enabled, there could
1426 be unexpected results in the applications.
1433 menu "ARMv8.1 architectural features"
1435 config ARM64_HW_AFDBM
1436 bool "Support for hardware updates of the Access and Dirty page flags"
1439 The ARMv8.1 architecture extensions introduce support for
1440 hardware updates of the access and dirty information in page
1441 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1442 capable processors, accesses to pages with PTE_AF cleared will
1443 set this bit instead of raising an access flag fault.
1444 Similarly, writes to read-only pages with the DBM bit set will
1445 clear the read-only bit (AP[2]) instead of raising a
1448 Kernels built with this configuration option enabled continue
1449 to work on pre-ARMv8.1 hardware and the performance impact is
1450 minimal. If unsure, say Y.
1453 bool "Enable support for Privileged Access Never (PAN)"
1456 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1457 prevents the kernel or hypervisor from accessing user-space (EL0)
1460 Choosing this option will cause any unprotected (not using
1461 copy_to_user et al) memory access to fail with a permission fault.
1463 The feature is detected at runtime, and will remain as a 'nop'
1464 instruction if the cpu does not implement the feature.
1467 def_bool $(as-instr,.arch_extension rcpc)
1469 config AS_HAS_LSE_ATOMICS
1470 def_bool $(as-instr,.arch_extension lse)
1472 config ARM64_LSE_ATOMICS
1474 default ARM64_USE_LSE_ATOMICS
1475 depends on AS_HAS_LSE_ATOMICS
1477 config ARM64_USE_LSE_ATOMICS
1478 bool "Atomic instructions"
1479 depends on JUMP_LABEL
1482 As part of the Large System Extensions, ARMv8.1 introduces new
1483 atomic instructions that are designed specifically to scale in
1486 Say Y here to make use of these instructions for the in-kernel
1487 atomic routines. This incurs a small overhead on CPUs that do
1488 not support these instructions and requires the kernel to be
1489 built with binutils >= 2.25 in order for the new instructions
1494 menu "ARMv8.2 architectural features"
1497 bool "Enable support for persistent memory"
1498 select ARCH_HAS_PMEM_API
1499 select ARCH_HAS_UACCESS_FLUSHCACHE
1501 Say Y to enable support for the persistent memory API based on the
1502 ARMv8.2 DCPoP feature.
1504 The feature is detected at runtime, and the kernel will use DC CVAC
1505 operations if DC CVAP is not supported (following the behaviour of
1506 DC CVAP itself if the system does not define a point of persistence).
1508 config ARM64_RAS_EXTN
1509 bool "Enable support for RAS CPU Extensions"
1512 CPUs that support the Reliability, Availability and Serviceability
1513 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1514 errors, classify them and report them to software.
1516 On CPUs with these extensions system software can use additional
1517 barriers to determine if faults are pending and read the
1518 classification from a new set of registers.
1520 Selecting this feature will allow the kernel to use these barriers
1521 and access the new registers if the system supports the extension.
1522 Platform RAS features may additionally depend on firmware support.
1525 bool "Enable support for Common Not Private (CNP) translations"
1527 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1529 Common Not Private (CNP) allows translation table entries to
1530 be shared between different PEs in the same inner shareable
1531 domain, so the hardware can use this fact to optimise the
1532 caching of such entries in the TLB.
1534 Selecting this option allows the CNP feature to be detected
1535 at runtime, and does not affect PEs that do not implement
1540 menu "ARMv8.3 architectural features"
1542 config ARM64_PTR_AUTH
1543 bool "Enable support for pointer authentication"
1546 Pointer authentication (part of the ARMv8.3 Extensions) provides
1547 instructions for signing and authenticating pointers against secret
1548 keys, which can be used to mitigate Return Oriented Programming (ROP)
1551 This option enables these instructions at EL0 (i.e. for userspace).
1552 Choosing this option will cause the kernel to initialise secret keys
1553 for each process at exec() time, with these keys being
1554 context-switched along with the process.
1556 The feature is detected at runtime. If the feature is not present in
1557 hardware it will not be advertised to userspace/KVM guest nor will it
1560 If the feature is present on the boot CPU but not on a late CPU, then
1561 the late CPU will be parked. Also, if the boot CPU does not have
1562 address auth and the late CPU has then the late CPU will still boot
1563 but with the feature disabled. On such a system, this option should
1566 config ARM64_PTR_AUTH_KERNEL
1567 bool "Use pointer authentication for kernel"
1569 depends on ARM64_PTR_AUTH
1570 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1571 # Modern compilers insert a .note.gnu.property section note for PAC
1572 # which is only understood by binutils starting with version 2.33.1.
1573 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1574 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1575 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1577 If the compiler supports the -mbranch-protection or
1578 -msign-return-address flag (e.g. GCC 7 or later), then this option
1579 will cause the kernel itself to be compiled with return address
1580 protection. In this case, and if the target hardware is known to
1581 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1582 disabled with minimal loss of protection.
1584 This feature works with FUNCTION_GRAPH_TRACER option only if
1585 DYNAMIC_FTRACE_WITH_REGS is enabled.
1587 config CC_HAS_BRANCH_PROT_PAC_RET
1588 # GCC 9 or later, clang 8 or later
1589 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1591 config CC_HAS_SIGN_RETURN_ADDRESS
1593 def_bool $(cc-option,-msign-return-address=all)
1596 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1598 config AS_HAS_CFI_NEGATE_RA_STATE
1599 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1603 menu "ARMv8.4 architectural features"
1605 config ARM64_AMU_EXTN
1606 bool "Enable support for the Activity Monitors Unit CPU extension"
1609 The activity monitors extension is an optional extension introduced
1610 by the ARMv8.4 CPU architecture. This enables support for version 1
1611 of the activity monitors architecture, AMUv1.
1613 To enable the use of this extension on CPUs that implement it, say Y.
1615 Note that for architectural reasons, firmware _must_ implement AMU
1616 support when running on CPUs that present the activity monitors
1617 extension. The required support is present in:
1618 * Version 1.5 and later of the ARM Trusted Firmware
1620 For kernels that have this configuration enabled but boot with broken
1621 firmware, you may need to say N here until the firmware is fixed.
1622 Otherwise you may experience firmware panics or lockups when
1623 accessing the counter registers. Even if you are not observing these
1624 symptoms, the values returned by the register reads might not
1625 correctly reflect reality. Most commonly, the value read will be 0,
1626 indicating that the counter is not enabled.
1628 config AS_HAS_ARMV8_4
1629 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1631 config ARM64_TLB_RANGE
1632 bool "Enable support for tlbi range feature"
1634 depends on AS_HAS_ARMV8_4
1636 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1637 range of input addresses.
1639 The feature introduces new assembly instructions, and they were
1640 support when binutils >= 2.30.
1644 menu "ARMv8.5 architectural features"
1646 config AS_HAS_ARMV8_5
1647 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1650 bool "Branch Target Identification support"
1653 Branch Target Identification (part of the ARMv8.5 Extensions)
1654 provides a mechanism to limit the set of locations to which computed
1655 branch instructions such as BR or BLR can jump.
1657 To make use of BTI on CPUs that support it, say Y.
1659 BTI is intended to provide complementary protection to other control
1660 flow integrity protection mechanisms, such as the Pointer
1661 authentication mechanism provided as part of the ARMv8.3 Extensions.
1662 For this reason, it does not make sense to enable this option without
1663 also enabling support for pointer authentication. Thus, when
1664 enabling this option you should also select ARM64_PTR_AUTH=y.
1666 Userspace binaries must also be specifically compiled to make use of
1667 this mechanism. If you say N here or the hardware does not support
1668 BTI, such binaries can still run, but you get no additional
1669 enforcement of branch destinations.
1671 config ARM64_BTI_KERNEL
1672 bool "Use Branch Target Identification for kernel"
1674 depends on ARM64_BTI
1675 depends on ARM64_PTR_AUTH_KERNEL
1676 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1677 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1678 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1679 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1680 depends on !CC_IS_GCC
1681 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1682 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1683 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1685 Build the kernel with Branch Target Identification annotations
1686 and enable enforcement of this for kernel code. When this option
1687 is enabled and the system supports BTI all kernel code including
1688 modular code must have BTI enabled.
1690 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1691 # GCC 9 or later, clang 8 or later
1692 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1695 bool "Enable support for E0PD"
1698 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1699 that EL0 accesses made via TTBR1 always fault in constant time,
1700 providing similar benefits to KASLR as those provided by KPTI, but
1701 with lower overhead and without disrupting legitimate access to
1702 kernel memory such as SPE.
1704 This option enables E0PD for TTBR1 where available.
1707 bool "Enable support for random number generation"
1710 Random number generation (part of the ARMv8.5 Extensions)
1711 provides a high bandwidth, cryptographically secure
1712 hardware random number generator.
1714 config ARM64_AS_HAS_MTE
1715 # Initial support for MTE went in binutils 2.32.0, checked with
1716 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1717 # as a late addition to the final architecture spec (LDGM/STGM)
1718 # is only supported in the newer 2.32.x and 2.33 binutils
1719 # versions, hence the extra "stgm" instruction check below.
1720 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1723 bool "Memory Tagging Extension support"
1725 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1726 depends on AS_HAS_ARMV8_5
1727 depends on AS_HAS_LSE_ATOMICS
1728 # Required for tag checking in the uaccess routines
1729 depends on ARM64_PAN
1730 select ARCH_USES_HIGH_VMA_FLAGS
1732 Memory Tagging (part of the ARMv8.5 Extensions) provides
1733 architectural support for run-time, always-on detection of
1734 various classes of memory error to aid with software debugging
1735 to eliminate vulnerabilities arising from memory-unsafe
1738 This option enables the support for the Memory Tagging
1739 Extension at EL0 (i.e. for userspace).
1741 Selecting this option allows the feature to be detected at
1742 runtime. Any secondary CPU not implementing this feature will
1743 not be allowed a late bring-up.
1745 Userspace binaries that want to use this feature must
1746 explicitly opt in. The mechanism for the userspace is
1749 Documentation/arm64/memory-tagging-extension.rst.
1753 menu "ARMv8.7 architectural features"
1756 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1758 depends on ARM64_PAN
1760 Enhanced Privileged Access Never (EPAN) allows Privileged
1761 Access Never to be used with Execute-only mappings.
1763 The feature is detected at runtime, and will remain disabled
1764 if the cpu does not implement the feature.
1768 bool "ARM Scalable Vector Extension support"
1771 The Scalable Vector Extension (SVE) is an extension to the AArch64
1772 execution state which complements and extends the SIMD functionality
1773 of the base architecture to support much larger vectors and to enable
1774 additional vectorisation opportunities.
1776 To enable use of this extension on CPUs that implement it, say Y.
1778 On CPUs that support the SVE2 extensions, this option will enable
1781 Note that for architectural reasons, firmware _must_ implement SVE
1782 support when running on SVE capable hardware. The required support
1785 * version 1.5 and later of the ARM Trusted Firmware
1786 * the AArch64 boot wrapper since commit 5e1261e08abf
1787 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1789 For other firmware implementations, consult the firmware documentation
1792 If you need the kernel to boot on SVE-capable hardware with broken
1793 firmware, you may need to say N here until you get your firmware
1794 fixed. Otherwise, you may experience firmware panics or lockups when
1795 booting the kernel. If unsure and you are not observing these
1796 symptoms, you should assume that it is safe to say Y.
1798 config ARM64_MODULE_PLTS
1799 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1801 select HAVE_MOD_ARCH_SPECIFIC
1803 Allocate PLTs when loading modules so that jumps and calls whose
1804 targets are too far away for their relative offsets to be encoded
1805 in the instructions themselves can be bounced via veneers in the
1806 module's PLT. This allows modules to be allocated in the generic
1807 vmalloc area after the dedicated module memory area has been
1810 When running with address space randomization (KASLR), the module
1811 region itself may be too far away for ordinary relative jumps and
1812 calls, and so in that case, module PLTs are required and cannot be
1815 Specific errata workaround(s) might also force module PLTs to be
1816 enabled (ARM64_ERRATUM_843419).
1818 config ARM64_PSEUDO_NMI
1819 bool "Support for NMI-like interrupts"
1822 Adds support for mimicking Non-Maskable Interrupts through the use of
1823 GIC interrupt priority. This support requires version 3 or later of
1826 This high priority configuration for interrupts needs to be
1827 explicitly enabled by setting the kernel parameter
1828 "irqchip.gicv3_pseudo_nmi" to 1.
1833 config ARM64_DEBUG_PRIORITY_MASKING
1834 bool "Debug interrupt priority masking"
1836 This adds runtime checks to functions enabling/disabling
1837 interrupts when using priority masking. The additional checks verify
1838 the validity of ICC_PMR_EL1 when calling concerned functions.
1844 bool "Build a relocatable kernel image" if EXPERT
1845 select ARCH_HAS_RELR
1848 This builds the kernel as a Position Independent Executable (PIE),
1849 which retains all relocation metadata required to relocate the
1850 kernel binary at runtime to a different virtual address than the
1851 address it was linked at.
1852 Since AArch64 uses the RELA relocation format, this requires a
1853 relocation pass at runtime even if the kernel is loaded at the
1854 same address it was linked at.
1856 config RANDOMIZE_BASE
1857 bool "Randomize the address of the kernel image"
1858 select ARM64_MODULE_PLTS if MODULES
1861 Randomizes the virtual address at which the kernel image is
1862 loaded, as a security feature that deters exploit attempts
1863 relying on knowledge of the location of kernel internals.
1865 It is the bootloader's job to provide entropy, by passing a
1866 random u64 value in /chosen/kaslr-seed at kernel entry.
1868 When booting via the UEFI stub, it will invoke the firmware's
1869 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1870 to the kernel proper. In addition, it will randomise the physical
1871 location of the kernel Image as well.
1875 config RANDOMIZE_MODULE_REGION_FULL
1876 bool "Randomize the module region over a 2 GB range"
1877 depends on RANDOMIZE_BASE
1880 Randomizes the location of the module region inside a 2 GB window
1881 covering the core kernel. This way, it is less likely for modules
1882 to leak information about the location of core kernel data structures
1883 but it does imply that function calls between modules and the core
1884 kernel will need to be resolved via veneers in the module PLT.
1886 When this option is not set, the module region will be randomized over
1887 a limited range that contains the [_stext, _etext] interval of the
1888 core kernel, so branch relocations are almost always in range unless
1889 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
1890 particular case of region exhaustion, modules might be able to fall
1891 back to a larger 2GB area.
1893 config CC_HAVE_STACKPROTECTOR_SYSREG
1894 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1896 config STACKPROTECTOR_PER_TASK
1898 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1904 config ARM64_ACPI_PARKING_PROTOCOL
1905 bool "Enable support for the ARM64 ACPI parking protocol"
1908 Enable support for the ARM64 ACPI parking protocol. If disabled
1909 the kernel will not allow booting through the ARM64 ACPI parking
1910 protocol even if the corresponding data is present in the ACPI
1914 string "Default kernel command string"
1917 Provide a set of default command-line options at build time by
1918 entering them here. As a minimum, you should specify the the
1919 root device (e.g. root=/dev/nfs).
1922 prompt "Kernel command line type" if CMDLINE != ""
1923 default CMDLINE_FROM_BOOTLOADER
1925 Choose how the kernel will handle the provided default kernel
1926 command line string.
1928 config CMDLINE_FROM_BOOTLOADER
1929 bool "Use bootloader kernel arguments if available"
1931 Uses the command-line options passed by the boot loader. If
1932 the boot loader doesn't provide any, the default kernel command
1933 string provided in CMDLINE will be used.
1935 config CMDLINE_FORCE
1936 bool "Always use the default kernel command string"
1938 Always use the default kernel command string, even if the boot
1939 loader passes other arguments to the kernel.
1940 This is useful if you cannot or don't want to change the
1941 command-line options your boot loader passes to the kernel.
1949 bool "UEFI runtime support"
1950 depends on OF && !CPU_BIG_ENDIAN
1951 depends on KERNEL_MODE_NEON
1952 select ARCH_SUPPORTS_ACPI
1955 select EFI_PARAMS_FROM_FDT
1956 select EFI_RUNTIME_WRAPPERS
1958 select EFI_GENERIC_STUB
1959 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
1962 This option provides support for runtime services provided
1963 by UEFI firmware (such as non-volatile variables, realtime
1964 clock, and platform reset). A UEFI stub is also provided to
1965 allow the kernel to be booted as an EFI application. This
1966 is only useful on systems that have UEFI firmware.
1969 bool "Enable support for SMBIOS (DMI) tables"
1973 This enables SMBIOS/DMI feature for systems.
1975 This option is only useful on systems that have UEFI firmware.
1976 However, even with this option, the resultant kernel should
1977 continue to boot on existing non-UEFI platforms.
1981 config SYSVIPC_COMPAT
1983 depends on COMPAT && SYSVIPC
1985 menu "Power management options"
1987 source "kernel/power/Kconfig"
1989 config ARCH_HIBERNATION_POSSIBLE
1993 config ARCH_HIBERNATION_HEADER
1995 depends on HIBERNATION
1997 config ARCH_SUSPEND_POSSIBLE
2002 menu "CPU Power Management"
2004 source "drivers/cpuidle/Kconfig"
2006 source "drivers/cpufreq/Kconfig"
2010 source "drivers/acpi/Kconfig"
2012 source "arch/arm64/kvm/Kconfig"
2015 source "arch/arm64/crypto/Kconfig"