1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_HAS_DEBUG_WX
13 select ARCH_BINFMT_ELF_EXTRA_PHDRS
14 select ARCH_BINFMT_ELF_STATE
15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17 select ARCH_ENABLE_MEMORY_HOTPLUG
18 select ARCH_ENABLE_MEMORY_HOTREMOVE
19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
21 select ARCH_HAS_CACHE_LINE_SIZE
22 select ARCH_HAS_CURRENT_STACK_POINTER
23 select ARCH_HAS_DEBUG_VIRTUAL
24 select ARCH_HAS_DEBUG_VM_PGTABLE
25 select ARCH_HAS_DMA_PREP_COHERENT
26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
27 select ARCH_HAS_FAST_MULTIPLIER
28 select ARCH_HAS_FORTIFY_SOURCE
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_HAS_GIGANTIC_PAGE
32 select ARCH_HAS_KEEPINITRD
33 select ARCH_HAS_MEMBARRIER_SYNC_CORE
34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
35 select ARCH_HAS_PTE_DEVMAP
36 select ARCH_HAS_PTE_SPECIAL
37 select ARCH_HAS_SETUP_DMA_OPS
38 select ARCH_HAS_SET_DIRECT_MAP
39 select ARCH_HAS_SET_MEMORY
41 select ARCH_HAS_STRICT_KERNEL_RWX
42 select ARCH_HAS_STRICT_MODULE_RWX
43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
44 select ARCH_HAS_SYNC_DMA_FOR_CPU
45 select ARCH_HAS_SYSCALL_WRAPPER
46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
48 select ARCH_HAS_ZONE_DMA_SET if EXPERT
49 select ARCH_HAVE_ELF_PROT
50 select ARCH_HAVE_NMI_SAFE_CMPXCHG
51 select ARCH_INLINE_READ_LOCK if !PREEMPTION
52 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
53 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
54 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
55 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
56 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
57 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
59 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
60 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
61 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
63 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
64 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
65 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
67 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
68 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
69 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
70 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
71 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
73 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
74 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
75 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
77 select ARCH_KEEP_MEMBLOCK
78 select ARCH_USE_CMPXCHG_LOCKREF
79 select ARCH_USE_GNU_PROPERTY
80 select ARCH_USE_MEMTEST
81 select ARCH_USE_QUEUED_RWLOCKS
82 select ARCH_USE_QUEUED_SPINLOCKS
83 select ARCH_USE_SYM_ANNOTATIONS
84 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
85 select ARCH_SUPPORTS_HUGETLBFS
86 select ARCH_SUPPORTS_MEMORY_FAILURE
87 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
88 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
89 select ARCH_SUPPORTS_LTO_CLANG_THIN
90 select ARCH_SUPPORTS_CFI_CLANG
91 select ARCH_SUPPORTS_ATOMIC_RMW
92 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
93 select ARCH_SUPPORTS_NUMA_BALANCING
94 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
95 select ARCH_WANT_DEFAULT_BPF_JIT
96 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
97 select ARCH_WANT_FRAME_POINTERS
98 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
99 select ARCH_WANT_LD_ORPHAN_WARN
100 select ARCH_WANTS_NO_INSTR
101 select ARCH_HAS_UBSAN_SANITIZE_ALL
103 select ARM_ARCH_TIMER
105 select AUDIT_ARCH_COMPAT_GENERIC
106 select ARM_GIC_V2M if PCI
108 select ARM_GIC_V3_ITS if PCI
110 select BUILDTIME_TABLE_SORT
111 select CLONE_BACKWARDS
113 select CPU_PM if (SUSPEND || CPU_IDLE)
115 select DCACHE_WORD_ACCESS
116 select DMA_DIRECT_REMAP
119 select GENERIC_ALLOCATOR
120 select GENERIC_ARCH_TOPOLOGY
121 select GENERIC_CLOCKEVENTS_BROADCAST
122 select GENERIC_CPU_AUTOPROBE
123 select GENERIC_CPU_VULNERABILITIES
124 select GENERIC_EARLY_IOREMAP
125 select GENERIC_IDLE_POLL_SETUP
126 select GENERIC_IRQ_IPI
127 select GENERIC_IRQ_PROBE
128 select GENERIC_IRQ_SHOW
129 select GENERIC_IRQ_SHOW_LEVEL
130 select GENERIC_LIB_DEVMEM_IS_ALLOWED
131 select GENERIC_PCI_IOMAP
132 select GENERIC_PTDUMP
133 select GENERIC_SCHED_CLOCK
134 select GENERIC_SMP_IDLE_THREAD
135 select GENERIC_TIME_VSYSCALL
136 select GENERIC_GETTIMEOFDAY
137 select GENERIC_VDSO_TIME_NS
138 select HARDIRQS_SW_RESEND
142 select HAVE_ACPI_APEI if (ACPI && EFI)
143 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
144 select HAVE_ARCH_AUDITSYSCALL
145 select HAVE_ARCH_BITREVERSE
146 select HAVE_ARCH_COMPILER_H
147 select HAVE_ARCH_HUGE_VMAP
148 select HAVE_ARCH_JUMP_LABEL
149 select HAVE_ARCH_JUMP_LABEL_RELATIVE
150 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
151 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
152 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
153 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
154 # Some instrumentation may be unsound, hence EXPERT
155 select HAVE_ARCH_KCSAN if EXPERT
156 select HAVE_ARCH_KFENCE
157 select HAVE_ARCH_KGDB
158 select HAVE_ARCH_MMAP_RND_BITS
159 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
160 select HAVE_ARCH_PREL32_RELOCATIONS
161 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
162 select HAVE_ARCH_SECCOMP_FILTER
163 select HAVE_ARCH_STACKLEAK
164 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
165 select HAVE_ARCH_TRACEHOOK
166 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
167 select HAVE_ARCH_VMAP_STACK
168 select HAVE_ARM_SMCCC
169 select HAVE_ASM_MODVERSIONS
171 select HAVE_C_RECORDMCOUNT
172 select HAVE_CMPXCHG_DOUBLE
173 select HAVE_CMPXCHG_LOCAL
174 select HAVE_CONTEXT_TRACKING
175 select HAVE_DEBUG_KMEMLEAK
176 select HAVE_DMA_CONTIGUOUS
177 select HAVE_DYNAMIC_FTRACE
178 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
179 if DYNAMIC_FTRACE_WITH_REGS
180 select HAVE_EFFICIENT_UNALIGNED_ACCESS
182 select HAVE_FTRACE_MCOUNT_RECORD
183 select HAVE_FUNCTION_TRACER
184 select HAVE_FUNCTION_ERROR_INJECTION
185 select HAVE_FUNCTION_GRAPH_TRACER
186 select HAVE_GCC_PLUGINS
187 select HAVE_HW_BREAKPOINT if PERF_EVENTS
188 select HAVE_IRQ_TIME_ACCOUNTING
191 select HAVE_PATA_PLATFORM
192 select HAVE_PERF_EVENTS
193 select HAVE_PERF_REGS
194 select HAVE_PERF_USER_STACK_DUMP
195 select HAVE_PREEMPT_DYNAMIC_KEY
196 select HAVE_REGS_AND_STACK_ACCESS_API
197 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
198 select HAVE_FUNCTION_ARG_ACCESS_API
199 select MMU_GATHER_RCU_TABLE_FREE
201 select HAVE_STACKPROTECTOR
202 select HAVE_SYSCALL_TRACEPOINTS
204 select HAVE_KRETPROBES
205 select HAVE_GENERIC_VDSO
206 select IOMMU_DMA if IOMMU_SUPPORT
208 select IRQ_FORCED_THREADING
209 select KASAN_VMALLOC if KASAN
210 select MODULES_USE_ELF_RELA
211 select NEED_DMA_MAP_STATE
212 select NEED_SG_DMA_LENGTH
214 select OF_EARLY_FLATTREE
215 select PCI_DOMAINS_GENERIC if PCI
216 select PCI_ECAM if (ACPI && PCI)
217 select PCI_SYSCALL if PCI
222 select SYSCTL_EXCEPTION_TRACE
223 select THREAD_INFO_IN_TASK
224 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
225 select TRACE_IRQFLAGS_SUPPORT
227 ARM 64-bit (AArch64) Linux support.
229 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
231 # https://github.com/ClangBuiltLinux/linux/issues/1507
232 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
233 select HAVE_DYNAMIC_FTRACE_WITH_REGS
235 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS
237 depends on $(cc-option,-fpatchable-function-entry=2)
238 select HAVE_DYNAMIC_FTRACE_WITH_REGS
246 config ARM64_PAGE_SHIFT
248 default 16 if ARM64_64K_PAGES
249 default 14 if ARM64_16K_PAGES
252 config ARM64_CONT_PTE_SHIFT
254 default 5 if ARM64_64K_PAGES
255 default 7 if ARM64_16K_PAGES
258 config ARM64_CONT_PMD_SHIFT
260 default 5 if ARM64_64K_PAGES
261 default 5 if ARM64_16K_PAGES
264 config ARCH_MMAP_RND_BITS_MIN
265 default 14 if ARM64_64K_PAGES
266 default 16 if ARM64_16K_PAGES
269 # max bits determined by the following formula:
270 # VA_BITS - PAGE_SHIFT - 3
271 config ARCH_MMAP_RND_BITS_MAX
272 default 19 if ARM64_VA_BITS=36
273 default 24 if ARM64_VA_BITS=39
274 default 27 if ARM64_VA_BITS=42
275 default 30 if ARM64_VA_BITS=47
276 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
277 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
278 default 33 if ARM64_VA_BITS=48
279 default 14 if ARM64_64K_PAGES
280 default 16 if ARM64_16K_PAGES
283 config ARCH_MMAP_RND_COMPAT_BITS_MIN
284 default 7 if ARM64_64K_PAGES
285 default 9 if ARM64_16K_PAGES
288 config ARCH_MMAP_RND_COMPAT_BITS_MAX
294 config STACKTRACE_SUPPORT
297 config ILLEGAL_POINTER_VALUE
299 default 0xdead000000000000
301 config LOCKDEP_SUPPORT
308 config GENERIC_BUG_RELATIVE_POINTERS
310 depends on GENERIC_BUG
312 config GENERIC_HWEIGHT
318 config GENERIC_CALIBRATE_DELAY
321 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
327 config KERNEL_MODE_NEON
330 config FIX_EARLYCON_MEM
333 config PGTABLE_LEVELS
335 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
336 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
337 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
338 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
339 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
340 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
342 config ARCH_SUPPORTS_UPROBES
345 config ARCH_PROC_KCORE_TEXT
348 config BROKEN_GAS_INST
349 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
351 config KASAN_SHADOW_OFFSET
353 depends on KASAN_GENERIC || KASAN_SW_TAGS
354 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
355 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
356 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
357 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
358 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
359 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
360 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
361 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
362 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
363 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
364 default 0xffffffffffffffff
366 source "arch/arm64/Kconfig.platforms"
368 menu "Kernel Features"
370 menu "ARM errata workarounds via the alternatives framework"
372 config ARM64_WORKAROUND_CLEAN_CACHE
375 config ARM64_ERRATUM_826319
376 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
378 select ARM64_WORKAROUND_CLEAN_CACHE
380 This option adds an alternative code sequence to work around ARM
381 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
382 AXI master interface and an L2 cache.
384 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
385 and is unable to accept a certain write via this interface, it will
386 not progress on read data presented on the read data channel and the
389 The workaround promotes data cache clean instructions to
390 data cache clean-and-invalidate.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_827319
398 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
400 select ARM64_WORKAROUND_CLEAN_CACHE
402 This option adds an alternative code sequence to work around ARM
403 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
404 master interface and an L2 cache.
406 Under certain conditions this erratum can cause a clean line eviction
407 to occur at the same time as another transaction to the same address
408 on the AMBA 5 CHI interface, which can cause data corruption if the
409 interconnect reorders the two transactions.
411 The workaround promotes data cache clean instructions to
412 data cache clean-and-invalidate.
413 Please note that this does not necessarily enable the workaround,
414 as it depends on the alternative framework, which will only patch
415 the kernel if an affected CPU is detected.
419 config ARM64_ERRATUM_824069
420 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
422 select ARM64_WORKAROUND_CLEAN_CACHE
424 This option adds an alternative code sequence to work around ARM
425 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
426 to a coherent interconnect.
428 If a Cortex-A53 processor is executing a store or prefetch for
429 write instruction at the same time as a processor in another
430 cluster is executing a cache maintenance operation to the same
431 address, then this erratum might cause a clean cache line to be
432 incorrectly marked as dirty.
434 The workaround promotes data cache clean instructions to
435 data cache clean-and-invalidate.
436 Please note that this option does not necessarily enable the
437 workaround, as it depends on the alternative framework, which will
438 only patch the kernel if an affected CPU is detected.
442 config ARM64_ERRATUM_819472
443 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
445 select ARM64_WORKAROUND_CLEAN_CACHE
447 This option adds an alternative code sequence to work around ARM
448 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
449 present when it is connected to a coherent interconnect.
451 If the processor is executing a load and store exclusive sequence at
452 the same time as a processor in another cluster is executing a cache
453 maintenance operation to the same address, then this erratum might
454 cause data corruption.
456 The workaround promotes data cache clean instructions to
457 data cache clean-and-invalidate.
458 Please note that this does not necessarily enable the workaround,
459 as it depends on the alternative framework, which will only patch
460 the kernel if an affected CPU is detected.
464 config ARM64_ERRATUM_832075
465 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
468 This option adds an alternative code sequence to work around ARM
469 erratum 832075 on Cortex-A57 parts up to r1p2.
471 Affected Cortex-A57 parts might deadlock when exclusive load/store
472 instructions to Write-Back memory are mixed with Device loads.
474 The workaround is to promote device loads to use Load-Acquire
476 Please note that this does not necessarily enable the workaround,
477 as it depends on the alternative framework, which will only patch
478 the kernel if an affected CPU is detected.
482 config ARM64_ERRATUM_834220
483 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
487 This option adds an alternative code sequence to work around ARM
488 erratum 834220 on Cortex-A57 parts up to r1p2.
490 Affected Cortex-A57 parts might report a Stage 2 translation
491 fault as the result of a Stage 1 fault for load crossing a
492 page boundary when there is a permission or device memory
493 alignment fault at Stage 1 and a translation fault at Stage 2.
495 The workaround is to verify that the Stage 1 translation
496 doesn't generate a fault before handling the Stage 2 fault.
497 Please note that this does not necessarily enable the workaround,
498 as it depends on the alternative framework, which will only patch
499 the kernel if an affected CPU is detected.
503 config ARM64_ERRATUM_845719
504 bool "Cortex-A53: 845719: a load might read incorrect data"
508 This option adds an alternative code sequence to work around ARM
509 erratum 845719 on Cortex-A53 parts up to r0p4.
511 When running a compat (AArch32) userspace on an affected Cortex-A53
512 part, a load at EL0 from a virtual address that matches the bottom 32
513 bits of the virtual address used by a recent load at (AArch64) EL1
514 might return incorrect data.
516 The workaround is to write the contextidr_el1 register on exception
517 return to a 32-bit task.
518 Please note that this does not necessarily enable the workaround,
519 as it depends on the alternative framework, which will only patch
520 the kernel if an affected CPU is detected.
524 config ARM64_ERRATUM_843419
525 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
527 select ARM64_MODULE_PLTS if MODULES
529 This option links the kernel with '--fix-cortex-a53-843419' and
530 enables PLT support to replace certain ADRP instructions, which can
531 cause subsequent memory accesses to use an incorrect address on
532 Cortex-A53 parts up to r0p4.
536 config ARM64_LD_HAS_FIX_ERRATUM_843419
537 def_bool $(ld-option,--fix-cortex-a53-843419)
539 config ARM64_ERRATUM_1024718
540 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
543 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
545 Affected Cortex-A55 cores (all revisions) could cause incorrect
546 update of the hardware dirty bit when the DBM/AP bits are updated
547 without a break-before-make. The workaround is to disable the usage
548 of hardware DBM locally on the affected cores. CPUs not affected by
549 this erratum will continue to use the feature.
553 config ARM64_ERRATUM_1418040
554 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
558 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
559 errata 1188873 and 1418040.
561 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
562 cause register corruption when accessing the timer registers
563 from AArch32 userspace.
567 config ARM64_WORKAROUND_SPECULATIVE_AT
570 config ARM64_ERRATUM_1165522
571 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
573 select ARM64_WORKAROUND_SPECULATIVE_AT
575 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
577 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
578 corrupted TLBs by speculating an AT instruction during a guest
583 config ARM64_ERRATUM_1319367
584 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
586 select ARM64_WORKAROUND_SPECULATIVE_AT
588 This option adds work arounds for ARM Cortex-A57 erratum 1319537
589 and A72 erratum 1319367
591 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
592 speculating an AT instruction during a guest context switch.
596 config ARM64_ERRATUM_1530923
597 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
599 select ARM64_WORKAROUND_SPECULATIVE_AT
601 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
603 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
604 corrupted TLBs by speculating an AT instruction during a guest
609 config ARM64_WORKAROUND_REPEAT_TLBI
612 config ARM64_ERRATUM_1286807
613 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
615 select ARM64_WORKAROUND_REPEAT_TLBI
617 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
619 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
620 address for a cacheable mapping of a location is being
621 accessed by a core while another core is remapping the virtual
622 address to a new physical page using the recommended
623 break-before-make sequence, then under very rare circumstances
624 TLBI+DSB completes before a read using the translation being
625 invalidated has been observed by other observers. The
626 workaround repeats the TLBI+DSB operation.
628 config ARM64_ERRATUM_1463225
629 bool "Cortex-A76: Software Step might prevent interrupt recognition"
632 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
634 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
635 of a system call instruction (SVC) can prevent recognition of
636 subsequent interrupts when software stepping is disabled in the
637 exception handler of the system call and either kernel debugging
638 is enabled or VHE is in use.
640 Work around the erratum by triggering a dummy step exception
641 when handling a system call from a task that is being stepped
642 in a VHE configuration of the kernel.
646 config ARM64_ERRATUM_1542419
647 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
650 This option adds a workaround for ARM Neoverse-N1 erratum
653 Affected Neoverse-N1 cores could execute a stale instruction when
654 modified by another CPU. The workaround depends on a firmware
657 Workaround the issue by hiding the DIC feature from EL0. This
658 forces user-space to perform cache maintenance.
662 config ARM64_ERRATUM_1508412
663 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
666 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
668 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
669 of a store-exclusive or read of PAR_EL1 and a load with device or
670 non-cacheable memory attributes. The workaround depends on a firmware
673 KVM guests must also have the workaround implemented or they can
676 Work around the issue by inserting DMB SY barriers around PAR_EL1
677 register reads and warning KVM users. The DMB barrier is sufficient
678 to prevent a speculative PAR_EL1 read.
682 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
685 config ARM64_ERRATUM_2051678
686 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
689 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
690 Affected Cortex-A510 might not respect the ordering rules for
691 hardware update of the page table's dirty bit. The workaround
692 is to not enable the feature on affected CPUs.
696 config ARM64_ERRATUM_2077057
697 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
700 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
701 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
702 expected, but a Pointer Authentication trap is taken instead. The
703 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
704 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
706 This can only happen when EL2 is stepping EL1.
708 When these conditions occur, the SPSR_EL2 value is unchanged from the
709 previous guest entry, and can be restored from the in-memory copy.
713 config ARM64_ERRATUM_2119858
714 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
716 depends on CORESIGHT_TRBE
717 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
719 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
721 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
722 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
723 the event of a WRAP event.
725 Work around the issue by always making sure we move the TRBPTR_EL1 by
726 256 bytes before enabling the buffer and filling the first 256 bytes of
727 the buffer with ETM ignore packets upon disabling.
731 config ARM64_ERRATUM_2139208
732 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
734 depends on CORESIGHT_TRBE
735 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
737 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
739 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
740 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
741 the event of a WRAP event.
743 Work around the issue by always making sure we move the TRBPTR_EL1 by
744 256 bytes before enabling the buffer and filling the first 256 bytes of
745 the buffer with ETM ignore packets upon disabling.
749 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
752 config ARM64_ERRATUM_2054223
753 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
755 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
757 Enable workaround for ARM Cortex-A710 erratum 2054223
759 Affected cores may fail to flush the trace data on a TSB instruction, when
760 the PE is in trace prohibited state. This will cause losing a few bytes
763 Workaround is to issue two TSB consecutively on affected cores.
767 config ARM64_ERRATUM_2067961
768 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
770 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
772 Enable workaround for ARM Neoverse-N2 erratum 2067961
774 Affected cores may fail to flush the trace data on a TSB instruction, when
775 the PE is in trace prohibited state. This will cause losing a few bytes
778 Workaround is to issue two TSB consecutively on affected cores.
782 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
785 config ARM64_ERRATUM_2253138
786 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
787 depends on CORESIGHT_TRBE
789 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
791 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
793 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
794 for TRBE. Under some conditions, the TRBE might generate a write to the next
795 virtually addressed page following the last page of the TRBE address space
796 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
798 Work around this in the driver by always making sure that there is a
799 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
803 config ARM64_ERRATUM_2224489
804 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
805 depends on CORESIGHT_TRBE
807 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
809 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
811 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
812 for TRBE. Under some conditions, the TRBE might generate a write to the next
813 virtually addressed page following the last page of the TRBE address space
814 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
816 Work around this in the driver by always making sure that there is a
817 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
821 config ARM64_ERRATUM_2064142
822 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
823 depends on CORESIGHT_TRBE
826 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
828 Affected Cortex-A510 core might fail to write into system registers after the
829 TRBE has been disabled. Under some conditions after the TRBE has been disabled
830 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
831 and TRBTRG_EL1 will be ignored and will not be effected.
833 Work around this in the driver by executing TSB CSYNC and DSB after collection
834 is stopped and before performing a system register write to one of the affected
839 config ARM64_ERRATUM_2038923
840 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
841 depends on CORESIGHT_TRBE
844 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
846 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
847 prohibited within the CPU. As a result, the trace buffer or trace buffer state
848 might be corrupted. This happens after TRBE buffer has been enabled by setting
849 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
850 execution changes from a context, in which trace is prohibited to one where it
851 isn't, or vice versa. In these mentioned conditions, the view of whether trace
852 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
853 the trace buffer state might be corrupted.
855 Work around this in the driver by preventing an inconsistent view of whether the
856 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
857 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
858 two ISB instructions if no ERET is to take place.
862 config ARM64_ERRATUM_1902691
863 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
864 depends on CORESIGHT_TRBE
867 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
869 Affected Cortex-A510 core might cause trace data corruption, when being written
870 into the memory. Effectively TRBE is broken and hence cannot be used to capture
873 Work around this problem in the driver by just preventing TRBE initialization on
874 affected cpus. The firmware must have disabled the access to TRBE for the kernel
875 on such implementations. This will cover the kernel for any firmware that doesn't
880 config CAVIUM_ERRATUM_22375
881 bool "Cavium erratum 22375, 24313"
884 Enable workaround for errata 22375 and 24313.
886 This implements two gicv3-its errata workarounds for ThunderX. Both
887 with a small impact affecting only ITS table allocation.
889 erratum 22375: only alloc 8MB table size
890 erratum 24313: ignore memory access type
892 The fixes are in ITS initialization and basically ignore memory access
893 type and table size provided by the TYPER and BASER registers.
897 config CAVIUM_ERRATUM_23144
898 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
902 ITS SYNC command hang for cross node io and collections/cpu mapping.
906 config CAVIUM_ERRATUM_23154
907 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
910 The ThunderX GICv3 implementation requires a modified version for
911 reading the IAR status to ensure data synchronization
912 (access to icc_iar1_el1 is not sync'ed before and after).
914 It also suffers from erratum 38545 (also present on Marvell's
915 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
916 spuriously presented to the CPU interface.
920 config CAVIUM_ERRATUM_27456
921 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
924 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
925 instructions may cause the icache to become corrupted if it
926 contains data for a non-current ASID. The fix is to
927 invalidate the icache when changing the mm context.
931 config CAVIUM_ERRATUM_30115
932 bool "Cavium erratum 30115: Guest may disable interrupts in host"
935 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
936 1.2, and T83 Pass 1.0, KVM guest execution may disable
937 interrupts in host. Trapping both GICv3 group-0 and group-1
938 accesses sidesteps the issue.
942 config CAVIUM_TX2_ERRATUM_219
943 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
946 On Cavium ThunderX2, a load, store or prefetch instruction between a
947 TTBR update and the corresponding context synchronizing operation can
948 cause a spurious Data Abort to be delivered to any hardware thread in
951 Work around the issue by avoiding the problematic code sequence and
952 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
953 trap handler performs the corresponding register access, skips the
954 instruction and ensures context synchronization by virtue of the
959 config FUJITSU_ERRATUM_010001
960 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
963 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
964 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
965 accesses may cause undefined fault (Data abort, DFSC=0b111111).
966 This fault occurs under a specific hardware condition when a
967 load/store instruction performs an address translation using:
968 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
969 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
970 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
971 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
973 The workaround is to ensure these bits are clear in TCR_ELx.
974 The workaround only affects the Fujitsu-A64FX.
978 config HISILICON_ERRATUM_161600802
979 bool "Hip07 161600802: Erroneous redistributor VLPI base"
982 The HiSilicon Hip07 SoC uses the wrong redistributor base
983 when issued ITS commands such as VMOVP and VMAPP, and requires
984 a 128kB offset to be applied to the target address in this commands.
988 config QCOM_FALKOR_ERRATUM_1003
989 bool "Falkor E1003: Incorrect translation due to ASID change"
992 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
993 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
994 in TTBR1_EL1, this situation only occurs in the entry trampoline and
995 then only for entries in the walk cache, since the leaf translation
996 is unchanged. Work around the erratum by invalidating the walk cache
997 entries for the trampoline before entering the kernel proper.
999 config QCOM_FALKOR_ERRATUM_1009
1000 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1002 select ARM64_WORKAROUND_REPEAT_TLBI
1004 On Falkor v1, the CPU may prematurely complete a DSB following a
1005 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1006 one more time to fix the issue.
1010 config QCOM_QDF2400_ERRATUM_0065
1011 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1014 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1015 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1016 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1020 config QCOM_FALKOR_ERRATUM_E1041
1021 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1024 Falkor CPU may speculatively fetch instructions from an improper
1025 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1026 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1030 config NVIDIA_CARMEL_CNP_ERRATUM
1031 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1034 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1035 invalidate shared TLB entries installed by a different core, as it would
1036 on standard ARM cores.
1040 config SOCIONEXT_SYNQUACER_PREITS
1041 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1044 Socionext Synquacer SoCs implement a separate h/w block to generate
1045 MSI doorbell writes with non-zero values for the device ID.
1049 endmenu # "ARM errata workarounds via the alternatives framework"
1053 default ARM64_4K_PAGES
1055 Page size (translation granule) configuration.
1057 config ARM64_4K_PAGES
1060 This feature enables 4KB pages support.
1062 config ARM64_16K_PAGES
1065 The system will use 16KB pages support. AArch32 emulation
1066 requires applications compiled with 16K (or a multiple of 16K)
1069 config ARM64_64K_PAGES
1072 This feature enables 64KB pages support (4KB by default)
1073 allowing only two levels of page tables and faster TLB
1074 look-up. AArch32 emulation requires applications compiled
1075 with 64K aligned segments.
1080 prompt "Virtual address space size"
1081 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1082 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1083 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1085 Allows choosing one of multiple possible virtual address
1086 space sizes. The level of translation table is determined by
1087 a combination of page size and virtual address space size.
1089 config ARM64_VA_BITS_36
1090 bool "36-bit" if EXPERT
1091 depends on ARM64_16K_PAGES
1093 config ARM64_VA_BITS_39
1095 depends on ARM64_4K_PAGES
1097 config ARM64_VA_BITS_42
1099 depends on ARM64_64K_PAGES
1101 config ARM64_VA_BITS_47
1103 depends on ARM64_16K_PAGES
1105 config ARM64_VA_BITS_48
1108 config ARM64_VA_BITS_52
1110 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1112 Enable 52-bit virtual addressing for userspace when explicitly
1113 requested via a hint to mmap(). The kernel will also use 52-bit
1114 virtual addresses for its own mappings (provided HW support for
1115 this feature is available, otherwise it reverts to 48-bit).
1117 NOTE: Enabling 52-bit virtual addressing in conjunction with
1118 ARMv8.3 Pointer Authentication will result in the PAC being
1119 reduced from 7 bits to 3 bits, which may have a significant
1120 impact on its susceptibility to brute-force attacks.
1122 If unsure, select 48-bit virtual addressing instead.
1126 config ARM64_FORCE_52BIT
1127 bool "Force 52-bit virtual addresses for userspace"
1128 depends on ARM64_VA_BITS_52 && EXPERT
1130 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1131 to maintain compatibility with older software by providing 48-bit VAs
1132 unless a hint is supplied to mmap.
1134 This configuration option disables the 48-bit compatibility logic, and
1135 forces all userspace addresses to be 52-bit on HW that supports it. One
1136 should only enable this configuration option for stress testing userspace
1137 memory management code. If unsure say N here.
1139 config ARM64_VA_BITS
1141 default 36 if ARM64_VA_BITS_36
1142 default 39 if ARM64_VA_BITS_39
1143 default 42 if ARM64_VA_BITS_42
1144 default 47 if ARM64_VA_BITS_47
1145 default 48 if ARM64_VA_BITS_48
1146 default 52 if ARM64_VA_BITS_52
1149 prompt "Physical address space size"
1150 default ARM64_PA_BITS_48
1152 Choose the maximum physical address range that the kernel will
1155 config ARM64_PA_BITS_48
1158 config ARM64_PA_BITS_52
1159 bool "52-bit (ARMv8.2)"
1160 depends on ARM64_64K_PAGES
1161 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1163 Enable support for a 52-bit physical address space, introduced as
1164 part of the ARMv8.2-LPA extension.
1166 With this enabled, the kernel will also continue to work on CPUs that
1167 do not support ARMv8.2-LPA, but with some added memory overhead (and
1168 minor performance overhead).
1172 config ARM64_PA_BITS
1174 default 48 if ARM64_PA_BITS_48
1175 default 52 if ARM64_PA_BITS_52
1179 default CPU_LITTLE_ENDIAN
1181 Select the endianness of data accesses performed by the CPU. Userspace
1182 applications will need to be compiled and linked for the endianness
1183 that is selected here.
1185 config CPU_BIG_ENDIAN
1186 bool "Build big-endian kernel"
1187 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1189 Say Y if you plan on running a kernel with a big-endian userspace.
1191 config CPU_LITTLE_ENDIAN
1192 bool "Build little-endian kernel"
1194 Say Y if you plan on running a kernel with a little-endian userspace.
1195 This is usually the case for distributions targeting arm64.
1200 bool "Multi-core scheduler support"
1202 Multi-core scheduler support improves the CPU scheduler's decision
1203 making when dealing with multi-core CPU chips at a cost of slightly
1204 increased overhead in some places. If unsure say N here.
1206 config SCHED_CLUSTER
1207 bool "Cluster scheduler support"
1209 Cluster scheduler support improves the CPU scheduler's decision
1210 making when dealing with machines that have clusters of CPUs.
1211 Cluster usually means a couple of CPUs which are placed closely
1212 by sharing mid-level caches, last-level cache tags or internal
1216 bool "SMT scheduler support"
1218 Improves the CPU scheduler's decision making when dealing with
1219 MultiThreading at a cost of slightly increased overhead in some
1220 places. If unsure say N here.
1223 int "Maximum number of CPUs (2-4096)"
1228 bool "Support for hot-pluggable CPUs"
1229 select GENERIC_IRQ_MIGRATION
1231 Say Y here to experiment with turning CPUs off and on. CPUs
1232 can be controlled through /sys/devices/system/cpu.
1234 # Common NUMA Features
1236 bool "NUMA Memory Allocation and Scheduler Support"
1237 select GENERIC_ARCH_NUMA
1238 select ACPI_NUMA if ACPI
1240 select HAVE_SETUP_PER_CPU_AREA
1241 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1242 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1243 select USE_PERCPU_NUMA_NODE_ID
1245 Enable NUMA (Non-Uniform Memory Access) support.
1247 The kernel will try to allocate memory used by a CPU on the
1248 local memory of the CPU and add some more
1249 NUMA awareness to the kernel.
1252 int "Maximum NUMA Nodes (as a power of 2)"
1257 Specify the maximum number of NUMA Nodes available on the target
1258 system. Increases memory reserved to accommodate various tables.
1260 source "kernel/Kconfig.hz"
1262 config ARCH_SPARSEMEM_ENABLE
1264 select SPARSEMEM_VMEMMAP_ENABLE
1265 select SPARSEMEM_VMEMMAP
1267 config HW_PERF_EVENTS
1271 # Supported by clang >= 7.0 or GCC >= 12.0.0
1272 config CC_HAVE_SHADOW_CALL_STACK
1273 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1276 bool "Enable paravirtualization code"
1278 This changes the kernel so it can modify itself when it is run
1279 under a hypervisor, potentially improving performance significantly
1280 over full virtualization.
1282 config PARAVIRT_TIME_ACCOUNTING
1283 bool "Paravirtual steal time accounting"
1286 Select this option to enable fine granularity task steal time
1287 accounting. Time spent executing other tasks in parallel with
1288 the current vCPU is discounted from the vCPU power. To account for
1289 that, there can be a small performance impact.
1291 If in doubt, say N here.
1294 depends on PM_SLEEP_SMP
1296 bool "kexec system call"
1298 kexec is a system call that implements the ability to shutdown your
1299 current kernel, and to start another kernel. It is like a reboot
1300 but it is independent of the system firmware. And like a reboot
1301 you can start any kernel with it, not just Linux.
1304 bool "kexec file based system call"
1306 select HAVE_IMA_KEXEC if IMA
1308 This is new version of kexec system call. This system call is
1309 file based and takes file descriptors as system call argument
1310 for kernel and initramfs as opposed to list of segments as
1311 accepted by previous system call.
1314 bool "Verify kernel signature during kexec_file_load() syscall"
1315 depends on KEXEC_FILE
1317 Select this option to verify a signature with loaded kernel
1318 image. If configured, any attempt of loading a image without
1319 valid signature will fail.
1321 In addition to that option, you need to enable signature
1322 verification for the corresponding kernel image type being
1323 loaded in order for this to work.
1325 config KEXEC_IMAGE_VERIFY_SIG
1326 bool "Enable Image signature verification support"
1328 depends on KEXEC_SIG
1329 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1331 Enable Image signature verification support.
1333 comment "Support for PE file signature verification disabled"
1334 depends on KEXEC_SIG
1335 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1338 bool "Build kdump crash kernel"
1340 Generate crash dump after being started by kexec. This should
1341 be normally only set in special crash dump kernels which are
1342 loaded in the main kernel with kexec-tools into a specially
1343 reserved region and then later executed after a crash by
1346 For more details see Documentation/admin-guide/kdump/kdump.rst
1350 depends on HIBERNATION || KEXEC_CORE
1357 bool "Xen guest support on ARM64"
1358 depends on ARM64 && OF
1362 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1364 config FORCE_MAX_ZONEORDER
1366 default "14" if ARM64_64K_PAGES
1367 default "12" if ARM64_16K_PAGES
1370 The kernel memory allocator divides physically contiguous memory
1371 blocks into "zones", where each zone is a power of two number of
1372 pages. This option selects the largest power of two that the kernel
1373 keeps in the memory allocator. If you need to allocate very large
1374 blocks of physically contiguous memory, then you may need to
1375 increase this value.
1377 This config option is actually maximum order plus one. For example,
1378 a value of 11 means that the largest free memory block is 2^10 pages.
1380 We make sure that we can allocate upto a HugePage size for each configuration.
1382 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1384 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1385 4M allocations matching the default size used by generic code.
1387 config UNMAP_KERNEL_AT_EL0
1388 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1391 Speculation attacks against some high-performance processors can
1392 be used to bypass MMU permission checks and leak kernel data to
1393 userspace. This can be defended against by unmapping the kernel
1394 when running in userspace, mapping it back in on exception entry
1395 via a trampoline page in the vector table.
1399 config MITIGATE_SPECTRE_BRANCH_HISTORY
1400 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1403 Speculation attacks against some high-performance processors can
1404 make use of branch history to influence future speculation.
1405 When taking an exception from user-space, a sequence of branches
1406 or a firmware call overwrites the branch history.
1408 config RODATA_FULL_DEFAULT_ENABLED
1409 bool "Apply r/o permissions of VM areas also to their linear aliases"
1412 Apply read-only attributes of VM areas to the linear alias of
1413 the backing pages as well. This prevents code or read-only data
1414 from being modified (inadvertently or intentionally) via another
1415 mapping of the same memory page. This additional enhancement can
1416 be turned off at runtime by passing rodata=[off|on] (and turned on
1417 with rodata=full if this option is set to 'n')
1419 This requires the linear region to be mapped down to pages,
1420 which may adversely affect performance in some cases.
1422 config ARM64_SW_TTBR0_PAN
1423 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1425 Enabling this option prevents the kernel from accessing
1426 user-space memory directly by pointing TTBR0_EL1 to a reserved
1427 zeroed area and reserved ASID. The user access routines
1428 restore the valid TTBR0_EL1 temporarily.
1430 config ARM64_TAGGED_ADDR_ABI
1431 bool "Enable the tagged user addresses syscall ABI"
1434 When this option is enabled, user applications can opt in to a
1435 relaxed ABI via prctl() allowing tagged addresses to be passed
1436 to system calls as pointer arguments. For details, see
1437 Documentation/arm64/tagged-address-abi.rst.
1440 bool "Kernel support for 32-bit EL0"
1441 depends on ARM64_4K_PAGES || EXPERT
1443 select OLD_SIGSUSPEND3
1444 select COMPAT_OLD_SIGACTION
1446 This option enables support for a 32-bit EL0 running under a 64-bit
1447 kernel at EL1. AArch32-specific components such as system calls,
1448 the user helper functions, VFP support and the ptrace interface are
1449 handled appropriately by the kernel.
1451 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1452 that you will only be able to execute AArch32 binaries that were compiled
1453 with page size aligned segments.
1455 If you want to execute 32-bit userspace applications, say Y.
1459 config KUSER_HELPERS
1460 bool "Enable kuser helpers page for 32-bit applications"
1463 Warning: disabling this option may break 32-bit user programs.
1465 Provide kuser helpers to compat tasks. The kernel provides
1466 helper code to userspace in read only form at a fixed location
1467 to allow userspace to be independent of the CPU type fitted to
1468 the system. This permits binaries to be run on ARMv4 through
1469 to ARMv8 without modification.
1471 See Documentation/arm/kernel_user_helpers.rst for details.
1473 However, the fixed address nature of these helpers can be used
1474 by ROP (return orientated programming) authors when creating
1477 If all of the binaries and libraries which run on your platform
1478 are built specifically for your platform, and make no use of
1479 these helpers, then you can turn this option off to hinder
1480 such exploits. However, in that case, if a binary or library
1481 relying on those helpers is run, it will not function correctly.
1483 Say N here only if you are absolutely certain that you do not
1484 need these helpers; otherwise, the safe option is to say Y.
1487 bool "Enable vDSO for 32-bit applications"
1488 depends on !CPU_BIG_ENDIAN
1489 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1490 select GENERIC_COMPAT_VDSO
1493 Place in the process address space of 32-bit applications an
1494 ELF shared object providing fast implementations of gettimeofday
1497 You must have a 32-bit build of glibc 2.22 or later for programs
1498 to seamlessly take advantage of this.
1500 config THUMB2_COMPAT_VDSO
1501 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1502 depends on COMPAT_VDSO
1505 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1506 otherwise with '-marm'.
1508 menuconfig ARMV8_DEPRECATED
1509 bool "Emulate deprecated/obsolete ARMv8 instructions"
1512 Legacy software support may require certain instructions
1513 that have been deprecated or obsoleted in the architecture.
1515 Enable this config to enable selective emulation of these
1522 config SWP_EMULATION
1523 bool "Emulate SWP/SWPB instructions"
1525 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1526 they are always undefined. Say Y here to enable software
1527 emulation of these instructions for userspace using LDXR/STXR.
1528 This feature can be controlled at runtime with the abi.swp
1529 sysctl which is disabled by default.
1531 In some older versions of glibc [<=2.8] SWP is used during futex
1532 trylock() operations with the assumption that the code will not
1533 be preempted. This invalid assumption may be more likely to fail
1534 with SWP emulation enabled, leading to deadlock of the user
1537 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1538 on an external transaction monitoring block called a global
1539 monitor to maintain update atomicity. If your system does not
1540 implement a global monitor, this option can cause programs that
1541 perform SWP operations to uncached memory to deadlock.
1545 config CP15_BARRIER_EMULATION
1546 bool "Emulate CP15 Barrier instructions"
1548 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1549 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1550 strongly recommended to use the ISB, DSB, and DMB
1551 instructions instead.
1553 Say Y here to enable software emulation of these
1554 instructions for AArch32 userspace code. When this option is
1555 enabled, CP15 barrier usage is traced which can help
1556 identify software that needs updating. This feature can be
1557 controlled at runtime with the abi.cp15_barrier sysctl.
1561 config SETEND_EMULATION
1562 bool "Emulate SETEND instruction"
1564 The SETEND instruction alters the data-endianness of the
1565 AArch32 EL0, and is deprecated in ARMv8.
1567 Say Y here to enable software emulation of the instruction
1568 for AArch32 userspace code. This feature can be controlled
1569 at runtime with the abi.setend sysctl.
1571 Note: All the cpus on the system must have mixed endian support at EL0
1572 for this feature to be enabled. If a new CPU - which doesn't support mixed
1573 endian - is hotplugged in after this feature has been enabled, there could
1574 be unexpected results in the applications.
1577 endif # ARMV8_DEPRECATED
1581 menu "ARMv8.1 architectural features"
1583 config ARM64_HW_AFDBM
1584 bool "Support for hardware updates of the Access and Dirty page flags"
1587 The ARMv8.1 architecture extensions introduce support for
1588 hardware updates of the access and dirty information in page
1589 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1590 capable processors, accesses to pages with PTE_AF cleared will
1591 set this bit instead of raising an access flag fault.
1592 Similarly, writes to read-only pages with the DBM bit set will
1593 clear the read-only bit (AP[2]) instead of raising a
1596 Kernels built with this configuration option enabled continue
1597 to work on pre-ARMv8.1 hardware and the performance impact is
1598 minimal. If unsure, say Y.
1601 bool "Enable support for Privileged Access Never (PAN)"
1604 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1605 prevents the kernel or hypervisor from accessing user-space (EL0)
1608 Choosing this option will cause any unprotected (not using
1609 copy_to_user et al) memory access to fail with a permission fault.
1611 The feature is detected at runtime, and will remain as a 'nop'
1612 instruction if the cpu does not implement the feature.
1615 def_bool $(as-instr,.arch_extension rcpc)
1617 config AS_HAS_LSE_ATOMICS
1618 def_bool $(as-instr,.arch_extension lse)
1620 config ARM64_LSE_ATOMICS
1622 default ARM64_USE_LSE_ATOMICS
1623 depends on AS_HAS_LSE_ATOMICS
1625 config ARM64_USE_LSE_ATOMICS
1626 bool "Atomic instructions"
1627 depends on JUMP_LABEL
1630 As part of the Large System Extensions, ARMv8.1 introduces new
1631 atomic instructions that are designed specifically to scale in
1634 Say Y here to make use of these instructions for the in-kernel
1635 atomic routines. This incurs a small overhead on CPUs that do
1636 not support these instructions and requires the kernel to be
1637 built with binutils >= 2.25 in order for the new instructions
1640 endmenu # "ARMv8.1 architectural features"
1642 menu "ARMv8.2 architectural features"
1644 config AS_HAS_ARMV8_2
1645 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1648 def_bool $(as-instr,.arch armv8.2-a+sha3)
1651 bool "Enable support for persistent memory"
1652 select ARCH_HAS_PMEM_API
1653 select ARCH_HAS_UACCESS_FLUSHCACHE
1655 Say Y to enable support for the persistent memory API based on the
1656 ARMv8.2 DCPoP feature.
1658 The feature is detected at runtime, and the kernel will use DC CVAC
1659 operations if DC CVAP is not supported (following the behaviour of
1660 DC CVAP itself if the system does not define a point of persistence).
1662 config ARM64_RAS_EXTN
1663 bool "Enable support for RAS CPU Extensions"
1666 CPUs that support the Reliability, Availability and Serviceability
1667 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1668 errors, classify them and report them to software.
1670 On CPUs with these extensions system software can use additional
1671 barriers to determine if faults are pending and read the
1672 classification from a new set of registers.
1674 Selecting this feature will allow the kernel to use these barriers
1675 and access the new registers if the system supports the extension.
1676 Platform RAS features may additionally depend on firmware support.
1679 bool "Enable support for Common Not Private (CNP) translations"
1681 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1683 Common Not Private (CNP) allows translation table entries to
1684 be shared between different PEs in the same inner shareable
1685 domain, so the hardware can use this fact to optimise the
1686 caching of such entries in the TLB.
1688 Selecting this option allows the CNP feature to be detected
1689 at runtime, and does not affect PEs that do not implement
1692 endmenu # "ARMv8.2 architectural features"
1694 menu "ARMv8.3 architectural features"
1696 config ARM64_PTR_AUTH
1697 bool "Enable support for pointer authentication"
1700 Pointer authentication (part of the ARMv8.3 Extensions) provides
1701 instructions for signing and authenticating pointers against secret
1702 keys, which can be used to mitigate Return Oriented Programming (ROP)
1705 This option enables these instructions at EL0 (i.e. for userspace).
1706 Choosing this option will cause the kernel to initialise secret keys
1707 for each process at exec() time, with these keys being
1708 context-switched along with the process.
1710 The feature is detected at runtime. If the feature is not present in
1711 hardware it will not be advertised to userspace/KVM guest nor will it
1714 If the feature is present on the boot CPU but not on a late CPU, then
1715 the late CPU will be parked. Also, if the boot CPU does not have
1716 address auth and the late CPU has then the late CPU will still boot
1717 but with the feature disabled. On such a system, this option should
1720 config ARM64_PTR_AUTH_KERNEL
1721 bool "Use pointer authentication for kernel"
1723 depends on ARM64_PTR_AUTH
1724 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1725 # Modern compilers insert a .note.gnu.property section note for PAC
1726 # which is only understood by binutils starting with version 2.33.1.
1727 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1728 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1729 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1731 If the compiler supports the -mbranch-protection or
1732 -msign-return-address flag (e.g. GCC 7 or later), then this option
1733 will cause the kernel itself to be compiled with return address
1734 protection. In this case, and if the target hardware is known to
1735 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1736 disabled with minimal loss of protection.
1738 This feature works with FUNCTION_GRAPH_TRACER option only if
1739 DYNAMIC_FTRACE_WITH_REGS is enabled.
1741 config CC_HAS_BRANCH_PROT_PAC_RET
1742 # GCC 9 or later, clang 8 or later
1743 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1745 config CC_HAS_SIGN_RETURN_ADDRESS
1747 def_bool $(cc-option,-msign-return-address=all)
1750 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1752 config AS_HAS_CFI_NEGATE_RA_STATE
1753 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1755 endmenu # "ARMv8.3 architectural features"
1757 menu "ARMv8.4 architectural features"
1759 config ARM64_AMU_EXTN
1760 bool "Enable support for the Activity Monitors Unit CPU extension"
1763 The activity monitors extension is an optional extension introduced
1764 by the ARMv8.4 CPU architecture. This enables support for version 1
1765 of the activity monitors architecture, AMUv1.
1767 To enable the use of this extension on CPUs that implement it, say Y.
1769 Note that for architectural reasons, firmware _must_ implement AMU
1770 support when running on CPUs that present the activity monitors
1771 extension. The required support is present in:
1772 * Version 1.5 and later of the ARM Trusted Firmware
1774 For kernels that have this configuration enabled but boot with broken
1775 firmware, you may need to say N here until the firmware is fixed.
1776 Otherwise you may experience firmware panics or lockups when
1777 accessing the counter registers. Even if you are not observing these
1778 symptoms, the values returned by the register reads might not
1779 correctly reflect reality. Most commonly, the value read will be 0,
1780 indicating that the counter is not enabled.
1782 config AS_HAS_ARMV8_4
1783 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1785 config ARM64_TLB_RANGE
1786 bool "Enable support for tlbi range feature"
1788 depends on AS_HAS_ARMV8_4
1790 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1791 range of input addresses.
1793 The feature introduces new assembly instructions, and they were
1794 support when binutils >= 2.30.
1796 endmenu # "ARMv8.4 architectural features"
1798 menu "ARMv8.5 architectural features"
1800 config AS_HAS_ARMV8_5
1801 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1804 bool "Branch Target Identification support"
1807 Branch Target Identification (part of the ARMv8.5 Extensions)
1808 provides a mechanism to limit the set of locations to which computed
1809 branch instructions such as BR or BLR can jump.
1811 To make use of BTI on CPUs that support it, say Y.
1813 BTI is intended to provide complementary protection to other control
1814 flow integrity protection mechanisms, such as the Pointer
1815 authentication mechanism provided as part of the ARMv8.3 Extensions.
1816 For this reason, it does not make sense to enable this option without
1817 also enabling support for pointer authentication. Thus, when
1818 enabling this option you should also select ARM64_PTR_AUTH=y.
1820 Userspace binaries must also be specifically compiled to make use of
1821 this mechanism. If you say N here or the hardware does not support
1822 BTI, such binaries can still run, but you get no additional
1823 enforcement of branch destinations.
1825 config ARM64_BTI_KERNEL
1826 bool "Use Branch Target Identification for kernel"
1828 depends on ARM64_BTI
1829 depends on ARM64_PTR_AUTH_KERNEL
1830 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1831 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1832 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1833 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1834 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1835 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
1837 Build the kernel with Branch Target Identification annotations
1838 and enable enforcement of this for kernel code. When this option
1839 is enabled and the system supports BTI all kernel code including
1840 modular code must have BTI enabled.
1842 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1843 # GCC 9 or later, clang 8 or later
1844 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1847 bool "Enable support for E0PD"
1850 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1851 that EL0 accesses made via TTBR1 always fault in constant time,
1852 providing similar benefits to KASLR as those provided by KPTI, but
1853 with lower overhead and without disrupting legitimate access to
1854 kernel memory such as SPE.
1856 This option enables E0PD for TTBR1 where available.
1859 bool "Enable support for random number generation"
1862 Random number generation (part of the ARMv8.5 Extensions)
1863 provides a high bandwidth, cryptographically secure
1864 hardware random number generator.
1866 config ARM64_AS_HAS_MTE
1867 # Initial support for MTE went in binutils 2.32.0, checked with
1868 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1869 # as a late addition to the final architecture spec (LDGM/STGM)
1870 # is only supported in the newer 2.32.x and 2.33 binutils
1871 # versions, hence the extra "stgm" instruction check below.
1872 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1875 bool "Memory Tagging Extension support"
1877 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1878 depends on AS_HAS_ARMV8_5
1879 depends on AS_HAS_LSE_ATOMICS
1880 # Required for tag checking in the uaccess routines
1881 depends on ARM64_PAN
1882 select ARCH_HAS_SUBPAGE_FAULTS
1883 select ARCH_USES_HIGH_VMA_FLAGS
1885 Memory Tagging (part of the ARMv8.5 Extensions) provides
1886 architectural support for run-time, always-on detection of
1887 various classes of memory error to aid with software debugging
1888 to eliminate vulnerabilities arising from memory-unsafe
1891 This option enables the support for the Memory Tagging
1892 Extension at EL0 (i.e. for userspace).
1894 Selecting this option allows the feature to be detected at
1895 runtime. Any secondary CPU not implementing this feature will
1896 not be allowed a late bring-up.
1898 Userspace binaries that want to use this feature must
1899 explicitly opt in. The mechanism for the userspace is
1902 Documentation/arm64/memory-tagging-extension.rst.
1904 endmenu # "ARMv8.5 architectural features"
1906 menu "ARMv8.7 architectural features"
1909 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
1911 depends on ARM64_PAN
1913 Enhanced Privileged Access Never (EPAN) allows Privileged
1914 Access Never to be used with Execute-only mappings.
1916 The feature is detected at runtime, and will remain disabled
1917 if the cpu does not implement the feature.
1918 endmenu # "ARMv8.7 architectural features"
1921 bool "ARM Scalable Vector Extension support"
1924 The Scalable Vector Extension (SVE) is an extension to the AArch64
1925 execution state which complements and extends the SIMD functionality
1926 of the base architecture to support much larger vectors and to enable
1927 additional vectorisation opportunities.
1929 To enable use of this extension on CPUs that implement it, say Y.
1931 On CPUs that support the SVE2 extensions, this option will enable
1934 Note that for architectural reasons, firmware _must_ implement SVE
1935 support when running on SVE capable hardware. The required support
1938 * version 1.5 and later of the ARM Trusted Firmware
1939 * the AArch64 boot wrapper since commit 5e1261e08abf
1940 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1942 For other firmware implementations, consult the firmware documentation
1945 If you need the kernel to boot on SVE-capable hardware with broken
1946 firmware, you may need to say N here until you get your firmware
1947 fixed. Otherwise, you may experience firmware panics or lockups when
1948 booting the kernel. If unsure and you are not observing these
1949 symptoms, you should assume that it is safe to say Y.
1952 bool "ARM Scalable Matrix Extension support"
1954 depends on ARM64_SVE
1956 The Scalable Matrix Extension (SME) is an extension to the AArch64
1957 execution state which utilises a substantial subset of the SVE
1958 instruction set, together with the addition of new architectural
1959 register state capable of holding two dimensional matrix tiles to
1960 enable various matrix operations.
1962 config ARM64_MODULE_PLTS
1963 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1965 select HAVE_MOD_ARCH_SPECIFIC
1967 Allocate PLTs when loading modules so that jumps and calls whose
1968 targets are too far away for their relative offsets to be encoded
1969 in the instructions themselves can be bounced via veneers in the
1970 module's PLT. This allows modules to be allocated in the generic
1971 vmalloc area after the dedicated module memory area has been
1974 When running with address space randomization (KASLR), the module
1975 region itself may be too far away for ordinary relative jumps and
1976 calls, and so in that case, module PLTs are required and cannot be
1979 Specific errata workaround(s) might also force module PLTs to be
1980 enabled (ARM64_ERRATUM_843419).
1982 config ARM64_PSEUDO_NMI
1983 bool "Support for NMI-like interrupts"
1986 Adds support for mimicking Non-Maskable Interrupts through the use of
1987 GIC interrupt priority. This support requires version 3 or later of
1990 This high priority configuration for interrupts needs to be
1991 explicitly enabled by setting the kernel parameter
1992 "irqchip.gicv3_pseudo_nmi" to 1.
1997 config ARM64_DEBUG_PRIORITY_MASKING
1998 bool "Debug interrupt priority masking"
2000 This adds runtime checks to functions enabling/disabling
2001 interrupts when using priority masking. The additional checks verify
2002 the validity of ICC_PMR_EL1 when calling concerned functions.
2005 endif # ARM64_PSEUDO_NMI
2008 bool "Build a relocatable kernel image" if EXPERT
2009 select ARCH_HAS_RELR
2012 This builds the kernel as a Position Independent Executable (PIE),
2013 which retains all relocation metadata required to relocate the
2014 kernel binary at runtime to a different virtual address than the
2015 address it was linked at.
2016 Since AArch64 uses the RELA relocation format, this requires a
2017 relocation pass at runtime even if the kernel is loaded at the
2018 same address it was linked at.
2020 config RANDOMIZE_BASE
2021 bool "Randomize the address of the kernel image"
2022 select ARM64_MODULE_PLTS if MODULES
2025 Randomizes the virtual address at which the kernel image is
2026 loaded, as a security feature that deters exploit attempts
2027 relying on knowledge of the location of kernel internals.
2029 It is the bootloader's job to provide entropy, by passing a
2030 random u64 value in /chosen/kaslr-seed at kernel entry.
2032 When booting via the UEFI stub, it will invoke the firmware's
2033 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2034 to the kernel proper. In addition, it will randomise the physical
2035 location of the kernel Image as well.
2039 config RANDOMIZE_MODULE_REGION_FULL
2040 bool "Randomize the module region over a 2 GB range"
2041 depends on RANDOMIZE_BASE
2044 Randomizes the location of the module region inside a 2 GB window
2045 covering the core kernel. This way, it is less likely for modules
2046 to leak information about the location of core kernel data structures
2047 but it does imply that function calls between modules and the core
2048 kernel will need to be resolved via veneers in the module PLT.
2050 When this option is not set, the module region will be randomized over
2051 a limited range that contains the [_stext, _etext] interval of the
2052 core kernel, so branch relocations are almost always in range unless
2053 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2054 particular case of region exhaustion, modules might be able to fall
2055 back to a larger 2GB area.
2057 config CC_HAVE_STACKPROTECTOR_SYSREG
2058 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2060 config STACKPROTECTOR_PER_TASK
2062 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2064 # The GPIO number here must be sorted by descending number. In case of
2065 # a multiplatform kernel, we just want the highest value required by the
2066 # selected platforms.
2069 default 2048 if ARCH_APPLE
2072 Maximum number of GPIOs in the system.
2074 If unsure, leave the default value.
2076 endmenu # "Kernel Features"
2080 config ARM64_ACPI_PARKING_PROTOCOL
2081 bool "Enable support for the ARM64 ACPI parking protocol"
2084 Enable support for the ARM64 ACPI parking protocol. If disabled
2085 the kernel will not allow booting through the ARM64 ACPI parking
2086 protocol even if the corresponding data is present in the ACPI
2090 string "Default kernel command string"
2093 Provide a set of default command-line options at build time by
2094 entering them here. As a minimum, you should specify the the
2095 root device (e.g. root=/dev/nfs).
2098 prompt "Kernel command line type" if CMDLINE != ""
2099 default CMDLINE_FROM_BOOTLOADER
2101 Choose how the kernel will handle the provided default kernel
2102 command line string.
2104 config CMDLINE_FROM_BOOTLOADER
2105 bool "Use bootloader kernel arguments if available"
2107 Uses the command-line options passed by the boot loader. If
2108 the boot loader doesn't provide any, the default kernel command
2109 string provided in CMDLINE will be used.
2111 config CMDLINE_FORCE
2112 bool "Always use the default kernel command string"
2114 Always use the default kernel command string, even if the boot
2115 loader passes other arguments to the kernel.
2116 This is useful if you cannot or don't want to change the
2117 command-line options your boot loader passes to the kernel.
2125 bool "UEFI runtime support"
2126 depends on OF && !CPU_BIG_ENDIAN
2127 depends on KERNEL_MODE_NEON
2128 select ARCH_SUPPORTS_ACPI
2131 select EFI_PARAMS_FROM_FDT
2132 select EFI_RUNTIME_WRAPPERS
2134 select EFI_GENERIC_STUB
2135 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2138 This option provides support for runtime services provided
2139 by UEFI firmware (such as non-volatile variables, realtime
2140 clock, and platform reset). A UEFI stub is also provided to
2141 allow the kernel to be booted as an EFI application. This
2142 is only useful on systems that have UEFI firmware.
2145 bool "Enable support for SMBIOS (DMI) tables"
2149 This enables SMBIOS/DMI feature for systems.
2151 This option is only useful on systems that have UEFI firmware.
2152 However, even with this option, the resultant kernel should
2153 continue to boot on existing non-UEFI platforms.
2155 endmenu # "Boot options"
2157 config SYSVIPC_COMPAT
2159 depends on COMPAT && SYSVIPC
2161 menu "Power management options"
2163 source "kernel/power/Kconfig"
2165 config ARCH_HIBERNATION_POSSIBLE
2169 config ARCH_HIBERNATION_HEADER
2171 depends on HIBERNATION
2173 config ARCH_SUSPEND_POSSIBLE
2176 endmenu # "Power management options"
2178 menu "CPU Power Management"
2180 source "drivers/cpuidle/Kconfig"
2182 source "drivers/cpufreq/Kconfig"
2184 endmenu # "CPU Power Management"
2186 source "drivers/acpi/Kconfig"
2188 source "arch/arm64/kvm/Kconfig"
2191 source "arch/arm64/crypto/Kconfig"