1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
82 select ARCH_USE_CMPXCHG_LOCKREF
83 select ARCH_USE_GNU_PROPERTY
84 select ARCH_USE_MEMTEST
85 select ARCH_USE_QUEUED_RWLOCKS
86 select ARCH_USE_QUEUED_SPINLOCKS
87 select ARCH_USE_SYM_ANNOTATIONS
88 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
89 select ARCH_SUPPORTS_HUGETLBFS
90 select ARCH_SUPPORTS_MEMORY_FAILURE
91 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
92 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
93 select ARCH_SUPPORTS_LTO_CLANG_THIN
94 select ARCH_SUPPORTS_CFI_CLANG
95 select ARCH_SUPPORTS_ATOMIC_RMW
96 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
97 select ARCH_SUPPORTS_NUMA_BALANCING
98 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
99 select ARCH_SUPPORTS_PER_VMA_LOCK
100 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
101 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
102 select ARCH_WANT_DEFAULT_BPF_JIT
103 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
104 select ARCH_WANT_FRAME_POINTERS
105 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
106 select ARCH_WANT_LD_ORPHAN_WARN
107 select ARCH_WANTS_NO_INSTR
108 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
109 select ARCH_HAS_UBSAN_SANITIZE_ALL
111 select ARM_ARCH_TIMER
113 select AUDIT_ARCH_COMPAT_GENERIC
114 select ARM_GIC_V2M if PCI
116 select ARM_GIC_V3_ITS if PCI
118 select BUILDTIME_TABLE_SORT
119 select CLONE_BACKWARDS
121 select CPU_PM if (SUSPEND || CPU_IDLE)
123 select DCACHE_WORD_ACCESS
124 select DYNAMIC_FTRACE if FUNCTION_TRACER
125 select DMA_BOUNCE_UNALIGNED_KMALLOC
126 select DMA_DIRECT_REMAP
129 select FUNCTION_ALIGNMENT_4B
130 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
131 select GENERIC_ALLOCATOR
132 select GENERIC_ARCH_TOPOLOGY
133 select GENERIC_CLOCKEVENTS_BROADCAST
134 select GENERIC_CPU_AUTOPROBE
135 select GENERIC_CPU_VULNERABILITIES
136 select GENERIC_EARLY_IOREMAP
137 select GENERIC_IDLE_POLL_SETUP
138 select GENERIC_IOREMAP
139 select GENERIC_IRQ_IPI
140 select GENERIC_IRQ_PROBE
141 select GENERIC_IRQ_SHOW
142 select GENERIC_IRQ_SHOW_LEVEL
143 select GENERIC_LIB_DEVMEM_IS_ALLOWED
144 select GENERIC_PCI_IOMAP
145 select GENERIC_PTDUMP
146 select GENERIC_SCHED_CLOCK
147 select GENERIC_SMP_IDLE_THREAD
148 select GENERIC_TIME_VSYSCALL
149 select GENERIC_GETTIMEOFDAY
150 select GENERIC_VDSO_TIME_NS
151 select HARDIRQS_SW_RESEND
156 select HAVE_ACPI_APEI if (ACPI && EFI)
157 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
158 select HAVE_ARCH_AUDITSYSCALL
159 select HAVE_ARCH_BITREVERSE
160 select HAVE_ARCH_COMPILER_H
161 select HAVE_ARCH_HUGE_VMALLOC
162 select HAVE_ARCH_HUGE_VMAP
163 select HAVE_ARCH_JUMP_LABEL
164 select HAVE_ARCH_JUMP_LABEL_RELATIVE
165 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
166 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
167 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
168 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
169 # Some instrumentation may be unsound, hence EXPERT
170 select HAVE_ARCH_KCSAN if EXPERT
171 select HAVE_ARCH_KFENCE
172 select HAVE_ARCH_KGDB
173 select HAVE_ARCH_MMAP_RND_BITS
174 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
175 select HAVE_ARCH_PREL32_RELOCATIONS
176 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
177 select HAVE_ARCH_SECCOMP_FILTER
178 select HAVE_ARCH_STACKLEAK
179 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
180 select HAVE_ARCH_TRACEHOOK
181 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
182 select HAVE_ARCH_VMAP_STACK
183 select HAVE_ARM_SMCCC
184 select HAVE_ASM_MODVERSIONS
186 select HAVE_C_RECORDMCOUNT
187 select HAVE_CMPXCHG_DOUBLE
188 select HAVE_CMPXCHG_LOCAL
189 select HAVE_CONTEXT_TRACKING_USER
190 select HAVE_DEBUG_KMEMLEAK
191 select HAVE_DMA_CONTIGUOUS
192 select HAVE_DYNAMIC_FTRACE
193 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
194 if $(cc-option,-fpatchable-function-entry=2)
195 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
196 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
197 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
198 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
199 !CC_OPTIMIZE_FOR_SIZE)
200 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
201 if DYNAMIC_FTRACE_WITH_ARGS
202 select HAVE_SAMPLE_FTRACE_DIRECT
203 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
204 select HAVE_EFFICIENT_UNALIGNED_ACCESS
206 select HAVE_FTRACE_MCOUNT_RECORD
207 select HAVE_FUNCTION_TRACER
208 select HAVE_FUNCTION_ERROR_INJECTION
209 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
210 select HAVE_FUNCTION_GRAPH_TRACER
211 select HAVE_GCC_PLUGINS
212 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
213 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
214 select HAVE_HW_BREAKPOINT if PERF_EVENTS
215 select HAVE_IOREMAP_PROT
216 select HAVE_IRQ_TIME_ACCOUNTING
218 select HAVE_MOD_ARCH_SPECIFIC
220 select HAVE_PERF_EVENTS
221 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
222 select HAVE_PERF_REGS
223 select HAVE_PERF_USER_STACK_DUMP
224 select HAVE_PREEMPT_DYNAMIC_KEY
225 select HAVE_REGS_AND_STACK_ACCESS_API
226 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
227 select HAVE_FUNCTION_ARG_ACCESS_API
228 select MMU_GATHER_RCU_TABLE_FREE
230 select HAVE_STACKPROTECTOR
231 select HAVE_SYSCALL_TRACEPOINTS
233 select HAVE_KRETPROBES
234 select HAVE_GENERIC_VDSO
235 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
237 select IRQ_FORCED_THREADING
238 select KASAN_VMALLOC if KASAN
239 select LOCK_MM_AND_FIND_VMA
240 select MODULES_USE_ELF_RELA
241 select NEED_DMA_MAP_STATE
242 select NEED_SG_DMA_LENGTH
244 select OF_EARLY_FLATTREE
245 select PCI_DOMAINS_GENERIC if PCI
246 select PCI_ECAM if (ACPI && PCI)
247 select PCI_SYSCALL if PCI
252 select SYSCTL_EXCEPTION_TRACE
253 select THREAD_INFO_IN_TASK
254 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
255 select TRACE_IRQFLAGS_SUPPORT
256 select TRACE_IRQFLAGS_NMI_SUPPORT
257 select HAVE_SOFTIRQ_ON_OWN_STACK
259 ARM 64-bit (AArch64) Linux support.
261 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
263 # https://github.com/ClangBuiltLinux/linux/issues/1507
264 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
265 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
267 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
269 depends on $(cc-option,-fpatchable-function-entry=2)
270 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
278 config ARM64_PAGE_SHIFT
280 default 16 if ARM64_64K_PAGES
281 default 14 if ARM64_16K_PAGES
284 config ARM64_CONT_PTE_SHIFT
286 default 5 if ARM64_64K_PAGES
287 default 7 if ARM64_16K_PAGES
290 config ARM64_CONT_PMD_SHIFT
292 default 5 if ARM64_64K_PAGES
293 default 5 if ARM64_16K_PAGES
296 config ARCH_MMAP_RND_BITS_MIN
297 default 14 if ARM64_64K_PAGES
298 default 16 if ARM64_16K_PAGES
301 # max bits determined by the following formula:
302 # VA_BITS - PAGE_SHIFT - 3
303 config ARCH_MMAP_RND_BITS_MAX
304 default 19 if ARM64_VA_BITS=36
305 default 24 if ARM64_VA_BITS=39
306 default 27 if ARM64_VA_BITS=42
307 default 30 if ARM64_VA_BITS=47
308 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
309 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
310 default 33 if ARM64_VA_BITS=48
311 default 14 if ARM64_64K_PAGES
312 default 16 if ARM64_16K_PAGES
315 config ARCH_MMAP_RND_COMPAT_BITS_MIN
316 default 7 if ARM64_64K_PAGES
317 default 9 if ARM64_16K_PAGES
320 config ARCH_MMAP_RND_COMPAT_BITS_MAX
326 config STACKTRACE_SUPPORT
329 config ILLEGAL_POINTER_VALUE
331 default 0xdead000000000000
333 config LOCKDEP_SUPPORT
340 config GENERIC_BUG_RELATIVE_POINTERS
342 depends on GENERIC_BUG
344 config GENERIC_HWEIGHT
350 config GENERIC_CALIBRATE_DELAY
356 config KERNEL_MODE_NEON
359 config FIX_EARLYCON_MEM
362 config PGTABLE_LEVELS
364 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
365 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
366 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
367 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
368 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
369 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
371 config ARCH_SUPPORTS_UPROBES
374 config ARCH_PROC_KCORE_TEXT
377 config BROKEN_GAS_INST
378 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
380 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
382 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0
383 # https://reviews.llvm.org/D75044
384 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
385 # GCC's __builtin_return_address() strips the PAC since 11.1.0,
386 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
387 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
388 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
389 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
390 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
391 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
394 config KASAN_SHADOW_OFFSET
396 depends on KASAN_GENERIC || KASAN_SW_TAGS
397 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
398 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
399 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
400 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
401 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
402 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
403 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
404 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
405 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
406 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
407 default 0xffffffffffffffff
412 source "arch/arm64/Kconfig.platforms"
414 menu "Kernel Features"
416 menu "ARM errata workarounds via the alternatives framework"
418 config AMPERE_ERRATUM_AC03_CPU_38
419 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
422 This option adds an alternative code sequence to work around Ampere
423 erratum AC03_CPU_38 on AmpereOne.
425 The affected design reports FEAT_HAFDBS as not implemented in
426 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
427 as required by the architecture. The unadvertised HAFDBS
428 implementation suffers from an additional erratum where hardware
429 A/D updates can occur after a PTE has been marked invalid.
431 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
432 which avoids enabling unadvertised hardware Access Flag management
437 config ARM64_WORKAROUND_CLEAN_CACHE
440 config ARM64_ERRATUM_826319
441 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
443 select ARM64_WORKAROUND_CLEAN_CACHE
445 This option adds an alternative code sequence to work around ARM
446 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
447 AXI master interface and an L2 cache.
449 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
450 and is unable to accept a certain write via this interface, it will
451 not progress on read data presented on the read data channel and the
454 The workaround promotes data cache clean instructions to
455 data cache clean-and-invalidate.
456 Please note that this does not necessarily enable the workaround,
457 as it depends on the alternative framework, which will only patch
458 the kernel if an affected CPU is detected.
462 config ARM64_ERRATUM_827319
463 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
465 select ARM64_WORKAROUND_CLEAN_CACHE
467 This option adds an alternative code sequence to work around ARM
468 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
469 master interface and an L2 cache.
471 Under certain conditions this erratum can cause a clean line eviction
472 to occur at the same time as another transaction to the same address
473 on the AMBA 5 CHI interface, which can cause data corruption if the
474 interconnect reorders the two transactions.
476 The workaround promotes data cache clean instructions to
477 data cache clean-and-invalidate.
478 Please note that this does not necessarily enable the workaround,
479 as it depends on the alternative framework, which will only patch
480 the kernel if an affected CPU is detected.
484 config ARM64_ERRATUM_824069
485 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
487 select ARM64_WORKAROUND_CLEAN_CACHE
489 This option adds an alternative code sequence to work around ARM
490 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
491 to a coherent interconnect.
493 If a Cortex-A53 processor is executing a store or prefetch for
494 write instruction at the same time as a processor in another
495 cluster is executing a cache maintenance operation to the same
496 address, then this erratum might cause a clean cache line to be
497 incorrectly marked as dirty.
499 The workaround promotes data cache clean instructions to
500 data cache clean-and-invalidate.
501 Please note that this option does not necessarily enable the
502 workaround, as it depends on the alternative framework, which will
503 only patch the kernel if an affected CPU is detected.
507 config ARM64_ERRATUM_819472
508 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
510 select ARM64_WORKAROUND_CLEAN_CACHE
512 This option adds an alternative code sequence to work around ARM
513 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
514 present when it is connected to a coherent interconnect.
516 If the processor is executing a load and store exclusive sequence at
517 the same time as a processor in another cluster is executing a cache
518 maintenance operation to the same address, then this erratum might
519 cause data corruption.
521 The workaround promotes data cache clean instructions to
522 data cache clean-and-invalidate.
523 Please note that this does not necessarily enable the workaround,
524 as it depends on the alternative framework, which will only patch
525 the kernel if an affected CPU is detected.
529 config ARM64_ERRATUM_832075
530 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
533 This option adds an alternative code sequence to work around ARM
534 erratum 832075 on Cortex-A57 parts up to r1p2.
536 Affected Cortex-A57 parts might deadlock when exclusive load/store
537 instructions to Write-Back memory are mixed with Device loads.
539 The workaround is to promote device loads to use Load-Acquire
541 Please note that this does not necessarily enable the workaround,
542 as it depends on the alternative framework, which will only patch
543 the kernel if an affected CPU is detected.
547 config ARM64_ERRATUM_834220
548 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
552 This option adds an alternative code sequence to work around ARM
553 erratum 834220 on Cortex-A57 parts up to r1p2.
555 Affected Cortex-A57 parts might report a Stage 2 translation
556 fault as the result of a Stage 1 fault for load crossing a
557 page boundary when there is a permission or device memory
558 alignment fault at Stage 1 and a translation fault at Stage 2.
560 The workaround is to verify that the Stage 1 translation
561 doesn't generate a fault before handling the Stage 2 fault.
562 Please note that this does not necessarily enable the workaround,
563 as it depends on the alternative framework, which will only patch
564 the kernel if an affected CPU is detected.
568 config ARM64_ERRATUM_1742098
569 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
573 This option removes the AES hwcap for aarch32 user-space to
574 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
576 Affected parts may corrupt the AES state if an interrupt is
577 taken between a pair of AES instructions. These instructions
578 are only present if the cryptography extensions are present.
579 All software should have a fallback implementation for CPUs
580 that don't implement the cryptography extensions.
584 config ARM64_ERRATUM_845719
585 bool "Cortex-A53: 845719: a load might read incorrect data"
589 This option adds an alternative code sequence to work around ARM
590 erratum 845719 on Cortex-A53 parts up to r0p4.
592 When running a compat (AArch32) userspace on an affected Cortex-A53
593 part, a load at EL0 from a virtual address that matches the bottom 32
594 bits of the virtual address used by a recent load at (AArch64) EL1
595 might return incorrect data.
597 The workaround is to write the contextidr_el1 register on exception
598 return to a 32-bit task.
599 Please note that this does not necessarily enable the workaround,
600 as it depends on the alternative framework, which will only patch
601 the kernel if an affected CPU is detected.
605 config ARM64_ERRATUM_843419
606 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
609 This option links the kernel with '--fix-cortex-a53-843419' and
610 enables PLT support to replace certain ADRP instructions, which can
611 cause subsequent memory accesses to use an incorrect address on
612 Cortex-A53 parts up to r0p4.
616 config ARM64_LD_HAS_FIX_ERRATUM_843419
617 def_bool $(ld-option,--fix-cortex-a53-843419)
619 config ARM64_ERRATUM_1024718
620 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
623 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
625 Affected Cortex-A55 cores (all revisions) could cause incorrect
626 update of the hardware dirty bit when the DBM/AP bits are updated
627 without a break-before-make. The workaround is to disable the usage
628 of hardware DBM locally on the affected cores. CPUs not affected by
629 this erratum will continue to use the feature.
633 config ARM64_ERRATUM_1418040
634 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
638 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
639 errata 1188873 and 1418040.
641 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
642 cause register corruption when accessing the timer registers
643 from AArch32 userspace.
647 config ARM64_WORKAROUND_SPECULATIVE_AT
650 config ARM64_ERRATUM_1165522
651 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
653 select ARM64_WORKAROUND_SPECULATIVE_AT
655 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
657 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
658 corrupted TLBs by speculating an AT instruction during a guest
663 config ARM64_ERRATUM_1319367
664 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
666 select ARM64_WORKAROUND_SPECULATIVE_AT
668 This option adds work arounds for ARM Cortex-A57 erratum 1319537
669 and A72 erratum 1319367
671 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
672 speculating an AT instruction during a guest context switch.
676 config ARM64_ERRATUM_1530923
677 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
679 select ARM64_WORKAROUND_SPECULATIVE_AT
681 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
683 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
684 corrupted TLBs by speculating an AT instruction during a guest
689 config ARM64_WORKAROUND_REPEAT_TLBI
692 config ARM64_ERRATUM_2441007
693 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
695 select ARM64_WORKAROUND_REPEAT_TLBI
697 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
699 Under very rare circumstances, affected Cortex-A55 CPUs
700 may not handle a race between a break-before-make sequence on one
701 CPU, and another CPU accessing the same page. This could allow a
702 store to a page that has been unmapped.
704 Work around this by adding the affected CPUs to the list that needs
705 TLB sequences to be done twice.
709 config ARM64_ERRATUM_1286807
710 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
712 select ARM64_WORKAROUND_REPEAT_TLBI
714 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
716 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
717 address for a cacheable mapping of a location is being
718 accessed by a core while another core is remapping the virtual
719 address to a new physical page using the recommended
720 break-before-make sequence, then under very rare circumstances
721 TLBI+DSB completes before a read using the translation being
722 invalidated has been observed by other observers. The
723 workaround repeats the TLBI+DSB operation.
725 config ARM64_ERRATUM_1463225
726 bool "Cortex-A76: Software Step might prevent interrupt recognition"
729 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
731 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
732 of a system call instruction (SVC) can prevent recognition of
733 subsequent interrupts when software stepping is disabled in the
734 exception handler of the system call and either kernel debugging
735 is enabled or VHE is in use.
737 Work around the erratum by triggering a dummy step exception
738 when handling a system call from a task that is being stepped
739 in a VHE configuration of the kernel.
743 config ARM64_ERRATUM_1542419
744 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
747 This option adds a workaround for ARM Neoverse-N1 erratum
750 Affected Neoverse-N1 cores could execute a stale instruction when
751 modified by another CPU. The workaround depends on a firmware
754 Workaround the issue by hiding the DIC feature from EL0. This
755 forces user-space to perform cache maintenance.
759 config ARM64_ERRATUM_1508412
760 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
763 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
765 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
766 of a store-exclusive or read of PAR_EL1 and a load with device or
767 non-cacheable memory attributes. The workaround depends on a firmware
770 KVM guests must also have the workaround implemented or they can
773 Work around the issue by inserting DMB SY barriers around PAR_EL1
774 register reads and warning KVM users. The DMB barrier is sufficient
775 to prevent a speculative PAR_EL1 read.
779 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
782 config ARM64_ERRATUM_2051678
783 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
786 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
787 Affected Cortex-A510 might not respect the ordering rules for
788 hardware update of the page table's dirty bit. The workaround
789 is to not enable the feature on affected CPUs.
793 config ARM64_ERRATUM_2077057
794 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
797 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
798 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
799 expected, but a Pointer Authentication trap is taken instead. The
800 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
801 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
803 This can only happen when EL2 is stepping EL1.
805 When these conditions occur, the SPSR_EL2 value is unchanged from the
806 previous guest entry, and can be restored from the in-memory copy.
810 config ARM64_ERRATUM_2658417
811 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
814 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
815 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
816 BFMMLA or VMMLA instructions in rare circumstances when a pair of
817 A510 CPUs are using shared neon hardware. As the sharing is not
818 discoverable by the kernel, hide the BF16 HWCAP to indicate that
819 user-space should not be using these instructions.
823 config ARM64_ERRATUM_2119858
824 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
826 depends on CORESIGHT_TRBE
827 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
829 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
831 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
832 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
833 the event of a WRAP event.
835 Work around the issue by always making sure we move the TRBPTR_EL1 by
836 256 bytes before enabling the buffer and filling the first 256 bytes of
837 the buffer with ETM ignore packets upon disabling.
841 config ARM64_ERRATUM_2139208
842 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
844 depends on CORESIGHT_TRBE
845 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
847 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
849 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
850 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
851 the event of a WRAP event.
853 Work around the issue by always making sure we move the TRBPTR_EL1 by
854 256 bytes before enabling the buffer and filling the first 256 bytes of
855 the buffer with ETM ignore packets upon disabling.
859 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
862 config ARM64_ERRATUM_2054223
863 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
865 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
867 Enable workaround for ARM Cortex-A710 erratum 2054223
869 Affected cores may fail to flush the trace data on a TSB instruction, when
870 the PE is in trace prohibited state. This will cause losing a few bytes
873 Workaround is to issue two TSB consecutively on affected cores.
877 config ARM64_ERRATUM_2067961
878 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
880 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
882 Enable workaround for ARM Neoverse-N2 erratum 2067961
884 Affected cores may fail to flush the trace data on a TSB instruction, when
885 the PE is in trace prohibited state. This will cause losing a few bytes
888 Workaround is to issue two TSB consecutively on affected cores.
892 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
895 config ARM64_ERRATUM_2253138
896 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
897 depends on CORESIGHT_TRBE
899 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
901 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
903 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
904 for TRBE. Under some conditions, the TRBE might generate a write to the next
905 virtually addressed page following the last page of the TRBE address space
906 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
908 Work around this in the driver by always making sure that there is a
909 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
913 config ARM64_ERRATUM_2224489
914 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
915 depends on CORESIGHT_TRBE
917 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
919 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
921 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
922 for TRBE. Under some conditions, the TRBE might generate a write to the next
923 virtually addressed page following the last page of the TRBE address space
924 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
926 Work around this in the driver by always making sure that there is a
927 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
931 config ARM64_ERRATUM_2441009
932 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
934 select ARM64_WORKAROUND_REPEAT_TLBI
936 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
938 Under very rare circumstances, affected Cortex-A510 CPUs
939 may not handle a race between a break-before-make sequence on one
940 CPU, and another CPU accessing the same page. This could allow a
941 store to a page that has been unmapped.
943 Work around this by adding the affected CPUs to the list that needs
944 TLB sequences to be done twice.
948 config ARM64_ERRATUM_2064142
949 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
950 depends on CORESIGHT_TRBE
953 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
955 Affected Cortex-A510 core might fail to write into system registers after the
956 TRBE has been disabled. Under some conditions after the TRBE has been disabled
957 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
958 and TRBTRG_EL1 will be ignored and will not be effected.
960 Work around this in the driver by executing TSB CSYNC and DSB after collection
961 is stopped and before performing a system register write to one of the affected
966 config ARM64_ERRATUM_2038923
967 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
968 depends on CORESIGHT_TRBE
971 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
973 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
974 prohibited within the CPU. As a result, the trace buffer or trace buffer state
975 might be corrupted. This happens after TRBE buffer has been enabled by setting
976 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
977 execution changes from a context, in which trace is prohibited to one where it
978 isn't, or vice versa. In these mentioned conditions, the view of whether trace
979 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
980 the trace buffer state might be corrupted.
982 Work around this in the driver by preventing an inconsistent view of whether the
983 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
984 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
985 two ISB instructions if no ERET is to take place.
989 config ARM64_ERRATUM_1902691
990 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
991 depends on CORESIGHT_TRBE
994 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
996 Affected Cortex-A510 core might cause trace data corruption, when being written
997 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1000 Work around this problem in the driver by just preventing TRBE initialization on
1001 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1002 on such implementations. This will cover the kernel for any firmware that doesn't
1007 config ARM64_ERRATUM_2457168
1008 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1009 depends on ARM64_AMU_EXTN
1012 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1014 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1015 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1016 incorrectly giving a significantly higher output value.
1018 Work around this problem by returning 0 when reading the affected counter in
1019 key locations that results in disabling all users of this counter. This effect
1020 is the same to firmware disabling affected counters.
1024 config ARM64_ERRATUM_2645198
1025 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1028 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1030 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1031 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1032 next instruction abort caused by permission fault.
1034 Only user-space does executable to non-executable permission transition via
1035 mprotect() system call. Workaround the problem by doing a break-before-make
1036 TLB invalidation, for all changes to executable user space mappings.
1040 config CAVIUM_ERRATUM_22375
1041 bool "Cavium erratum 22375, 24313"
1044 Enable workaround for errata 22375 and 24313.
1046 This implements two gicv3-its errata workarounds for ThunderX. Both
1047 with a small impact affecting only ITS table allocation.
1049 erratum 22375: only alloc 8MB table size
1050 erratum 24313: ignore memory access type
1052 The fixes are in ITS initialization and basically ignore memory access
1053 type and table size provided by the TYPER and BASER registers.
1057 config CAVIUM_ERRATUM_23144
1058 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1062 ITS SYNC command hang for cross node io and collections/cpu mapping.
1066 config CAVIUM_ERRATUM_23154
1067 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1070 The ThunderX GICv3 implementation requires a modified version for
1071 reading the IAR status to ensure data synchronization
1072 (access to icc_iar1_el1 is not sync'ed before and after).
1074 It also suffers from erratum 38545 (also present on Marvell's
1075 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1076 spuriously presented to the CPU interface.
1080 config CAVIUM_ERRATUM_27456
1081 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1084 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1085 instructions may cause the icache to become corrupted if it
1086 contains data for a non-current ASID. The fix is to
1087 invalidate the icache when changing the mm context.
1091 config CAVIUM_ERRATUM_30115
1092 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1095 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1096 1.2, and T83 Pass 1.0, KVM guest execution may disable
1097 interrupts in host. Trapping both GICv3 group-0 and group-1
1098 accesses sidesteps the issue.
1102 config CAVIUM_TX2_ERRATUM_219
1103 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1106 On Cavium ThunderX2, a load, store or prefetch instruction between a
1107 TTBR update and the corresponding context synchronizing operation can
1108 cause a spurious Data Abort to be delivered to any hardware thread in
1111 Work around the issue by avoiding the problematic code sequence and
1112 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1113 trap handler performs the corresponding register access, skips the
1114 instruction and ensures context synchronization by virtue of the
1119 config FUJITSU_ERRATUM_010001
1120 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1123 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1124 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1125 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1126 This fault occurs under a specific hardware condition when a
1127 load/store instruction performs an address translation using:
1128 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1129 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1130 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1131 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1133 The workaround is to ensure these bits are clear in TCR_ELx.
1134 The workaround only affects the Fujitsu-A64FX.
1138 config HISILICON_ERRATUM_161600802
1139 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1142 The HiSilicon Hip07 SoC uses the wrong redistributor base
1143 when issued ITS commands such as VMOVP and VMAPP, and requires
1144 a 128kB offset to be applied to the target address in this commands.
1148 config QCOM_FALKOR_ERRATUM_1003
1149 bool "Falkor E1003: Incorrect translation due to ASID change"
1152 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1153 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1154 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1155 then only for entries in the walk cache, since the leaf translation
1156 is unchanged. Work around the erratum by invalidating the walk cache
1157 entries for the trampoline before entering the kernel proper.
1159 config QCOM_FALKOR_ERRATUM_1009
1160 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1162 select ARM64_WORKAROUND_REPEAT_TLBI
1164 On Falkor v1, the CPU may prematurely complete a DSB following a
1165 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1166 one more time to fix the issue.
1170 config QCOM_QDF2400_ERRATUM_0065
1171 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1174 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1175 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1176 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1180 config QCOM_FALKOR_ERRATUM_E1041
1181 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1184 Falkor CPU may speculatively fetch instructions from an improper
1185 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1186 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1190 config NVIDIA_CARMEL_CNP_ERRATUM
1191 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1194 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1195 invalidate shared TLB entries installed by a different core, as it would
1196 on standard ARM cores.
1200 config ROCKCHIP_ERRATUM_3588001
1201 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1204 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1205 This means, that its sharability feature may not be used, even though it
1206 is supported by the IP itself.
1210 config SOCIONEXT_SYNQUACER_PREITS
1211 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1214 Socionext Synquacer SoCs implement a separate h/w block to generate
1215 MSI doorbell writes with non-zero values for the device ID.
1219 endmenu # "ARM errata workarounds via the alternatives framework"
1223 default ARM64_4K_PAGES
1225 Page size (translation granule) configuration.
1227 config ARM64_4K_PAGES
1230 This feature enables 4KB pages support.
1232 config ARM64_16K_PAGES
1235 The system will use 16KB pages support. AArch32 emulation
1236 requires applications compiled with 16K (or a multiple of 16K)
1239 config ARM64_64K_PAGES
1242 This feature enables 64KB pages support (4KB by default)
1243 allowing only two levels of page tables and faster TLB
1244 look-up. AArch32 emulation requires applications compiled
1245 with 64K aligned segments.
1250 prompt "Virtual address space size"
1251 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1252 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1253 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1255 Allows choosing one of multiple possible virtual address
1256 space sizes. The level of translation table is determined by
1257 a combination of page size and virtual address space size.
1259 config ARM64_VA_BITS_36
1260 bool "36-bit" if EXPERT
1261 depends on ARM64_16K_PAGES
1263 config ARM64_VA_BITS_39
1265 depends on ARM64_4K_PAGES
1267 config ARM64_VA_BITS_42
1269 depends on ARM64_64K_PAGES
1271 config ARM64_VA_BITS_47
1273 depends on ARM64_16K_PAGES
1275 config ARM64_VA_BITS_48
1278 config ARM64_VA_BITS_52
1280 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1282 Enable 52-bit virtual addressing for userspace when explicitly
1283 requested via a hint to mmap(). The kernel will also use 52-bit
1284 virtual addresses for its own mappings (provided HW support for
1285 this feature is available, otherwise it reverts to 48-bit).
1287 NOTE: Enabling 52-bit virtual addressing in conjunction with
1288 ARMv8.3 Pointer Authentication will result in the PAC being
1289 reduced from 7 bits to 3 bits, which may have a significant
1290 impact on its susceptibility to brute-force attacks.
1292 If unsure, select 48-bit virtual addressing instead.
1296 config ARM64_FORCE_52BIT
1297 bool "Force 52-bit virtual addresses for userspace"
1298 depends on ARM64_VA_BITS_52 && EXPERT
1300 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1301 to maintain compatibility with older software by providing 48-bit VAs
1302 unless a hint is supplied to mmap.
1304 This configuration option disables the 48-bit compatibility logic, and
1305 forces all userspace addresses to be 52-bit on HW that supports it. One
1306 should only enable this configuration option for stress testing userspace
1307 memory management code. If unsure say N here.
1309 config ARM64_VA_BITS
1311 default 36 if ARM64_VA_BITS_36
1312 default 39 if ARM64_VA_BITS_39
1313 default 42 if ARM64_VA_BITS_42
1314 default 47 if ARM64_VA_BITS_47
1315 default 48 if ARM64_VA_BITS_48
1316 default 52 if ARM64_VA_BITS_52
1319 prompt "Physical address space size"
1320 default ARM64_PA_BITS_48
1322 Choose the maximum physical address range that the kernel will
1325 config ARM64_PA_BITS_48
1328 config ARM64_PA_BITS_52
1329 bool "52-bit (ARMv8.2)"
1330 depends on ARM64_64K_PAGES
1331 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1333 Enable support for a 52-bit physical address space, introduced as
1334 part of the ARMv8.2-LPA extension.
1336 With this enabled, the kernel will also continue to work on CPUs that
1337 do not support ARMv8.2-LPA, but with some added memory overhead (and
1338 minor performance overhead).
1342 config ARM64_PA_BITS
1344 default 48 if ARM64_PA_BITS_48
1345 default 52 if ARM64_PA_BITS_52
1349 default CPU_LITTLE_ENDIAN
1351 Select the endianness of data accesses performed by the CPU. Userspace
1352 applications will need to be compiled and linked for the endianness
1353 that is selected here.
1355 config CPU_BIG_ENDIAN
1356 bool "Build big-endian kernel"
1357 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1359 Say Y if you plan on running a kernel with a big-endian userspace.
1361 config CPU_LITTLE_ENDIAN
1362 bool "Build little-endian kernel"
1364 Say Y if you plan on running a kernel with a little-endian userspace.
1365 This is usually the case for distributions targeting arm64.
1370 bool "Multi-core scheduler support"
1372 Multi-core scheduler support improves the CPU scheduler's decision
1373 making when dealing with multi-core CPU chips at a cost of slightly
1374 increased overhead in some places. If unsure say N here.
1376 config SCHED_CLUSTER
1377 bool "Cluster scheduler support"
1379 Cluster scheduler support improves the CPU scheduler's decision
1380 making when dealing with machines that have clusters of CPUs.
1381 Cluster usually means a couple of CPUs which are placed closely
1382 by sharing mid-level caches, last-level cache tags or internal
1386 bool "SMT scheduler support"
1388 Improves the CPU scheduler's decision making when dealing with
1389 MultiThreading at a cost of slightly increased overhead in some
1390 places. If unsure say N here.
1393 int "Maximum number of CPUs (2-4096)"
1398 bool "Support for hot-pluggable CPUs"
1399 select GENERIC_IRQ_MIGRATION
1401 Say Y here to experiment with turning CPUs off and on. CPUs
1402 can be controlled through /sys/devices/system/cpu.
1404 # Common NUMA Features
1406 bool "NUMA Memory Allocation and Scheduler Support"
1407 select GENERIC_ARCH_NUMA
1408 select ACPI_NUMA if ACPI
1410 select HAVE_SETUP_PER_CPU_AREA
1411 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1412 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1413 select USE_PERCPU_NUMA_NODE_ID
1415 Enable NUMA (Non-Uniform Memory Access) support.
1417 The kernel will try to allocate memory used by a CPU on the
1418 local memory of the CPU and add some more
1419 NUMA awareness to the kernel.
1422 int "Maximum NUMA Nodes (as a power of 2)"
1427 Specify the maximum number of NUMA Nodes available on the target
1428 system. Increases memory reserved to accommodate various tables.
1430 source "kernel/Kconfig.hz"
1432 config ARCH_SPARSEMEM_ENABLE
1434 select SPARSEMEM_VMEMMAP_ENABLE
1435 select SPARSEMEM_VMEMMAP
1437 config HW_PERF_EVENTS
1441 # Supported by clang >= 7.0 or GCC >= 12.0.0
1442 config CC_HAVE_SHADOW_CALL_STACK
1443 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1446 bool "Enable paravirtualization code"
1448 This changes the kernel so it can modify itself when it is run
1449 under a hypervisor, potentially improving performance significantly
1450 over full virtualization.
1452 config PARAVIRT_TIME_ACCOUNTING
1453 bool "Paravirtual steal time accounting"
1456 Select this option to enable fine granularity task steal time
1457 accounting. Time spent executing other tasks in parallel with
1458 the current vCPU is discounted from the vCPU power. To account for
1459 that, there can be a small performance impact.
1461 If in doubt, say N here.
1463 config ARCH_SUPPORTS_KEXEC
1464 def_bool PM_SLEEP_SMP
1466 config ARCH_SUPPORTS_KEXEC_FILE
1469 config ARCH_SELECTS_KEXEC_FILE
1471 depends on KEXEC_FILE
1472 select HAVE_IMA_KEXEC if IMA
1474 config ARCH_SUPPORTS_KEXEC_SIG
1477 config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1480 config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1483 config ARCH_SUPPORTS_CRASH_DUMP
1488 depends on HIBERNATION || KEXEC_CORE
1495 bool "Xen guest support on ARM64"
1496 depends on ARM64 && OF
1500 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1502 # include/linux/mmzone.h requires the following to be true:
1504 # MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1506 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1508 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER |
1509 # ----+-------------------+--------------+-----------------+--------------------+
1510 # 4K | 27 | 12 | 15 | 10 |
1511 # 16K | 27 | 14 | 13 | 11 |
1512 # 64K | 29 | 16 | 13 | 13 |
1513 config ARCH_FORCE_MAX_ORDER
1515 default "13" if ARM64_64K_PAGES
1516 default "11" if ARM64_16K_PAGES
1519 The kernel page allocator limits the size of maximal physically
1520 contiguous allocations. The limit is called MAX_ORDER and it
1521 defines the maximal power of two of number of pages that can be
1522 allocated as a single contiguous block. This option allows
1523 overriding the default setting when ability to allocate very
1524 large blocks of physically contiguous memory is required.
1526 The maximal size of allocation cannot exceed the size of the
1527 section, so the value of MAX_ORDER should satisfy
1529 MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1531 Don't change if unsure.
1533 config UNMAP_KERNEL_AT_EL0
1534 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1537 Speculation attacks against some high-performance processors can
1538 be used to bypass MMU permission checks and leak kernel data to
1539 userspace. This can be defended against by unmapping the kernel
1540 when running in userspace, mapping it back in on exception entry
1541 via a trampoline page in the vector table.
1545 config MITIGATE_SPECTRE_BRANCH_HISTORY
1546 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1549 Speculation attacks against some high-performance processors can
1550 make use of branch history to influence future speculation.
1551 When taking an exception from user-space, a sequence of branches
1552 or a firmware call overwrites the branch history.
1554 config RODATA_FULL_DEFAULT_ENABLED
1555 bool "Apply r/o permissions of VM areas also to their linear aliases"
1558 Apply read-only attributes of VM areas to the linear alias of
1559 the backing pages as well. This prevents code or read-only data
1560 from being modified (inadvertently or intentionally) via another
1561 mapping of the same memory page. This additional enhancement can
1562 be turned off at runtime by passing rodata=[off|on] (and turned on
1563 with rodata=full if this option is set to 'n')
1565 This requires the linear region to be mapped down to pages,
1566 which may adversely affect performance in some cases.
1568 config ARM64_SW_TTBR0_PAN
1569 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1571 Enabling this option prevents the kernel from accessing
1572 user-space memory directly by pointing TTBR0_EL1 to a reserved
1573 zeroed area and reserved ASID. The user access routines
1574 restore the valid TTBR0_EL1 temporarily.
1576 config ARM64_TAGGED_ADDR_ABI
1577 bool "Enable the tagged user addresses syscall ABI"
1580 When this option is enabled, user applications can opt in to a
1581 relaxed ABI via prctl() allowing tagged addresses to be passed
1582 to system calls as pointer arguments. For details, see
1583 Documentation/arch/arm64/tagged-address-abi.rst.
1586 bool "Kernel support for 32-bit EL0"
1587 depends on ARM64_4K_PAGES || EXPERT
1589 select OLD_SIGSUSPEND3
1590 select COMPAT_OLD_SIGACTION
1592 This option enables support for a 32-bit EL0 running under a 64-bit
1593 kernel at EL1. AArch32-specific components such as system calls,
1594 the user helper functions, VFP support and the ptrace interface are
1595 handled appropriately by the kernel.
1597 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1598 that you will only be able to execute AArch32 binaries that were compiled
1599 with page size aligned segments.
1601 If you want to execute 32-bit userspace applications, say Y.
1605 config KUSER_HELPERS
1606 bool "Enable kuser helpers page for 32-bit applications"
1609 Warning: disabling this option may break 32-bit user programs.
1611 Provide kuser helpers to compat tasks. The kernel provides
1612 helper code to userspace in read only form at a fixed location
1613 to allow userspace to be independent of the CPU type fitted to
1614 the system. This permits binaries to be run on ARMv4 through
1615 to ARMv8 without modification.
1617 See Documentation/arch/arm/kernel_user_helpers.rst for details.
1619 However, the fixed address nature of these helpers can be used
1620 by ROP (return orientated programming) authors when creating
1623 If all of the binaries and libraries which run on your platform
1624 are built specifically for your platform, and make no use of
1625 these helpers, then you can turn this option off to hinder
1626 such exploits. However, in that case, if a binary or library
1627 relying on those helpers is run, it will not function correctly.
1629 Say N here only if you are absolutely certain that you do not
1630 need these helpers; otherwise, the safe option is to say Y.
1633 bool "Enable vDSO for 32-bit applications"
1634 depends on !CPU_BIG_ENDIAN
1635 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1636 select GENERIC_COMPAT_VDSO
1639 Place in the process address space of 32-bit applications an
1640 ELF shared object providing fast implementations of gettimeofday
1643 You must have a 32-bit build of glibc 2.22 or later for programs
1644 to seamlessly take advantage of this.
1646 config THUMB2_COMPAT_VDSO
1647 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1648 depends on COMPAT_VDSO
1651 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1652 otherwise with '-marm'.
1654 config COMPAT_ALIGNMENT_FIXUPS
1655 bool "Fix up misaligned multi-word loads and stores in user space"
1657 menuconfig ARMV8_DEPRECATED
1658 bool "Emulate deprecated/obsolete ARMv8 instructions"
1661 Legacy software support may require certain instructions
1662 that have been deprecated or obsoleted in the architecture.
1664 Enable this config to enable selective emulation of these
1671 config SWP_EMULATION
1672 bool "Emulate SWP/SWPB instructions"
1674 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1675 they are always undefined. Say Y here to enable software
1676 emulation of these instructions for userspace using LDXR/STXR.
1677 This feature can be controlled at runtime with the abi.swp
1678 sysctl which is disabled by default.
1680 In some older versions of glibc [<=2.8] SWP is used during futex
1681 trylock() operations with the assumption that the code will not
1682 be preempted. This invalid assumption may be more likely to fail
1683 with SWP emulation enabled, leading to deadlock of the user
1686 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1687 on an external transaction monitoring block called a global
1688 monitor to maintain update atomicity. If your system does not
1689 implement a global monitor, this option can cause programs that
1690 perform SWP operations to uncached memory to deadlock.
1694 config CP15_BARRIER_EMULATION
1695 bool "Emulate CP15 Barrier instructions"
1697 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1698 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1699 strongly recommended to use the ISB, DSB, and DMB
1700 instructions instead.
1702 Say Y here to enable software emulation of these
1703 instructions for AArch32 userspace code. When this option is
1704 enabled, CP15 barrier usage is traced which can help
1705 identify software that needs updating. This feature can be
1706 controlled at runtime with the abi.cp15_barrier sysctl.
1710 config SETEND_EMULATION
1711 bool "Emulate SETEND instruction"
1713 The SETEND instruction alters the data-endianness of the
1714 AArch32 EL0, and is deprecated in ARMv8.
1716 Say Y here to enable software emulation of the instruction
1717 for AArch32 userspace code. This feature can be controlled
1718 at runtime with the abi.setend sysctl.
1720 Note: All the cpus on the system must have mixed endian support at EL0
1721 for this feature to be enabled. If a new CPU - which doesn't support mixed
1722 endian - is hotplugged in after this feature has been enabled, there could
1723 be unexpected results in the applications.
1726 endif # ARMV8_DEPRECATED
1730 menu "ARMv8.1 architectural features"
1732 config ARM64_HW_AFDBM
1733 bool "Support for hardware updates of the Access and Dirty page flags"
1736 The ARMv8.1 architecture extensions introduce support for
1737 hardware updates of the access and dirty information in page
1738 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1739 capable processors, accesses to pages with PTE_AF cleared will
1740 set this bit instead of raising an access flag fault.
1741 Similarly, writes to read-only pages with the DBM bit set will
1742 clear the read-only bit (AP[2]) instead of raising a
1745 Kernels built with this configuration option enabled continue
1746 to work on pre-ARMv8.1 hardware and the performance impact is
1747 minimal. If unsure, say Y.
1750 bool "Enable support for Privileged Access Never (PAN)"
1753 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1754 prevents the kernel or hypervisor from accessing user-space (EL0)
1757 Choosing this option will cause any unprotected (not using
1758 copy_to_user et al) memory access to fail with a permission fault.
1760 The feature is detected at runtime, and will remain as a 'nop'
1761 instruction if the cpu does not implement the feature.
1763 config AS_HAS_LSE_ATOMICS
1764 def_bool $(as-instr,.arch_extension lse)
1766 config ARM64_LSE_ATOMICS
1768 default ARM64_USE_LSE_ATOMICS
1769 depends on AS_HAS_LSE_ATOMICS
1771 config ARM64_USE_LSE_ATOMICS
1772 bool "Atomic instructions"
1775 As part of the Large System Extensions, ARMv8.1 introduces new
1776 atomic instructions that are designed specifically to scale in
1779 Say Y here to make use of these instructions for the in-kernel
1780 atomic routines. This incurs a small overhead on CPUs that do
1781 not support these instructions and requires the kernel to be
1782 built with binutils >= 2.25 in order for the new instructions
1785 endmenu # "ARMv8.1 architectural features"
1787 menu "ARMv8.2 architectural features"
1789 config AS_HAS_ARMV8_2
1790 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1793 def_bool $(as-instr,.arch armv8.2-a+sha3)
1796 bool "Enable support for persistent memory"
1797 select ARCH_HAS_PMEM_API
1798 select ARCH_HAS_UACCESS_FLUSHCACHE
1800 Say Y to enable support for the persistent memory API based on the
1801 ARMv8.2 DCPoP feature.
1803 The feature is detected at runtime, and the kernel will use DC CVAC
1804 operations if DC CVAP is not supported (following the behaviour of
1805 DC CVAP itself if the system does not define a point of persistence).
1807 config ARM64_RAS_EXTN
1808 bool "Enable support for RAS CPU Extensions"
1811 CPUs that support the Reliability, Availability and Serviceability
1812 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1813 errors, classify them and report them to software.
1815 On CPUs with these extensions system software can use additional
1816 barriers to determine if faults are pending and read the
1817 classification from a new set of registers.
1819 Selecting this feature will allow the kernel to use these barriers
1820 and access the new registers if the system supports the extension.
1821 Platform RAS features may additionally depend on firmware support.
1824 bool "Enable support for Common Not Private (CNP) translations"
1826 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1828 Common Not Private (CNP) allows translation table entries to
1829 be shared between different PEs in the same inner shareable
1830 domain, so the hardware can use this fact to optimise the
1831 caching of such entries in the TLB.
1833 Selecting this option allows the CNP feature to be detected
1834 at runtime, and does not affect PEs that do not implement
1837 endmenu # "ARMv8.2 architectural features"
1839 menu "ARMv8.3 architectural features"
1841 config ARM64_PTR_AUTH
1842 bool "Enable support for pointer authentication"
1845 Pointer authentication (part of the ARMv8.3 Extensions) provides
1846 instructions for signing and authenticating pointers against secret
1847 keys, which can be used to mitigate Return Oriented Programming (ROP)
1850 This option enables these instructions at EL0 (i.e. for userspace).
1851 Choosing this option will cause the kernel to initialise secret keys
1852 for each process at exec() time, with these keys being
1853 context-switched along with the process.
1855 The feature is detected at runtime. If the feature is not present in
1856 hardware it will not be advertised to userspace/KVM guest nor will it
1859 If the feature is present on the boot CPU but not on a late CPU, then
1860 the late CPU will be parked. Also, if the boot CPU does not have
1861 address auth and the late CPU has then the late CPU will still boot
1862 but with the feature disabled. On such a system, this option should
1865 config ARM64_PTR_AUTH_KERNEL
1866 bool "Use pointer authentication for kernel"
1868 depends on ARM64_PTR_AUTH
1869 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1870 # Modern compilers insert a .note.gnu.property section note for PAC
1871 # which is only understood by binutils starting with version 2.33.1.
1872 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1873 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1874 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1876 If the compiler supports the -mbranch-protection or
1877 -msign-return-address flag (e.g. GCC 7 or later), then this option
1878 will cause the kernel itself to be compiled with return address
1879 protection. In this case, and if the target hardware is known to
1880 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1881 disabled with minimal loss of protection.
1883 This feature works with FUNCTION_GRAPH_TRACER option only if
1884 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1886 config CC_HAS_BRANCH_PROT_PAC_RET
1887 # GCC 9 or later, clang 8 or later
1888 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1890 config CC_HAS_SIGN_RETURN_ADDRESS
1892 def_bool $(cc-option,-msign-return-address=all)
1894 config AS_HAS_ARMV8_3
1895 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1897 config AS_HAS_CFI_NEGATE_RA_STATE
1898 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1901 def_bool $(as-instr,.arch_extension rcpc)
1903 endmenu # "ARMv8.3 architectural features"
1905 menu "ARMv8.4 architectural features"
1907 config ARM64_AMU_EXTN
1908 bool "Enable support for the Activity Monitors Unit CPU extension"
1911 The activity monitors extension is an optional extension introduced
1912 by the ARMv8.4 CPU architecture. This enables support for version 1
1913 of the activity monitors architecture, AMUv1.
1915 To enable the use of this extension on CPUs that implement it, say Y.
1917 Note that for architectural reasons, firmware _must_ implement AMU
1918 support when running on CPUs that present the activity monitors
1919 extension. The required support is present in:
1920 * Version 1.5 and later of the ARM Trusted Firmware
1922 For kernels that have this configuration enabled but boot with broken
1923 firmware, you may need to say N here until the firmware is fixed.
1924 Otherwise you may experience firmware panics or lockups when
1925 accessing the counter registers. Even if you are not observing these
1926 symptoms, the values returned by the register reads might not
1927 correctly reflect reality. Most commonly, the value read will be 0,
1928 indicating that the counter is not enabled.
1930 config AS_HAS_ARMV8_4
1931 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1933 config ARM64_TLB_RANGE
1934 bool "Enable support for tlbi range feature"
1936 depends on AS_HAS_ARMV8_4
1938 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1939 range of input addresses.
1941 The feature introduces new assembly instructions, and they were
1942 support when binutils >= 2.30.
1944 endmenu # "ARMv8.4 architectural features"
1946 menu "ARMv8.5 architectural features"
1948 config AS_HAS_ARMV8_5
1949 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1952 bool "Branch Target Identification support"
1955 Branch Target Identification (part of the ARMv8.5 Extensions)
1956 provides a mechanism to limit the set of locations to which computed
1957 branch instructions such as BR or BLR can jump.
1959 To make use of BTI on CPUs that support it, say Y.
1961 BTI is intended to provide complementary protection to other control
1962 flow integrity protection mechanisms, such as the Pointer
1963 authentication mechanism provided as part of the ARMv8.3 Extensions.
1964 For this reason, it does not make sense to enable this option without
1965 also enabling support for pointer authentication. Thus, when
1966 enabling this option you should also select ARM64_PTR_AUTH=y.
1968 Userspace binaries must also be specifically compiled to make use of
1969 this mechanism. If you say N here or the hardware does not support
1970 BTI, such binaries can still run, but you get no additional
1971 enforcement of branch destinations.
1973 config ARM64_BTI_KERNEL
1974 bool "Use Branch Target Identification for kernel"
1976 depends on ARM64_BTI
1977 depends on ARM64_PTR_AUTH_KERNEL
1978 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1979 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1980 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1981 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1982 depends on !CC_IS_GCC
1983 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1984 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1985 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1987 Build the kernel with Branch Target Identification annotations
1988 and enable enforcement of this for kernel code. When this option
1989 is enabled and the system supports BTI all kernel code including
1990 modular code must have BTI enabled.
1992 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1993 # GCC 9 or later, clang 8 or later
1994 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1997 bool "Enable support for E0PD"
2000 E0PD (part of the ARMv8.5 extensions) allows us to ensure
2001 that EL0 accesses made via TTBR1 always fault in constant time,
2002 providing similar benefits to KASLR as those provided by KPTI, but
2003 with lower overhead and without disrupting legitimate access to
2004 kernel memory such as SPE.
2006 This option enables E0PD for TTBR1 where available.
2008 config ARM64_AS_HAS_MTE
2009 # Initial support for MTE went in binutils 2.32.0, checked with
2010 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2011 # as a late addition to the final architecture spec (LDGM/STGM)
2012 # is only supported in the newer 2.32.x and 2.33 binutils
2013 # versions, hence the extra "stgm" instruction check below.
2014 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2017 bool "Memory Tagging Extension support"
2019 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2020 depends on AS_HAS_ARMV8_5
2021 depends on AS_HAS_LSE_ATOMICS
2022 # Required for tag checking in the uaccess routines
2023 depends on ARM64_PAN
2024 select ARCH_HAS_SUBPAGE_FAULTS
2025 select ARCH_USES_HIGH_VMA_FLAGS
2026 select ARCH_USES_PG_ARCH_X
2028 Memory Tagging (part of the ARMv8.5 Extensions) provides
2029 architectural support for run-time, always-on detection of
2030 various classes of memory error to aid with software debugging
2031 to eliminate vulnerabilities arising from memory-unsafe
2034 This option enables the support for the Memory Tagging
2035 Extension at EL0 (i.e. for userspace).
2037 Selecting this option allows the feature to be detected at
2038 runtime. Any secondary CPU not implementing this feature will
2039 not be allowed a late bring-up.
2041 Userspace binaries that want to use this feature must
2042 explicitly opt in. The mechanism for the userspace is
2045 Documentation/arch/arm64/memory-tagging-extension.rst.
2047 endmenu # "ARMv8.5 architectural features"
2049 menu "ARMv8.7 architectural features"
2052 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2054 depends on ARM64_PAN
2056 Enhanced Privileged Access Never (EPAN) allows Privileged
2057 Access Never to be used with Execute-only mappings.
2059 The feature is detected at runtime, and will remain disabled
2060 if the cpu does not implement the feature.
2061 endmenu # "ARMv8.7 architectural features"
2064 bool "ARM Scalable Vector Extension support"
2067 The Scalable Vector Extension (SVE) is an extension to the AArch64
2068 execution state which complements and extends the SIMD functionality
2069 of the base architecture to support much larger vectors and to enable
2070 additional vectorisation opportunities.
2072 To enable use of this extension on CPUs that implement it, say Y.
2074 On CPUs that support the SVE2 extensions, this option will enable
2077 Note that for architectural reasons, firmware _must_ implement SVE
2078 support when running on SVE capable hardware. The required support
2081 * version 1.5 and later of the ARM Trusted Firmware
2082 * the AArch64 boot wrapper since commit 5e1261e08abf
2083 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2085 For other firmware implementations, consult the firmware documentation
2088 If you need the kernel to boot on SVE-capable hardware with broken
2089 firmware, you may need to say N here until you get your firmware
2090 fixed. Otherwise, you may experience firmware panics or lockups when
2091 booting the kernel. If unsure and you are not observing these
2092 symptoms, you should assume that it is safe to say Y.
2095 bool "ARM Scalable Matrix Extension support"
2097 depends on ARM64_SVE
2099 The Scalable Matrix Extension (SME) is an extension to the AArch64
2100 execution state which utilises a substantial subset of the SVE
2101 instruction set, together with the addition of new architectural
2102 register state capable of holding two dimensional matrix tiles to
2103 enable various matrix operations.
2105 config ARM64_PSEUDO_NMI
2106 bool "Support for NMI-like interrupts"
2109 Adds support for mimicking Non-Maskable Interrupts through the use of
2110 GIC interrupt priority. This support requires version 3 or later of
2113 This high priority configuration for interrupts needs to be
2114 explicitly enabled by setting the kernel parameter
2115 "irqchip.gicv3_pseudo_nmi" to 1.
2120 config ARM64_DEBUG_PRIORITY_MASKING
2121 bool "Debug interrupt priority masking"
2123 This adds runtime checks to functions enabling/disabling
2124 interrupts when using priority masking. The additional checks verify
2125 the validity of ICC_PMR_EL1 when calling concerned functions.
2128 endif # ARM64_PSEUDO_NMI
2131 bool "Build a relocatable kernel image" if EXPERT
2132 select ARCH_HAS_RELR
2135 This builds the kernel as a Position Independent Executable (PIE),
2136 which retains all relocation metadata required to relocate the
2137 kernel binary at runtime to a different virtual address than the
2138 address it was linked at.
2139 Since AArch64 uses the RELA relocation format, this requires a
2140 relocation pass at runtime even if the kernel is loaded at the
2141 same address it was linked at.
2143 config RANDOMIZE_BASE
2144 bool "Randomize the address of the kernel image"
2147 Randomizes the virtual address at which the kernel image is
2148 loaded, as a security feature that deters exploit attempts
2149 relying on knowledge of the location of kernel internals.
2151 It is the bootloader's job to provide entropy, by passing a
2152 random u64 value in /chosen/kaslr-seed at kernel entry.
2154 When booting via the UEFI stub, it will invoke the firmware's
2155 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2156 to the kernel proper. In addition, it will randomise the physical
2157 location of the kernel Image as well.
2161 config RANDOMIZE_MODULE_REGION_FULL
2162 bool "Randomize the module region over a 2 GB range"
2163 depends on RANDOMIZE_BASE
2166 Randomizes the location of the module region inside a 2 GB window
2167 covering the core kernel. This way, it is less likely for modules
2168 to leak information about the location of core kernel data structures
2169 but it does imply that function calls between modules and the core
2170 kernel will need to be resolved via veneers in the module PLT.
2172 When this option is not set, the module region will be randomized over
2173 a limited range that contains the [_stext, _etext] interval of the
2174 core kernel, so branch relocations are almost always in range unless
2175 the region is exhausted. In this particular case of region
2176 exhaustion, modules might be able to fall back to a larger 2GB area.
2178 config CC_HAVE_STACKPROTECTOR_SYSREG
2179 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2181 config STACKPROTECTOR_PER_TASK
2183 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2185 config UNWIND_PATCH_PAC_INTO_SCS
2186 bool "Enable shadow call stack dynamically using code patching"
2187 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2188 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2189 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2190 depends on SHADOW_CALL_STACK
2191 select UNWIND_TABLES
2194 endmenu # "Kernel Features"
2198 config ARM64_ACPI_PARKING_PROTOCOL
2199 bool "Enable support for the ARM64 ACPI parking protocol"
2202 Enable support for the ARM64 ACPI parking protocol. If disabled
2203 the kernel will not allow booting through the ARM64 ACPI parking
2204 protocol even if the corresponding data is present in the ACPI
2208 string "Default kernel command string"
2211 Provide a set of default command-line options at build time by
2212 entering them here. As a minimum, you should specify the the
2213 root device (e.g. root=/dev/nfs).
2216 prompt "Kernel command line type" if CMDLINE != ""
2217 default CMDLINE_FROM_BOOTLOADER
2219 Choose how the kernel will handle the provided default kernel
2220 command line string.
2222 config CMDLINE_FROM_BOOTLOADER
2223 bool "Use bootloader kernel arguments if available"
2225 Uses the command-line options passed by the boot loader. If
2226 the boot loader doesn't provide any, the default kernel command
2227 string provided in CMDLINE will be used.
2229 config CMDLINE_FORCE
2230 bool "Always use the default kernel command string"
2232 Always use the default kernel command string, even if the boot
2233 loader passes other arguments to the kernel.
2234 This is useful if you cannot or don't want to change the
2235 command-line options your boot loader passes to the kernel.
2243 bool "UEFI runtime support"
2244 depends on OF && !CPU_BIG_ENDIAN
2245 depends on KERNEL_MODE_NEON
2246 select ARCH_SUPPORTS_ACPI
2249 select EFI_PARAMS_FROM_FDT
2250 select EFI_RUNTIME_WRAPPERS
2252 select EFI_GENERIC_STUB
2253 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2256 This option provides support for runtime services provided
2257 by UEFI firmware (such as non-volatile variables, realtime
2258 clock, and platform reset). A UEFI stub is also provided to
2259 allow the kernel to be booted as an EFI application. This
2260 is only useful on systems that have UEFI firmware.
2263 bool "Enable support for SMBIOS (DMI) tables"
2267 This enables SMBIOS/DMI feature for systems.
2269 This option is only useful on systems that have UEFI firmware.
2270 However, even with this option, the resultant kernel should
2271 continue to boot on existing non-UEFI platforms.
2273 endmenu # "Boot options"
2275 menu "Power management options"
2277 source "kernel/power/Kconfig"
2279 config ARCH_HIBERNATION_POSSIBLE
2283 config ARCH_HIBERNATION_HEADER
2285 depends on HIBERNATION
2287 config ARCH_SUSPEND_POSSIBLE
2290 endmenu # "Power management options"
2292 menu "CPU Power Management"
2294 source "drivers/cpuidle/Kconfig"
2296 source "drivers/cpufreq/Kconfig"
2298 endmenu # "CPU Power Management"
2300 source "drivers/acpi/Kconfig"
2302 source "arch/arm64/kvm/Kconfig"