1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_SUPPORTS_PER_VMA_LOCK
99 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
100 select ARCH_WANT_DEFAULT_BPF_JIT
101 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
102 select ARCH_WANT_FRAME_POINTERS
103 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
104 select ARCH_WANT_LD_ORPHAN_WARN
105 select ARCH_WANTS_NO_INSTR
106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
107 select ARCH_HAS_UBSAN_SANITIZE_ALL
109 select ARM_ARCH_TIMER
111 select AUDIT_ARCH_COMPAT_GENERIC
112 select ARM_GIC_V2M if PCI
114 select ARM_GIC_V3_ITS if PCI
116 select BUILDTIME_TABLE_SORT
117 select CLONE_BACKWARDS
119 select CPU_PM if (SUSPEND || CPU_IDLE)
121 select DCACHE_WORD_ACCESS
122 select DYNAMIC_FTRACE if FUNCTION_TRACER
123 select DMA_BOUNCE_UNALIGNED_KMALLOC
124 select DMA_DIRECT_REMAP
127 select FUNCTION_ALIGNMENT_4B
128 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
129 select GENERIC_ALLOCATOR
130 select GENERIC_ARCH_TOPOLOGY
131 select GENERIC_CLOCKEVENTS_BROADCAST
132 select GENERIC_CPU_AUTOPROBE
133 select GENERIC_CPU_VULNERABILITIES
134 select GENERIC_EARLY_IOREMAP
135 select GENERIC_IDLE_POLL_SETUP
136 select GENERIC_IOREMAP
137 select GENERIC_IRQ_IPI
138 select GENERIC_IRQ_PROBE
139 select GENERIC_IRQ_SHOW
140 select GENERIC_IRQ_SHOW_LEVEL
141 select GENERIC_LIB_DEVMEM_IS_ALLOWED
142 select GENERIC_PCI_IOMAP
143 select GENERIC_PTDUMP
144 select GENERIC_SCHED_CLOCK
145 select GENERIC_SMP_IDLE_THREAD
146 select GENERIC_TIME_VSYSCALL
147 select GENERIC_GETTIMEOFDAY
148 select GENERIC_VDSO_TIME_NS
149 select HARDIRQS_SW_RESEND
154 select HAVE_ACPI_APEI if (ACPI && EFI)
155 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
156 select HAVE_ARCH_AUDITSYSCALL
157 select HAVE_ARCH_BITREVERSE
158 select HAVE_ARCH_COMPILER_H
159 select HAVE_ARCH_HUGE_VMALLOC
160 select HAVE_ARCH_HUGE_VMAP
161 select HAVE_ARCH_JUMP_LABEL
162 select HAVE_ARCH_JUMP_LABEL_RELATIVE
163 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
164 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
165 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
166 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
167 # Some instrumentation may be unsound, hence EXPERT
168 select HAVE_ARCH_KCSAN if EXPERT
169 select HAVE_ARCH_KFENCE
170 select HAVE_ARCH_KGDB
171 select HAVE_ARCH_MMAP_RND_BITS
172 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
173 select HAVE_ARCH_PREL32_RELOCATIONS
174 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
175 select HAVE_ARCH_SECCOMP_FILTER
176 select HAVE_ARCH_STACKLEAK
177 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
178 select HAVE_ARCH_TRACEHOOK
179 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
180 select HAVE_ARCH_VMAP_STACK
181 select HAVE_ARM_SMCCC
182 select HAVE_ASM_MODVERSIONS
184 select HAVE_C_RECORDMCOUNT
185 select HAVE_CMPXCHG_DOUBLE
186 select HAVE_CMPXCHG_LOCAL
187 select HAVE_CONTEXT_TRACKING_USER
188 select HAVE_DEBUG_KMEMLEAK
189 select HAVE_DMA_CONTIGUOUS
190 select HAVE_DYNAMIC_FTRACE
191 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
192 if $(cc-option,-fpatchable-function-entry=2)
193 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
194 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
195 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
196 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
197 !CC_OPTIMIZE_FOR_SIZE)
198 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
199 if DYNAMIC_FTRACE_WITH_ARGS
200 select HAVE_EFFICIENT_UNALIGNED_ACCESS
202 select HAVE_FTRACE_MCOUNT_RECORD
203 select HAVE_FUNCTION_TRACER
204 select HAVE_FUNCTION_ERROR_INJECTION
205 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
206 select HAVE_FUNCTION_GRAPH_TRACER
207 select HAVE_GCC_PLUGINS
208 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
209 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
210 select HAVE_HW_BREAKPOINT if PERF_EVENTS
211 select HAVE_IOREMAP_PROT
212 select HAVE_IRQ_TIME_ACCOUNTING
214 select HAVE_MOD_ARCH_SPECIFIC
216 select HAVE_PERF_EVENTS
217 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
218 select HAVE_PERF_REGS
219 select HAVE_PERF_USER_STACK_DUMP
220 select HAVE_PREEMPT_DYNAMIC_KEY
221 select HAVE_REGS_AND_STACK_ACCESS_API
222 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
223 select HAVE_FUNCTION_ARG_ACCESS_API
224 select MMU_GATHER_RCU_TABLE_FREE
226 select HAVE_STACKPROTECTOR
227 select HAVE_SYSCALL_TRACEPOINTS
229 select HAVE_KRETPROBES
230 select HAVE_GENERIC_VDSO
231 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
233 select IRQ_FORCED_THREADING
234 select KASAN_VMALLOC if KASAN
235 select LOCK_MM_AND_FIND_VMA
236 select MODULES_USE_ELF_RELA
237 select NEED_DMA_MAP_STATE
238 select NEED_SG_DMA_LENGTH
240 select OF_EARLY_FLATTREE
241 select PCI_DOMAINS_GENERIC if PCI
242 select PCI_ECAM if (ACPI && PCI)
243 select PCI_SYSCALL if PCI
248 select SYSCTL_EXCEPTION_TRACE
249 select THREAD_INFO_IN_TASK
250 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
251 select TRACE_IRQFLAGS_SUPPORT
252 select TRACE_IRQFLAGS_NMI_SUPPORT
253 select HAVE_SOFTIRQ_ON_OWN_STACK
255 ARM 64-bit (AArch64) Linux support.
257 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
259 # https://github.com/ClangBuiltLinux/linux/issues/1507
260 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
261 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
263 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
265 depends on $(cc-option,-fpatchable-function-entry=2)
266 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
274 config ARM64_PAGE_SHIFT
276 default 16 if ARM64_64K_PAGES
277 default 14 if ARM64_16K_PAGES
280 config ARM64_CONT_PTE_SHIFT
282 default 5 if ARM64_64K_PAGES
283 default 7 if ARM64_16K_PAGES
286 config ARM64_CONT_PMD_SHIFT
288 default 5 if ARM64_64K_PAGES
289 default 5 if ARM64_16K_PAGES
292 config ARCH_MMAP_RND_BITS_MIN
293 default 14 if ARM64_64K_PAGES
294 default 16 if ARM64_16K_PAGES
297 # max bits determined by the following formula:
298 # VA_BITS - PAGE_SHIFT - 3
299 config ARCH_MMAP_RND_BITS_MAX
300 default 19 if ARM64_VA_BITS=36
301 default 24 if ARM64_VA_BITS=39
302 default 27 if ARM64_VA_BITS=42
303 default 30 if ARM64_VA_BITS=47
304 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
305 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
306 default 33 if ARM64_VA_BITS=48
307 default 14 if ARM64_64K_PAGES
308 default 16 if ARM64_16K_PAGES
311 config ARCH_MMAP_RND_COMPAT_BITS_MIN
312 default 7 if ARM64_64K_PAGES
313 default 9 if ARM64_16K_PAGES
316 config ARCH_MMAP_RND_COMPAT_BITS_MAX
322 config STACKTRACE_SUPPORT
325 config ILLEGAL_POINTER_VALUE
327 default 0xdead000000000000
329 config LOCKDEP_SUPPORT
336 config GENERIC_BUG_RELATIVE_POINTERS
338 depends on GENERIC_BUG
340 config GENERIC_HWEIGHT
346 config GENERIC_CALIBRATE_DELAY
349 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
355 config KERNEL_MODE_NEON
358 config FIX_EARLYCON_MEM
361 config PGTABLE_LEVELS
363 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
364 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
365 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
366 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
367 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
368 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
370 config ARCH_SUPPORTS_UPROBES
373 config ARCH_PROC_KCORE_TEXT
376 config BROKEN_GAS_INST
377 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
379 config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
381 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0
382 # https://reviews.llvm.org/D75044
383 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000)
384 # GCC's __builtin_return_address() strips the PAC since 11.1.0,
385 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
386 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
387 default y if CC_IS_GCC && (GCC_VERSION >= 110100)
388 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
389 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000)
390 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000)
393 config KASAN_SHADOW_OFFSET
395 depends on KASAN_GENERIC || KASAN_SW_TAGS
396 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
397 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
398 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
399 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
400 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
401 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
402 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
403 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
404 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
405 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
406 default 0xffffffffffffffff
411 source "arch/arm64/Kconfig.platforms"
413 menu "Kernel Features"
415 menu "ARM errata workarounds via the alternatives framework"
417 config AMPERE_ERRATUM_AC03_CPU_38
418 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
421 This option adds an alternative code sequence to work around Ampere
422 erratum AC03_CPU_38 on AmpereOne.
424 The affected design reports FEAT_HAFDBS as not implemented in
425 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
426 as required by the architecture. The unadvertised HAFDBS
427 implementation suffers from an additional erratum where hardware
428 A/D updates can occur after a PTE has been marked invalid.
430 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
431 which avoids enabling unadvertised hardware Access Flag management
436 config ARM64_WORKAROUND_CLEAN_CACHE
439 config ARM64_ERRATUM_826319
440 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
442 select ARM64_WORKAROUND_CLEAN_CACHE
444 This option adds an alternative code sequence to work around ARM
445 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
446 AXI master interface and an L2 cache.
448 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
449 and is unable to accept a certain write via this interface, it will
450 not progress on read data presented on the read data channel and the
453 The workaround promotes data cache clean instructions to
454 data cache clean-and-invalidate.
455 Please note that this does not necessarily enable the workaround,
456 as it depends on the alternative framework, which will only patch
457 the kernel if an affected CPU is detected.
461 config ARM64_ERRATUM_827319
462 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
464 select ARM64_WORKAROUND_CLEAN_CACHE
466 This option adds an alternative code sequence to work around ARM
467 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
468 master interface and an L2 cache.
470 Under certain conditions this erratum can cause a clean line eviction
471 to occur at the same time as another transaction to the same address
472 on the AMBA 5 CHI interface, which can cause data corruption if the
473 interconnect reorders the two transactions.
475 The workaround promotes data cache clean instructions to
476 data cache clean-and-invalidate.
477 Please note that this does not necessarily enable the workaround,
478 as it depends on the alternative framework, which will only patch
479 the kernel if an affected CPU is detected.
483 config ARM64_ERRATUM_824069
484 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
486 select ARM64_WORKAROUND_CLEAN_CACHE
488 This option adds an alternative code sequence to work around ARM
489 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
490 to a coherent interconnect.
492 If a Cortex-A53 processor is executing a store or prefetch for
493 write instruction at the same time as a processor in another
494 cluster is executing a cache maintenance operation to the same
495 address, then this erratum might cause a clean cache line to be
496 incorrectly marked as dirty.
498 The workaround promotes data cache clean instructions to
499 data cache clean-and-invalidate.
500 Please note that this option does not necessarily enable the
501 workaround, as it depends on the alternative framework, which will
502 only patch the kernel if an affected CPU is detected.
506 config ARM64_ERRATUM_819472
507 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
509 select ARM64_WORKAROUND_CLEAN_CACHE
511 This option adds an alternative code sequence to work around ARM
512 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
513 present when it is connected to a coherent interconnect.
515 If the processor is executing a load and store exclusive sequence at
516 the same time as a processor in another cluster is executing a cache
517 maintenance operation to the same address, then this erratum might
518 cause data corruption.
520 The workaround promotes data cache clean instructions to
521 data cache clean-and-invalidate.
522 Please note that this does not necessarily enable the workaround,
523 as it depends on the alternative framework, which will only patch
524 the kernel if an affected CPU is detected.
528 config ARM64_ERRATUM_832075
529 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
532 This option adds an alternative code sequence to work around ARM
533 erratum 832075 on Cortex-A57 parts up to r1p2.
535 Affected Cortex-A57 parts might deadlock when exclusive load/store
536 instructions to Write-Back memory are mixed with Device loads.
538 The workaround is to promote device loads to use Load-Acquire
540 Please note that this does not necessarily enable the workaround,
541 as it depends on the alternative framework, which will only patch
542 the kernel if an affected CPU is detected.
546 config ARM64_ERRATUM_834220
547 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
551 This option adds an alternative code sequence to work around ARM
552 erratum 834220 on Cortex-A57 parts up to r1p2.
554 Affected Cortex-A57 parts might report a Stage 2 translation
555 fault as the result of a Stage 1 fault for load crossing a
556 page boundary when there is a permission or device memory
557 alignment fault at Stage 1 and a translation fault at Stage 2.
559 The workaround is to verify that the Stage 1 translation
560 doesn't generate a fault before handling the Stage 2 fault.
561 Please note that this does not necessarily enable the workaround,
562 as it depends on the alternative framework, which will only patch
563 the kernel if an affected CPU is detected.
567 config ARM64_ERRATUM_1742098
568 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
572 This option removes the AES hwcap for aarch32 user-space to
573 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
575 Affected parts may corrupt the AES state if an interrupt is
576 taken between a pair of AES instructions. These instructions
577 are only present if the cryptography extensions are present.
578 All software should have a fallback implementation for CPUs
579 that don't implement the cryptography extensions.
583 config ARM64_ERRATUM_845719
584 bool "Cortex-A53: 845719: a load might read incorrect data"
588 This option adds an alternative code sequence to work around ARM
589 erratum 845719 on Cortex-A53 parts up to r0p4.
591 When running a compat (AArch32) userspace on an affected Cortex-A53
592 part, a load at EL0 from a virtual address that matches the bottom 32
593 bits of the virtual address used by a recent load at (AArch64) EL1
594 might return incorrect data.
596 The workaround is to write the contextidr_el1 register on exception
597 return to a 32-bit task.
598 Please note that this does not necessarily enable the workaround,
599 as it depends on the alternative framework, which will only patch
600 the kernel if an affected CPU is detected.
604 config ARM64_ERRATUM_843419
605 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
608 This option links the kernel with '--fix-cortex-a53-843419' and
609 enables PLT support to replace certain ADRP instructions, which can
610 cause subsequent memory accesses to use an incorrect address on
611 Cortex-A53 parts up to r0p4.
615 config ARM64_LD_HAS_FIX_ERRATUM_843419
616 def_bool $(ld-option,--fix-cortex-a53-843419)
618 config ARM64_ERRATUM_1024718
619 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
622 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
624 Affected Cortex-A55 cores (all revisions) could cause incorrect
625 update of the hardware dirty bit when the DBM/AP bits are updated
626 without a break-before-make. The workaround is to disable the usage
627 of hardware DBM locally on the affected cores. CPUs not affected by
628 this erratum will continue to use the feature.
632 config ARM64_ERRATUM_1418040
633 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
637 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
638 errata 1188873 and 1418040.
640 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
641 cause register corruption when accessing the timer registers
642 from AArch32 userspace.
646 config ARM64_WORKAROUND_SPECULATIVE_AT
649 config ARM64_ERRATUM_1165522
650 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
652 select ARM64_WORKAROUND_SPECULATIVE_AT
654 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
656 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
657 corrupted TLBs by speculating an AT instruction during a guest
662 config ARM64_ERRATUM_1319367
663 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
665 select ARM64_WORKAROUND_SPECULATIVE_AT
667 This option adds work arounds for ARM Cortex-A57 erratum 1319537
668 and A72 erratum 1319367
670 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
671 speculating an AT instruction during a guest context switch.
675 config ARM64_ERRATUM_1530923
676 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
678 select ARM64_WORKAROUND_SPECULATIVE_AT
680 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
682 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
683 corrupted TLBs by speculating an AT instruction during a guest
688 config ARM64_WORKAROUND_REPEAT_TLBI
691 config ARM64_ERRATUM_2441007
692 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
694 select ARM64_WORKAROUND_REPEAT_TLBI
696 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
698 Under very rare circumstances, affected Cortex-A55 CPUs
699 may not handle a race between a break-before-make sequence on one
700 CPU, and another CPU accessing the same page. This could allow a
701 store to a page that has been unmapped.
703 Work around this by adding the affected CPUs to the list that needs
704 TLB sequences to be done twice.
708 config ARM64_ERRATUM_1286807
709 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
711 select ARM64_WORKAROUND_REPEAT_TLBI
713 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
715 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
716 address for a cacheable mapping of a location is being
717 accessed by a core while another core is remapping the virtual
718 address to a new physical page using the recommended
719 break-before-make sequence, then under very rare circumstances
720 TLBI+DSB completes before a read using the translation being
721 invalidated has been observed by other observers. The
722 workaround repeats the TLBI+DSB operation.
724 config ARM64_ERRATUM_1463225
725 bool "Cortex-A76: Software Step might prevent interrupt recognition"
728 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
730 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
731 of a system call instruction (SVC) can prevent recognition of
732 subsequent interrupts when software stepping is disabled in the
733 exception handler of the system call and either kernel debugging
734 is enabled or VHE is in use.
736 Work around the erratum by triggering a dummy step exception
737 when handling a system call from a task that is being stepped
738 in a VHE configuration of the kernel.
742 config ARM64_ERRATUM_1542419
743 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
746 This option adds a workaround for ARM Neoverse-N1 erratum
749 Affected Neoverse-N1 cores could execute a stale instruction when
750 modified by another CPU. The workaround depends on a firmware
753 Workaround the issue by hiding the DIC feature from EL0. This
754 forces user-space to perform cache maintenance.
758 config ARM64_ERRATUM_1508412
759 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
762 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
764 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
765 of a store-exclusive or read of PAR_EL1 and a load with device or
766 non-cacheable memory attributes. The workaround depends on a firmware
769 KVM guests must also have the workaround implemented or they can
772 Work around the issue by inserting DMB SY barriers around PAR_EL1
773 register reads and warning KVM users. The DMB barrier is sufficient
774 to prevent a speculative PAR_EL1 read.
778 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
781 config ARM64_ERRATUM_2051678
782 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
785 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
786 Affected Cortex-A510 might not respect the ordering rules for
787 hardware update of the page table's dirty bit. The workaround
788 is to not enable the feature on affected CPUs.
792 config ARM64_ERRATUM_2077057
793 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
796 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
797 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
798 expected, but a Pointer Authentication trap is taken instead. The
799 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
800 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
802 This can only happen when EL2 is stepping EL1.
804 When these conditions occur, the SPSR_EL2 value is unchanged from the
805 previous guest entry, and can be restored from the in-memory copy.
809 config ARM64_ERRATUM_2658417
810 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
813 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
814 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
815 BFMMLA or VMMLA instructions in rare circumstances when a pair of
816 A510 CPUs are using shared neon hardware. As the sharing is not
817 discoverable by the kernel, hide the BF16 HWCAP to indicate that
818 user-space should not be using these instructions.
822 config ARM64_ERRATUM_2119858
823 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
825 depends on CORESIGHT_TRBE
826 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
828 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
830 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
831 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
832 the event of a WRAP event.
834 Work around the issue by always making sure we move the TRBPTR_EL1 by
835 256 bytes before enabling the buffer and filling the first 256 bytes of
836 the buffer with ETM ignore packets upon disabling.
840 config ARM64_ERRATUM_2139208
841 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
843 depends on CORESIGHT_TRBE
844 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
846 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
848 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
849 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
850 the event of a WRAP event.
852 Work around the issue by always making sure we move the TRBPTR_EL1 by
853 256 bytes before enabling the buffer and filling the first 256 bytes of
854 the buffer with ETM ignore packets upon disabling.
858 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
861 config ARM64_ERRATUM_2054223
862 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
864 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
866 Enable workaround for ARM Cortex-A710 erratum 2054223
868 Affected cores may fail to flush the trace data on a TSB instruction, when
869 the PE is in trace prohibited state. This will cause losing a few bytes
872 Workaround is to issue two TSB consecutively on affected cores.
876 config ARM64_ERRATUM_2067961
877 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
879 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
881 Enable workaround for ARM Neoverse-N2 erratum 2067961
883 Affected cores may fail to flush the trace data on a TSB instruction, when
884 the PE is in trace prohibited state. This will cause losing a few bytes
887 Workaround is to issue two TSB consecutively on affected cores.
891 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
894 config ARM64_ERRATUM_2253138
895 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
896 depends on CORESIGHT_TRBE
898 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
900 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
902 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
903 for TRBE. Under some conditions, the TRBE might generate a write to the next
904 virtually addressed page following the last page of the TRBE address space
905 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
907 Work around this in the driver by always making sure that there is a
908 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
912 config ARM64_ERRATUM_2224489
913 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
914 depends on CORESIGHT_TRBE
916 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
918 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
920 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
921 for TRBE. Under some conditions, the TRBE might generate a write to the next
922 virtually addressed page following the last page of the TRBE address space
923 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
925 Work around this in the driver by always making sure that there is a
926 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
930 config ARM64_ERRATUM_2441009
931 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
933 select ARM64_WORKAROUND_REPEAT_TLBI
935 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
937 Under very rare circumstances, affected Cortex-A510 CPUs
938 may not handle a race between a break-before-make sequence on one
939 CPU, and another CPU accessing the same page. This could allow a
940 store to a page that has been unmapped.
942 Work around this by adding the affected CPUs to the list that needs
943 TLB sequences to be done twice.
947 config ARM64_ERRATUM_2064142
948 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
949 depends on CORESIGHT_TRBE
952 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
954 Affected Cortex-A510 core might fail to write into system registers after the
955 TRBE has been disabled. Under some conditions after the TRBE has been disabled
956 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
957 and TRBTRG_EL1 will be ignored and will not be effected.
959 Work around this in the driver by executing TSB CSYNC and DSB after collection
960 is stopped and before performing a system register write to one of the affected
965 config ARM64_ERRATUM_2038923
966 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
967 depends on CORESIGHT_TRBE
970 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
972 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
973 prohibited within the CPU. As a result, the trace buffer or trace buffer state
974 might be corrupted. This happens after TRBE buffer has been enabled by setting
975 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
976 execution changes from a context, in which trace is prohibited to one where it
977 isn't, or vice versa. In these mentioned conditions, the view of whether trace
978 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
979 the trace buffer state might be corrupted.
981 Work around this in the driver by preventing an inconsistent view of whether the
982 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
983 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
984 two ISB instructions if no ERET is to take place.
988 config ARM64_ERRATUM_1902691
989 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
990 depends on CORESIGHT_TRBE
993 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
995 Affected Cortex-A510 core might cause trace data corruption, when being written
996 into the memory. Effectively TRBE is broken and hence cannot be used to capture
999 Work around this problem in the driver by just preventing TRBE initialization on
1000 affected cpus. The firmware must have disabled the access to TRBE for the kernel
1001 on such implementations. This will cover the kernel for any firmware that doesn't
1006 config ARM64_ERRATUM_2457168
1007 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1008 depends on ARM64_AMU_EXTN
1011 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1013 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1014 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1015 incorrectly giving a significantly higher output value.
1017 Work around this problem by returning 0 when reading the affected counter in
1018 key locations that results in disabling all users of this counter. This effect
1019 is the same to firmware disabling affected counters.
1023 config ARM64_ERRATUM_2645198
1024 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1027 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1029 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1030 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1031 next instruction abort caused by permission fault.
1033 Only user-space does executable to non-executable permission transition via
1034 mprotect() system call. Workaround the problem by doing a break-before-make
1035 TLB invalidation, for all changes to executable user space mappings.
1039 config CAVIUM_ERRATUM_22375
1040 bool "Cavium erratum 22375, 24313"
1043 Enable workaround for errata 22375 and 24313.
1045 This implements two gicv3-its errata workarounds for ThunderX. Both
1046 with a small impact affecting only ITS table allocation.
1048 erratum 22375: only alloc 8MB table size
1049 erratum 24313: ignore memory access type
1051 The fixes are in ITS initialization and basically ignore memory access
1052 type and table size provided by the TYPER and BASER registers.
1056 config CAVIUM_ERRATUM_23144
1057 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1061 ITS SYNC command hang for cross node io and collections/cpu mapping.
1065 config CAVIUM_ERRATUM_23154
1066 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1069 The ThunderX GICv3 implementation requires a modified version for
1070 reading the IAR status to ensure data synchronization
1071 (access to icc_iar1_el1 is not sync'ed before and after).
1073 It also suffers from erratum 38545 (also present on Marvell's
1074 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1075 spuriously presented to the CPU interface.
1079 config CAVIUM_ERRATUM_27456
1080 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1083 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1084 instructions may cause the icache to become corrupted if it
1085 contains data for a non-current ASID. The fix is to
1086 invalidate the icache when changing the mm context.
1090 config CAVIUM_ERRATUM_30115
1091 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1094 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1095 1.2, and T83 Pass 1.0, KVM guest execution may disable
1096 interrupts in host. Trapping both GICv3 group-0 and group-1
1097 accesses sidesteps the issue.
1101 config CAVIUM_TX2_ERRATUM_219
1102 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1105 On Cavium ThunderX2, a load, store or prefetch instruction between a
1106 TTBR update and the corresponding context synchronizing operation can
1107 cause a spurious Data Abort to be delivered to any hardware thread in
1110 Work around the issue by avoiding the problematic code sequence and
1111 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1112 trap handler performs the corresponding register access, skips the
1113 instruction and ensures context synchronization by virtue of the
1118 config FUJITSU_ERRATUM_010001
1119 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1122 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1123 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1124 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1125 This fault occurs under a specific hardware condition when a
1126 load/store instruction performs an address translation using:
1127 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1128 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1129 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1130 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1132 The workaround is to ensure these bits are clear in TCR_ELx.
1133 The workaround only affects the Fujitsu-A64FX.
1137 config HISILICON_ERRATUM_161600802
1138 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1141 The HiSilicon Hip07 SoC uses the wrong redistributor base
1142 when issued ITS commands such as VMOVP and VMAPP, and requires
1143 a 128kB offset to be applied to the target address in this commands.
1147 config QCOM_FALKOR_ERRATUM_1003
1148 bool "Falkor E1003: Incorrect translation due to ASID change"
1151 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1152 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1153 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1154 then only for entries in the walk cache, since the leaf translation
1155 is unchanged. Work around the erratum by invalidating the walk cache
1156 entries for the trampoline before entering the kernel proper.
1158 config QCOM_FALKOR_ERRATUM_1009
1159 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1161 select ARM64_WORKAROUND_REPEAT_TLBI
1163 On Falkor v1, the CPU may prematurely complete a DSB following a
1164 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1165 one more time to fix the issue.
1169 config QCOM_QDF2400_ERRATUM_0065
1170 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1173 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1174 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1175 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1179 config QCOM_FALKOR_ERRATUM_E1041
1180 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1183 Falkor CPU may speculatively fetch instructions from an improper
1184 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1185 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1189 config NVIDIA_CARMEL_CNP_ERRATUM
1190 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1193 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1194 invalidate shared TLB entries installed by a different core, as it would
1195 on standard ARM cores.
1199 config ROCKCHIP_ERRATUM_3588001
1200 bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1203 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1204 This means, that its sharability feature may not be used, even though it
1205 is supported by the IP itself.
1209 config SOCIONEXT_SYNQUACER_PREITS
1210 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1213 Socionext Synquacer SoCs implement a separate h/w block to generate
1214 MSI doorbell writes with non-zero values for the device ID.
1218 endmenu # "ARM errata workarounds via the alternatives framework"
1222 default ARM64_4K_PAGES
1224 Page size (translation granule) configuration.
1226 config ARM64_4K_PAGES
1229 This feature enables 4KB pages support.
1231 config ARM64_16K_PAGES
1234 The system will use 16KB pages support. AArch32 emulation
1235 requires applications compiled with 16K (or a multiple of 16K)
1238 config ARM64_64K_PAGES
1241 This feature enables 64KB pages support (4KB by default)
1242 allowing only two levels of page tables and faster TLB
1243 look-up. AArch32 emulation requires applications compiled
1244 with 64K aligned segments.
1249 prompt "Virtual address space size"
1250 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1251 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1252 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1254 Allows choosing one of multiple possible virtual address
1255 space sizes. The level of translation table is determined by
1256 a combination of page size and virtual address space size.
1258 config ARM64_VA_BITS_36
1259 bool "36-bit" if EXPERT
1260 depends on ARM64_16K_PAGES
1262 config ARM64_VA_BITS_39
1264 depends on ARM64_4K_PAGES
1266 config ARM64_VA_BITS_42
1268 depends on ARM64_64K_PAGES
1270 config ARM64_VA_BITS_47
1272 depends on ARM64_16K_PAGES
1274 config ARM64_VA_BITS_48
1277 config ARM64_VA_BITS_52
1279 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1281 Enable 52-bit virtual addressing for userspace when explicitly
1282 requested via a hint to mmap(). The kernel will also use 52-bit
1283 virtual addresses for its own mappings (provided HW support for
1284 this feature is available, otherwise it reverts to 48-bit).
1286 NOTE: Enabling 52-bit virtual addressing in conjunction with
1287 ARMv8.3 Pointer Authentication will result in the PAC being
1288 reduced from 7 bits to 3 bits, which may have a significant
1289 impact on its susceptibility to brute-force attacks.
1291 If unsure, select 48-bit virtual addressing instead.
1295 config ARM64_FORCE_52BIT
1296 bool "Force 52-bit virtual addresses for userspace"
1297 depends on ARM64_VA_BITS_52 && EXPERT
1299 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1300 to maintain compatibility with older software by providing 48-bit VAs
1301 unless a hint is supplied to mmap.
1303 This configuration option disables the 48-bit compatibility logic, and
1304 forces all userspace addresses to be 52-bit on HW that supports it. One
1305 should only enable this configuration option for stress testing userspace
1306 memory management code. If unsure say N here.
1308 config ARM64_VA_BITS
1310 default 36 if ARM64_VA_BITS_36
1311 default 39 if ARM64_VA_BITS_39
1312 default 42 if ARM64_VA_BITS_42
1313 default 47 if ARM64_VA_BITS_47
1314 default 48 if ARM64_VA_BITS_48
1315 default 52 if ARM64_VA_BITS_52
1318 prompt "Physical address space size"
1319 default ARM64_PA_BITS_48
1321 Choose the maximum physical address range that the kernel will
1324 config ARM64_PA_BITS_48
1327 config ARM64_PA_BITS_52
1328 bool "52-bit (ARMv8.2)"
1329 depends on ARM64_64K_PAGES
1330 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1332 Enable support for a 52-bit physical address space, introduced as
1333 part of the ARMv8.2-LPA extension.
1335 With this enabled, the kernel will also continue to work on CPUs that
1336 do not support ARMv8.2-LPA, but with some added memory overhead (and
1337 minor performance overhead).
1341 config ARM64_PA_BITS
1343 default 48 if ARM64_PA_BITS_48
1344 default 52 if ARM64_PA_BITS_52
1348 default CPU_LITTLE_ENDIAN
1350 Select the endianness of data accesses performed by the CPU. Userspace
1351 applications will need to be compiled and linked for the endianness
1352 that is selected here.
1354 config CPU_BIG_ENDIAN
1355 bool "Build big-endian kernel"
1356 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1358 Say Y if you plan on running a kernel with a big-endian userspace.
1360 config CPU_LITTLE_ENDIAN
1361 bool "Build little-endian kernel"
1363 Say Y if you plan on running a kernel with a little-endian userspace.
1364 This is usually the case for distributions targeting arm64.
1369 bool "Multi-core scheduler support"
1371 Multi-core scheduler support improves the CPU scheduler's decision
1372 making when dealing with multi-core CPU chips at a cost of slightly
1373 increased overhead in some places. If unsure say N here.
1375 config SCHED_CLUSTER
1376 bool "Cluster scheduler support"
1378 Cluster scheduler support improves the CPU scheduler's decision
1379 making when dealing with machines that have clusters of CPUs.
1380 Cluster usually means a couple of CPUs which are placed closely
1381 by sharing mid-level caches, last-level cache tags or internal
1385 bool "SMT scheduler support"
1387 Improves the CPU scheduler's decision making when dealing with
1388 MultiThreading at a cost of slightly increased overhead in some
1389 places. If unsure say N here.
1392 int "Maximum number of CPUs (2-4096)"
1397 bool "Support for hot-pluggable CPUs"
1398 select GENERIC_IRQ_MIGRATION
1400 Say Y here to experiment with turning CPUs off and on. CPUs
1401 can be controlled through /sys/devices/system/cpu.
1403 # Common NUMA Features
1405 bool "NUMA Memory Allocation and Scheduler Support"
1406 select GENERIC_ARCH_NUMA
1407 select ACPI_NUMA if ACPI
1409 select HAVE_SETUP_PER_CPU_AREA
1410 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1411 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1412 select USE_PERCPU_NUMA_NODE_ID
1414 Enable NUMA (Non-Uniform Memory Access) support.
1416 The kernel will try to allocate memory used by a CPU on the
1417 local memory of the CPU and add some more
1418 NUMA awareness to the kernel.
1421 int "Maximum NUMA Nodes (as a power of 2)"
1426 Specify the maximum number of NUMA Nodes available on the target
1427 system. Increases memory reserved to accommodate various tables.
1429 source "kernel/Kconfig.hz"
1431 config ARCH_SPARSEMEM_ENABLE
1433 select SPARSEMEM_VMEMMAP_ENABLE
1434 select SPARSEMEM_VMEMMAP
1436 config HW_PERF_EVENTS
1440 # Supported by clang >= 7.0 or GCC >= 12.0.0
1441 config CC_HAVE_SHADOW_CALL_STACK
1442 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1445 bool "Enable paravirtualization code"
1447 This changes the kernel so it can modify itself when it is run
1448 under a hypervisor, potentially improving performance significantly
1449 over full virtualization.
1451 config PARAVIRT_TIME_ACCOUNTING
1452 bool "Paravirtual steal time accounting"
1455 Select this option to enable fine granularity task steal time
1456 accounting. Time spent executing other tasks in parallel with
1457 the current vCPU is discounted from the vCPU power. To account for
1458 that, there can be a small performance impact.
1460 If in doubt, say N here.
1463 depends on PM_SLEEP_SMP
1465 bool "kexec system call"
1467 kexec is a system call that implements the ability to shutdown your
1468 current kernel, and to start another kernel. It is like a reboot
1469 but it is independent of the system firmware. And like a reboot
1470 you can start any kernel with it, not just Linux.
1473 bool "kexec file based system call"
1475 select HAVE_IMA_KEXEC if IMA
1477 This is new version of kexec system call. This system call is
1478 file based and takes file descriptors as system call argument
1479 for kernel and initramfs as opposed to list of segments as
1480 accepted by previous system call.
1483 bool "Verify kernel signature during kexec_file_load() syscall"
1484 depends on KEXEC_FILE
1486 Select this option to verify a signature with loaded kernel
1487 image. If configured, any attempt of loading a image without
1488 valid signature will fail.
1490 In addition to that option, you need to enable signature
1491 verification for the corresponding kernel image type being
1492 loaded in order for this to work.
1494 config KEXEC_IMAGE_VERIFY_SIG
1495 bool "Enable Image signature verification support"
1497 depends on KEXEC_SIG
1498 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1500 Enable Image signature verification support.
1502 comment "Support for PE file signature verification disabled"
1503 depends on KEXEC_SIG
1504 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1507 bool "Build kdump crash kernel"
1509 Generate crash dump after being started by kexec. This should
1510 be normally only set in special crash dump kernels which are
1511 loaded in the main kernel with kexec-tools into a specially
1512 reserved region and then later executed after a crash by
1515 For more details see Documentation/admin-guide/kdump/kdump.rst
1519 depends on HIBERNATION || KEXEC_CORE
1526 bool "Xen guest support on ARM64"
1527 depends on ARM64 && OF
1531 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1533 # include/linux/mmzone.h requires the following to be true:
1535 # MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1537 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1539 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER |
1540 # ----+-------------------+--------------+-----------------+--------------------+
1541 # 4K | 27 | 12 | 15 | 10 |
1542 # 16K | 27 | 14 | 13 | 11 |
1543 # 64K | 29 | 16 | 13 | 13 |
1544 config ARCH_FORCE_MAX_ORDER
1546 default "13" if ARM64_64K_PAGES
1547 default "11" if ARM64_16K_PAGES
1550 The kernel page allocator limits the size of maximal physically
1551 contiguous allocations. The limit is called MAX_ORDER and it
1552 defines the maximal power of two of number of pages that can be
1553 allocated as a single contiguous block. This option allows
1554 overriding the default setting when ability to allocate very
1555 large blocks of physically contiguous memory is required.
1557 The maximal size of allocation cannot exceed the size of the
1558 section, so the value of MAX_ORDER should satisfy
1560 MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1562 Don't change if unsure.
1564 config UNMAP_KERNEL_AT_EL0
1565 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1568 Speculation attacks against some high-performance processors can
1569 be used to bypass MMU permission checks and leak kernel data to
1570 userspace. This can be defended against by unmapping the kernel
1571 when running in userspace, mapping it back in on exception entry
1572 via a trampoline page in the vector table.
1576 config MITIGATE_SPECTRE_BRANCH_HISTORY
1577 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1580 Speculation attacks against some high-performance processors can
1581 make use of branch history to influence future speculation.
1582 When taking an exception from user-space, a sequence of branches
1583 or a firmware call overwrites the branch history.
1585 config RODATA_FULL_DEFAULT_ENABLED
1586 bool "Apply r/o permissions of VM areas also to their linear aliases"
1589 Apply read-only attributes of VM areas to the linear alias of
1590 the backing pages as well. This prevents code or read-only data
1591 from being modified (inadvertently or intentionally) via another
1592 mapping of the same memory page. This additional enhancement can
1593 be turned off at runtime by passing rodata=[off|on] (and turned on
1594 with rodata=full if this option is set to 'n')
1596 This requires the linear region to be mapped down to pages,
1597 which may adversely affect performance in some cases.
1599 config ARM64_SW_TTBR0_PAN
1600 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1602 Enabling this option prevents the kernel from accessing
1603 user-space memory directly by pointing TTBR0_EL1 to a reserved
1604 zeroed area and reserved ASID. The user access routines
1605 restore the valid TTBR0_EL1 temporarily.
1607 config ARM64_TAGGED_ADDR_ABI
1608 bool "Enable the tagged user addresses syscall ABI"
1611 When this option is enabled, user applications can opt in to a
1612 relaxed ABI via prctl() allowing tagged addresses to be passed
1613 to system calls as pointer arguments. For details, see
1614 Documentation/arch/arm64/tagged-address-abi.rst.
1617 bool "Kernel support for 32-bit EL0"
1618 depends on ARM64_4K_PAGES || EXPERT
1620 select OLD_SIGSUSPEND3
1621 select COMPAT_OLD_SIGACTION
1623 This option enables support for a 32-bit EL0 running under a 64-bit
1624 kernel at EL1. AArch32-specific components such as system calls,
1625 the user helper functions, VFP support and the ptrace interface are
1626 handled appropriately by the kernel.
1628 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1629 that you will only be able to execute AArch32 binaries that were compiled
1630 with page size aligned segments.
1632 If you want to execute 32-bit userspace applications, say Y.
1636 config KUSER_HELPERS
1637 bool "Enable kuser helpers page for 32-bit applications"
1640 Warning: disabling this option may break 32-bit user programs.
1642 Provide kuser helpers to compat tasks. The kernel provides
1643 helper code to userspace in read only form at a fixed location
1644 to allow userspace to be independent of the CPU type fitted to
1645 the system. This permits binaries to be run on ARMv4 through
1646 to ARMv8 without modification.
1648 See Documentation/arch/arm/kernel_user_helpers.rst for details.
1650 However, the fixed address nature of these helpers can be used
1651 by ROP (return orientated programming) authors when creating
1654 If all of the binaries and libraries which run on your platform
1655 are built specifically for your platform, and make no use of
1656 these helpers, then you can turn this option off to hinder
1657 such exploits. However, in that case, if a binary or library
1658 relying on those helpers is run, it will not function correctly.
1660 Say N here only if you are absolutely certain that you do not
1661 need these helpers; otherwise, the safe option is to say Y.
1664 bool "Enable vDSO for 32-bit applications"
1665 depends on !CPU_BIG_ENDIAN
1666 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1667 select GENERIC_COMPAT_VDSO
1670 Place in the process address space of 32-bit applications an
1671 ELF shared object providing fast implementations of gettimeofday
1674 You must have a 32-bit build of glibc 2.22 or later for programs
1675 to seamlessly take advantage of this.
1677 config THUMB2_COMPAT_VDSO
1678 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1679 depends on COMPAT_VDSO
1682 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1683 otherwise with '-marm'.
1685 config COMPAT_ALIGNMENT_FIXUPS
1686 bool "Fix up misaligned multi-word loads and stores in user space"
1688 menuconfig ARMV8_DEPRECATED
1689 bool "Emulate deprecated/obsolete ARMv8 instructions"
1692 Legacy software support may require certain instructions
1693 that have been deprecated or obsoleted in the architecture.
1695 Enable this config to enable selective emulation of these
1702 config SWP_EMULATION
1703 bool "Emulate SWP/SWPB instructions"
1705 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1706 they are always undefined. Say Y here to enable software
1707 emulation of these instructions for userspace using LDXR/STXR.
1708 This feature can be controlled at runtime with the abi.swp
1709 sysctl which is disabled by default.
1711 In some older versions of glibc [<=2.8] SWP is used during futex
1712 trylock() operations with the assumption that the code will not
1713 be preempted. This invalid assumption may be more likely to fail
1714 with SWP emulation enabled, leading to deadlock of the user
1717 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1718 on an external transaction monitoring block called a global
1719 monitor to maintain update atomicity. If your system does not
1720 implement a global monitor, this option can cause programs that
1721 perform SWP operations to uncached memory to deadlock.
1725 config CP15_BARRIER_EMULATION
1726 bool "Emulate CP15 Barrier instructions"
1728 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1729 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1730 strongly recommended to use the ISB, DSB, and DMB
1731 instructions instead.
1733 Say Y here to enable software emulation of these
1734 instructions for AArch32 userspace code. When this option is
1735 enabled, CP15 barrier usage is traced which can help
1736 identify software that needs updating. This feature can be
1737 controlled at runtime with the abi.cp15_barrier sysctl.
1741 config SETEND_EMULATION
1742 bool "Emulate SETEND instruction"
1744 The SETEND instruction alters the data-endianness of the
1745 AArch32 EL0, and is deprecated in ARMv8.
1747 Say Y here to enable software emulation of the instruction
1748 for AArch32 userspace code. This feature can be controlled
1749 at runtime with the abi.setend sysctl.
1751 Note: All the cpus on the system must have mixed endian support at EL0
1752 for this feature to be enabled. If a new CPU - which doesn't support mixed
1753 endian - is hotplugged in after this feature has been enabled, there could
1754 be unexpected results in the applications.
1757 endif # ARMV8_DEPRECATED
1761 menu "ARMv8.1 architectural features"
1763 config ARM64_HW_AFDBM
1764 bool "Support for hardware updates of the Access and Dirty page flags"
1767 The ARMv8.1 architecture extensions introduce support for
1768 hardware updates of the access and dirty information in page
1769 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1770 capable processors, accesses to pages with PTE_AF cleared will
1771 set this bit instead of raising an access flag fault.
1772 Similarly, writes to read-only pages with the DBM bit set will
1773 clear the read-only bit (AP[2]) instead of raising a
1776 Kernels built with this configuration option enabled continue
1777 to work on pre-ARMv8.1 hardware and the performance impact is
1778 minimal. If unsure, say Y.
1781 bool "Enable support for Privileged Access Never (PAN)"
1784 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1785 prevents the kernel or hypervisor from accessing user-space (EL0)
1788 Choosing this option will cause any unprotected (not using
1789 copy_to_user et al) memory access to fail with a permission fault.
1791 The feature is detected at runtime, and will remain as a 'nop'
1792 instruction if the cpu does not implement the feature.
1795 def_bool $(as-instr,.arch_extension rcpc)
1797 config AS_HAS_LSE_ATOMICS
1798 def_bool $(as-instr,.arch_extension lse)
1800 config ARM64_LSE_ATOMICS
1802 default ARM64_USE_LSE_ATOMICS
1803 depends on AS_HAS_LSE_ATOMICS
1805 config ARM64_USE_LSE_ATOMICS
1806 bool "Atomic instructions"
1809 As part of the Large System Extensions, ARMv8.1 introduces new
1810 atomic instructions that are designed specifically to scale in
1813 Say Y here to make use of these instructions for the in-kernel
1814 atomic routines. This incurs a small overhead on CPUs that do
1815 not support these instructions and requires the kernel to be
1816 built with binutils >= 2.25 in order for the new instructions
1819 endmenu # "ARMv8.1 architectural features"
1821 menu "ARMv8.2 architectural features"
1823 config AS_HAS_ARMV8_2
1824 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1827 def_bool $(as-instr,.arch armv8.2-a+sha3)
1830 bool "Enable support for persistent memory"
1831 select ARCH_HAS_PMEM_API
1832 select ARCH_HAS_UACCESS_FLUSHCACHE
1834 Say Y to enable support for the persistent memory API based on the
1835 ARMv8.2 DCPoP feature.
1837 The feature is detected at runtime, and the kernel will use DC CVAC
1838 operations if DC CVAP is not supported (following the behaviour of
1839 DC CVAP itself if the system does not define a point of persistence).
1841 config ARM64_RAS_EXTN
1842 bool "Enable support for RAS CPU Extensions"
1845 CPUs that support the Reliability, Availability and Serviceability
1846 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1847 errors, classify them and report them to software.
1849 On CPUs with these extensions system software can use additional
1850 barriers to determine if faults are pending and read the
1851 classification from a new set of registers.
1853 Selecting this feature will allow the kernel to use these barriers
1854 and access the new registers if the system supports the extension.
1855 Platform RAS features may additionally depend on firmware support.
1858 bool "Enable support for Common Not Private (CNP) translations"
1860 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1862 Common Not Private (CNP) allows translation table entries to
1863 be shared between different PEs in the same inner shareable
1864 domain, so the hardware can use this fact to optimise the
1865 caching of such entries in the TLB.
1867 Selecting this option allows the CNP feature to be detected
1868 at runtime, and does not affect PEs that do not implement
1871 endmenu # "ARMv8.2 architectural features"
1873 menu "ARMv8.3 architectural features"
1875 config ARM64_PTR_AUTH
1876 bool "Enable support for pointer authentication"
1879 Pointer authentication (part of the ARMv8.3 Extensions) provides
1880 instructions for signing and authenticating pointers against secret
1881 keys, which can be used to mitigate Return Oriented Programming (ROP)
1884 This option enables these instructions at EL0 (i.e. for userspace).
1885 Choosing this option will cause the kernel to initialise secret keys
1886 for each process at exec() time, with these keys being
1887 context-switched along with the process.
1889 The feature is detected at runtime. If the feature is not present in
1890 hardware it will not be advertised to userspace/KVM guest nor will it
1893 If the feature is present on the boot CPU but not on a late CPU, then
1894 the late CPU will be parked. Also, if the boot CPU does not have
1895 address auth and the late CPU has then the late CPU will still boot
1896 but with the feature disabled. On such a system, this option should
1899 config ARM64_PTR_AUTH_KERNEL
1900 bool "Use pointer authentication for kernel"
1902 depends on ARM64_PTR_AUTH
1903 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1904 # Modern compilers insert a .note.gnu.property section note for PAC
1905 # which is only understood by binutils starting with version 2.33.1.
1906 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1907 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1908 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1910 If the compiler supports the -mbranch-protection or
1911 -msign-return-address flag (e.g. GCC 7 or later), then this option
1912 will cause the kernel itself to be compiled with return address
1913 protection. In this case, and if the target hardware is known to
1914 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1915 disabled with minimal loss of protection.
1917 This feature works with FUNCTION_GRAPH_TRACER option only if
1918 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1920 config CC_HAS_BRANCH_PROT_PAC_RET
1921 # GCC 9 or later, clang 8 or later
1922 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1924 config CC_HAS_SIGN_RETURN_ADDRESS
1926 def_bool $(cc-option,-msign-return-address=all)
1928 config AS_HAS_ARMV8_3
1929 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1931 config AS_HAS_CFI_NEGATE_RA_STATE
1932 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1934 endmenu # "ARMv8.3 architectural features"
1936 menu "ARMv8.4 architectural features"
1938 config ARM64_AMU_EXTN
1939 bool "Enable support for the Activity Monitors Unit CPU extension"
1942 The activity monitors extension is an optional extension introduced
1943 by the ARMv8.4 CPU architecture. This enables support for version 1
1944 of the activity monitors architecture, AMUv1.
1946 To enable the use of this extension on CPUs that implement it, say Y.
1948 Note that for architectural reasons, firmware _must_ implement AMU
1949 support when running on CPUs that present the activity monitors
1950 extension. The required support is present in:
1951 * Version 1.5 and later of the ARM Trusted Firmware
1953 For kernels that have this configuration enabled but boot with broken
1954 firmware, you may need to say N here until the firmware is fixed.
1955 Otherwise you may experience firmware panics or lockups when
1956 accessing the counter registers. Even if you are not observing these
1957 symptoms, the values returned by the register reads might not
1958 correctly reflect reality. Most commonly, the value read will be 0,
1959 indicating that the counter is not enabled.
1961 config AS_HAS_ARMV8_4
1962 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1964 config ARM64_TLB_RANGE
1965 bool "Enable support for tlbi range feature"
1967 depends on AS_HAS_ARMV8_4
1969 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1970 range of input addresses.
1972 The feature introduces new assembly instructions, and they were
1973 support when binutils >= 2.30.
1975 endmenu # "ARMv8.4 architectural features"
1977 menu "ARMv8.5 architectural features"
1979 config AS_HAS_ARMV8_5
1980 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1983 bool "Branch Target Identification support"
1986 Branch Target Identification (part of the ARMv8.5 Extensions)
1987 provides a mechanism to limit the set of locations to which computed
1988 branch instructions such as BR or BLR can jump.
1990 To make use of BTI on CPUs that support it, say Y.
1992 BTI is intended to provide complementary protection to other control
1993 flow integrity protection mechanisms, such as the Pointer
1994 authentication mechanism provided as part of the ARMv8.3 Extensions.
1995 For this reason, it does not make sense to enable this option without
1996 also enabling support for pointer authentication. Thus, when
1997 enabling this option you should also select ARM64_PTR_AUTH=y.
1999 Userspace binaries must also be specifically compiled to make use of
2000 this mechanism. If you say N here or the hardware does not support
2001 BTI, such binaries can still run, but you get no additional
2002 enforcement of branch destinations.
2004 config ARM64_BTI_KERNEL
2005 bool "Use Branch Target Identification for kernel"
2007 depends on ARM64_BTI
2008 depends on ARM64_PTR_AUTH_KERNEL
2009 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2010 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2011 depends on !CC_IS_GCC || GCC_VERSION >= 100100
2012 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2013 depends on !CC_IS_GCC
2014 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2015 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
2016 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2018 Build the kernel with Branch Target Identification annotations
2019 and enable enforcement of this for kernel code. When this option
2020 is enabled and the system supports BTI all kernel code including
2021 modular code must have BTI enabled.
2023 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2024 # GCC 9 or later, clang 8 or later
2025 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2028 bool "Enable support for E0PD"
2031 E0PD (part of the ARMv8.5 extensions) allows us to ensure
2032 that EL0 accesses made via TTBR1 always fault in constant time,
2033 providing similar benefits to KASLR as those provided by KPTI, but
2034 with lower overhead and without disrupting legitimate access to
2035 kernel memory such as SPE.
2037 This option enables E0PD for TTBR1 where available.
2039 config ARM64_AS_HAS_MTE
2040 # Initial support for MTE went in binutils 2.32.0, checked with
2041 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2042 # as a late addition to the final architecture spec (LDGM/STGM)
2043 # is only supported in the newer 2.32.x and 2.33 binutils
2044 # versions, hence the extra "stgm" instruction check below.
2045 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2048 bool "Memory Tagging Extension support"
2050 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2051 depends on AS_HAS_ARMV8_5
2052 depends on AS_HAS_LSE_ATOMICS
2053 # Required for tag checking in the uaccess routines
2054 depends on ARM64_PAN
2055 select ARCH_HAS_SUBPAGE_FAULTS
2056 select ARCH_USES_HIGH_VMA_FLAGS
2057 select ARCH_USES_PG_ARCH_X
2059 Memory Tagging (part of the ARMv8.5 Extensions) provides
2060 architectural support for run-time, always-on detection of
2061 various classes of memory error to aid with software debugging
2062 to eliminate vulnerabilities arising from memory-unsafe
2065 This option enables the support for the Memory Tagging
2066 Extension at EL0 (i.e. for userspace).
2068 Selecting this option allows the feature to be detected at
2069 runtime. Any secondary CPU not implementing this feature will
2070 not be allowed a late bring-up.
2072 Userspace binaries that want to use this feature must
2073 explicitly opt in. The mechanism for the userspace is
2076 Documentation/arch/arm64/memory-tagging-extension.rst.
2078 endmenu # "ARMv8.5 architectural features"
2080 menu "ARMv8.7 architectural features"
2083 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2085 depends on ARM64_PAN
2087 Enhanced Privileged Access Never (EPAN) allows Privileged
2088 Access Never to be used with Execute-only mappings.
2090 The feature is detected at runtime, and will remain disabled
2091 if the cpu does not implement the feature.
2092 endmenu # "ARMv8.7 architectural features"
2095 bool "ARM Scalable Vector Extension support"
2098 The Scalable Vector Extension (SVE) is an extension to the AArch64
2099 execution state which complements and extends the SIMD functionality
2100 of the base architecture to support much larger vectors and to enable
2101 additional vectorisation opportunities.
2103 To enable use of this extension on CPUs that implement it, say Y.
2105 On CPUs that support the SVE2 extensions, this option will enable
2108 Note that for architectural reasons, firmware _must_ implement SVE
2109 support when running on SVE capable hardware. The required support
2112 * version 1.5 and later of the ARM Trusted Firmware
2113 * the AArch64 boot wrapper since commit 5e1261e08abf
2114 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2116 For other firmware implementations, consult the firmware documentation
2119 If you need the kernel to boot on SVE-capable hardware with broken
2120 firmware, you may need to say N here until you get your firmware
2121 fixed. Otherwise, you may experience firmware panics or lockups when
2122 booting the kernel. If unsure and you are not observing these
2123 symptoms, you should assume that it is safe to say Y.
2126 bool "ARM Scalable Matrix Extension support"
2128 depends on ARM64_SVE
2130 The Scalable Matrix Extension (SME) is an extension to the AArch64
2131 execution state which utilises a substantial subset of the SVE
2132 instruction set, together with the addition of new architectural
2133 register state capable of holding two dimensional matrix tiles to
2134 enable various matrix operations.
2136 config ARM64_PSEUDO_NMI
2137 bool "Support for NMI-like interrupts"
2140 Adds support for mimicking Non-Maskable Interrupts through the use of
2141 GIC interrupt priority. This support requires version 3 or later of
2144 This high priority configuration for interrupts needs to be
2145 explicitly enabled by setting the kernel parameter
2146 "irqchip.gicv3_pseudo_nmi" to 1.
2151 config ARM64_DEBUG_PRIORITY_MASKING
2152 bool "Debug interrupt priority masking"
2154 This adds runtime checks to functions enabling/disabling
2155 interrupts when using priority masking. The additional checks verify
2156 the validity of ICC_PMR_EL1 when calling concerned functions.
2159 endif # ARM64_PSEUDO_NMI
2162 bool "Build a relocatable kernel image" if EXPERT
2163 select ARCH_HAS_RELR
2166 This builds the kernel as a Position Independent Executable (PIE),
2167 which retains all relocation metadata required to relocate the
2168 kernel binary at runtime to a different virtual address than the
2169 address it was linked at.
2170 Since AArch64 uses the RELA relocation format, this requires a
2171 relocation pass at runtime even if the kernel is loaded at the
2172 same address it was linked at.
2174 config RANDOMIZE_BASE
2175 bool "Randomize the address of the kernel image"
2178 Randomizes the virtual address at which the kernel image is
2179 loaded, as a security feature that deters exploit attempts
2180 relying on knowledge of the location of kernel internals.
2182 It is the bootloader's job to provide entropy, by passing a
2183 random u64 value in /chosen/kaslr-seed at kernel entry.
2185 When booting via the UEFI stub, it will invoke the firmware's
2186 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2187 to the kernel proper. In addition, it will randomise the physical
2188 location of the kernel Image as well.
2192 config RANDOMIZE_MODULE_REGION_FULL
2193 bool "Randomize the module region over a 2 GB range"
2194 depends on RANDOMIZE_BASE
2197 Randomizes the location of the module region inside a 2 GB window
2198 covering the core kernel. This way, it is less likely for modules
2199 to leak information about the location of core kernel data structures
2200 but it does imply that function calls between modules and the core
2201 kernel will need to be resolved via veneers in the module PLT.
2203 When this option is not set, the module region will be randomized over
2204 a limited range that contains the [_stext, _etext] interval of the
2205 core kernel, so branch relocations are almost always in range unless
2206 the region is exhausted. In this particular case of region
2207 exhaustion, modules might be able to fall back to a larger 2GB area.
2209 config CC_HAVE_STACKPROTECTOR_SYSREG
2210 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2212 config STACKPROTECTOR_PER_TASK
2214 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2216 config UNWIND_PATCH_PAC_INTO_SCS
2217 bool "Enable shadow call stack dynamically using code patching"
2218 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2219 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2220 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2221 depends on SHADOW_CALL_STACK
2222 select UNWIND_TABLES
2225 endmenu # "Kernel Features"
2229 config ARM64_ACPI_PARKING_PROTOCOL
2230 bool "Enable support for the ARM64 ACPI parking protocol"
2233 Enable support for the ARM64 ACPI parking protocol. If disabled
2234 the kernel will not allow booting through the ARM64 ACPI parking
2235 protocol even if the corresponding data is present in the ACPI
2239 string "Default kernel command string"
2242 Provide a set of default command-line options at build time by
2243 entering them here. As a minimum, you should specify the the
2244 root device (e.g. root=/dev/nfs).
2247 prompt "Kernel command line type" if CMDLINE != ""
2248 default CMDLINE_FROM_BOOTLOADER
2250 Choose how the kernel will handle the provided default kernel
2251 command line string.
2253 config CMDLINE_FROM_BOOTLOADER
2254 bool "Use bootloader kernel arguments if available"
2256 Uses the command-line options passed by the boot loader. If
2257 the boot loader doesn't provide any, the default kernel command
2258 string provided in CMDLINE will be used.
2260 config CMDLINE_FORCE
2261 bool "Always use the default kernel command string"
2263 Always use the default kernel command string, even if the boot
2264 loader passes other arguments to the kernel.
2265 This is useful if you cannot or don't want to change the
2266 command-line options your boot loader passes to the kernel.
2274 bool "UEFI runtime support"
2275 depends on OF && !CPU_BIG_ENDIAN
2276 depends on KERNEL_MODE_NEON
2277 select ARCH_SUPPORTS_ACPI
2280 select EFI_PARAMS_FROM_FDT
2281 select EFI_RUNTIME_WRAPPERS
2283 select EFI_GENERIC_STUB
2284 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2287 This option provides support for runtime services provided
2288 by UEFI firmware (such as non-volatile variables, realtime
2289 clock, and platform reset). A UEFI stub is also provided to
2290 allow the kernel to be booted as an EFI application. This
2291 is only useful on systems that have UEFI firmware.
2294 bool "Enable support for SMBIOS (DMI) tables"
2298 This enables SMBIOS/DMI feature for systems.
2300 This option is only useful on systems that have UEFI firmware.
2301 However, even with this option, the resultant kernel should
2302 continue to boot on existing non-UEFI platforms.
2304 endmenu # "Boot options"
2306 menu "Power management options"
2308 source "kernel/power/Kconfig"
2310 config ARCH_HIBERNATION_POSSIBLE
2314 config ARCH_HIBERNATION_HEADER
2316 depends on HIBERNATION
2318 config ARCH_SUSPEND_POSSIBLE
2321 endmenu # "Power management options"
2323 menu "CPU Power Management"
2325 source "drivers/cpuidle/Kconfig"
2327 source "drivers/cpufreq/Kconfig"
2329 endmenu # "CPU Power Management"
2331 source "drivers/acpi/Kconfig"
2333 source "arch/arm64/kvm/Kconfig"