1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
99 select ARCH_WANT_DEFAULT_BPF_JIT
100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
101 select ARCH_WANT_FRAME_POINTERS
102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
103 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
104 select ARCH_WANT_LD_ORPHAN_WARN
105 select ARCH_WANTS_NO_INSTR
106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
107 select ARCH_HAS_UBSAN_SANITIZE_ALL
109 select ARM_ARCH_TIMER
111 select AUDIT_ARCH_COMPAT_GENERIC
112 select ARM_GIC_V2M if PCI
114 select ARM_GIC_V3_ITS if PCI
116 select BUILDTIME_TABLE_SORT
117 select CLONE_BACKWARDS
119 select CPU_PM if (SUSPEND || CPU_IDLE)
121 select DCACHE_WORD_ACCESS
122 select DYNAMIC_FTRACE if FUNCTION_TRACER
123 select DMA_DIRECT_REMAP
126 select FUNCTION_ALIGNMENT_4B
127 select GENERIC_ALLOCATOR
128 select GENERIC_ARCH_TOPOLOGY
129 select GENERIC_CLOCKEVENTS_BROADCAST
130 select GENERIC_CPU_AUTOPROBE
131 select GENERIC_CPU_VULNERABILITIES
132 select GENERIC_EARLY_IOREMAP
133 select GENERIC_IDLE_POLL_SETUP
134 select GENERIC_IOREMAP
135 select GENERIC_IRQ_IPI
136 select GENERIC_IRQ_PROBE
137 select GENERIC_IRQ_SHOW
138 select GENERIC_IRQ_SHOW_LEVEL
139 select GENERIC_LIB_DEVMEM_IS_ALLOWED
140 select GENERIC_PCI_IOMAP
141 select GENERIC_PTDUMP
142 select GENERIC_SCHED_CLOCK
143 select GENERIC_SMP_IDLE_THREAD
144 select GENERIC_TIME_VSYSCALL
145 select GENERIC_GETTIMEOFDAY
146 select GENERIC_VDSO_TIME_NS
147 select HARDIRQS_SW_RESEND
151 select HAVE_ACPI_APEI if (ACPI && EFI)
152 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
153 select HAVE_ARCH_AUDITSYSCALL
154 select HAVE_ARCH_BITREVERSE
155 select HAVE_ARCH_COMPILER_H
156 select HAVE_ARCH_HUGE_VMALLOC
157 select HAVE_ARCH_HUGE_VMAP
158 select HAVE_ARCH_JUMP_LABEL
159 select HAVE_ARCH_JUMP_LABEL_RELATIVE
160 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
161 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
162 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
163 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
164 # Some instrumentation may be unsound, hence EXPERT
165 select HAVE_ARCH_KCSAN if EXPERT
166 select HAVE_ARCH_KFENCE
167 select HAVE_ARCH_KGDB
168 select HAVE_ARCH_MMAP_RND_BITS
169 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
170 select HAVE_ARCH_PREL32_RELOCATIONS
171 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
172 select HAVE_ARCH_SECCOMP_FILTER
173 select HAVE_ARCH_STACKLEAK
174 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
175 select HAVE_ARCH_TRACEHOOK
176 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
177 select HAVE_ARCH_VMAP_STACK
178 select HAVE_ARM_SMCCC
179 select HAVE_ASM_MODVERSIONS
181 select HAVE_C_RECORDMCOUNT
182 select HAVE_CMPXCHG_DOUBLE
183 select HAVE_CMPXCHG_LOCAL
184 select HAVE_CONTEXT_TRACKING_USER
185 select HAVE_DEBUG_KMEMLEAK
186 select HAVE_DMA_CONTIGUOUS
187 select HAVE_DYNAMIC_FTRACE
188 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
189 if $(cc-option,-fpatchable-function-entry=2)
190 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
191 if DYNAMIC_FTRACE_WITH_ARGS
192 select HAVE_EFFICIENT_UNALIGNED_ACCESS
194 select HAVE_FTRACE_MCOUNT_RECORD
195 select HAVE_FUNCTION_TRACER
196 select HAVE_FUNCTION_ERROR_INJECTION
197 select HAVE_FUNCTION_GRAPH_TRACER
198 select HAVE_GCC_PLUGINS
199 select HAVE_HW_BREAKPOINT if PERF_EVENTS
200 select HAVE_IOREMAP_PROT
201 select HAVE_IRQ_TIME_ACCOUNTING
204 select HAVE_PERF_EVENTS
205 select HAVE_PERF_REGS
206 select HAVE_PERF_USER_STACK_DUMP
207 select HAVE_PREEMPT_DYNAMIC_KEY
208 select HAVE_REGS_AND_STACK_ACCESS_API
209 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
210 select HAVE_FUNCTION_ARG_ACCESS_API
211 select MMU_GATHER_RCU_TABLE_FREE
213 select HAVE_STACKPROTECTOR
214 select HAVE_SYSCALL_TRACEPOINTS
216 select HAVE_KRETPROBES
217 select HAVE_GENERIC_VDSO
219 select IRQ_FORCED_THREADING
220 select KASAN_VMALLOC if KASAN
221 select MODULES_USE_ELF_RELA
222 select NEED_DMA_MAP_STATE
223 select NEED_SG_DMA_LENGTH
225 select OF_EARLY_FLATTREE
226 select PCI_DOMAINS_GENERIC if PCI
227 select PCI_ECAM if (ACPI && PCI)
228 select PCI_SYSCALL if PCI
233 select SYSCTL_EXCEPTION_TRACE
234 select THREAD_INFO_IN_TASK
235 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
236 select TRACE_IRQFLAGS_SUPPORT
237 select TRACE_IRQFLAGS_NMI_SUPPORT
238 select HAVE_SOFTIRQ_ON_OWN_STACK
240 ARM 64-bit (AArch64) Linux support.
242 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
244 # https://github.com/ClangBuiltLinux/linux/issues/1507
245 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
246 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
248 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
250 depends on $(cc-option,-fpatchable-function-entry=2)
251 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
259 config ARM64_PAGE_SHIFT
261 default 16 if ARM64_64K_PAGES
262 default 14 if ARM64_16K_PAGES
265 config ARM64_CONT_PTE_SHIFT
267 default 5 if ARM64_64K_PAGES
268 default 7 if ARM64_16K_PAGES
271 config ARM64_CONT_PMD_SHIFT
273 default 5 if ARM64_64K_PAGES
274 default 5 if ARM64_16K_PAGES
277 config ARCH_MMAP_RND_BITS_MIN
278 default 14 if ARM64_64K_PAGES
279 default 16 if ARM64_16K_PAGES
282 # max bits determined by the following formula:
283 # VA_BITS - PAGE_SHIFT - 3
284 config ARCH_MMAP_RND_BITS_MAX
285 default 19 if ARM64_VA_BITS=36
286 default 24 if ARM64_VA_BITS=39
287 default 27 if ARM64_VA_BITS=42
288 default 30 if ARM64_VA_BITS=47
289 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
290 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
291 default 33 if ARM64_VA_BITS=48
292 default 14 if ARM64_64K_PAGES
293 default 16 if ARM64_16K_PAGES
296 config ARCH_MMAP_RND_COMPAT_BITS_MIN
297 default 7 if ARM64_64K_PAGES
298 default 9 if ARM64_16K_PAGES
301 config ARCH_MMAP_RND_COMPAT_BITS_MAX
307 config STACKTRACE_SUPPORT
310 config ILLEGAL_POINTER_VALUE
312 default 0xdead000000000000
314 config LOCKDEP_SUPPORT
321 config GENERIC_BUG_RELATIVE_POINTERS
323 depends on GENERIC_BUG
325 config GENERIC_HWEIGHT
331 config GENERIC_CALIBRATE_DELAY
334 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
340 config KERNEL_MODE_NEON
343 config FIX_EARLYCON_MEM
346 config PGTABLE_LEVELS
348 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
349 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
350 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
351 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
352 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
353 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
355 config ARCH_SUPPORTS_UPROBES
358 config ARCH_PROC_KCORE_TEXT
361 config BROKEN_GAS_INST
362 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
364 config KASAN_SHADOW_OFFSET
366 depends on KASAN_GENERIC || KASAN_SW_TAGS
367 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
368 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
369 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
370 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
371 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
372 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
373 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
374 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
375 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
376 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
377 default 0xffffffffffffffff
382 source "arch/arm64/Kconfig.platforms"
384 menu "Kernel Features"
386 menu "ARM errata workarounds via the alternatives framework"
388 config ARM64_WORKAROUND_CLEAN_CACHE
391 config ARM64_ERRATUM_826319
392 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
394 select ARM64_WORKAROUND_CLEAN_CACHE
396 This option adds an alternative code sequence to work around ARM
397 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
398 AXI master interface and an L2 cache.
400 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
401 and is unable to accept a certain write via this interface, it will
402 not progress on read data presented on the read data channel and the
405 The workaround promotes data cache clean instructions to
406 data cache clean-and-invalidate.
407 Please note that this does not necessarily enable the workaround,
408 as it depends on the alternative framework, which will only patch
409 the kernel if an affected CPU is detected.
413 config ARM64_ERRATUM_827319
414 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
416 select ARM64_WORKAROUND_CLEAN_CACHE
418 This option adds an alternative code sequence to work around ARM
419 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
420 master interface and an L2 cache.
422 Under certain conditions this erratum can cause a clean line eviction
423 to occur at the same time as another transaction to the same address
424 on the AMBA 5 CHI interface, which can cause data corruption if the
425 interconnect reorders the two transactions.
427 The workaround promotes data cache clean instructions to
428 data cache clean-and-invalidate.
429 Please note that this does not necessarily enable the workaround,
430 as it depends on the alternative framework, which will only patch
431 the kernel if an affected CPU is detected.
435 config ARM64_ERRATUM_824069
436 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
438 select ARM64_WORKAROUND_CLEAN_CACHE
440 This option adds an alternative code sequence to work around ARM
441 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
442 to a coherent interconnect.
444 If a Cortex-A53 processor is executing a store or prefetch for
445 write instruction at the same time as a processor in another
446 cluster is executing a cache maintenance operation to the same
447 address, then this erratum might cause a clean cache line to be
448 incorrectly marked as dirty.
450 The workaround promotes data cache clean instructions to
451 data cache clean-and-invalidate.
452 Please note that this option does not necessarily enable the
453 workaround, as it depends on the alternative framework, which will
454 only patch the kernel if an affected CPU is detected.
458 config ARM64_ERRATUM_819472
459 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
461 select ARM64_WORKAROUND_CLEAN_CACHE
463 This option adds an alternative code sequence to work around ARM
464 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
465 present when it is connected to a coherent interconnect.
467 If the processor is executing a load and store exclusive sequence at
468 the same time as a processor in another cluster is executing a cache
469 maintenance operation to the same address, then this erratum might
470 cause data corruption.
472 The workaround promotes data cache clean instructions to
473 data cache clean-and-invalidate.
474 Please note that this does not necessarily enable the workaround,
475 as it depends on the alternative framework, which will only patch
476 the kernel if an affected CPU is detected.
480 config ARM64_ERRATUM_832075
481 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
484 This option adds an alternative code sequence to work around ARM
485 erratum 832075 on Cortex-A57 parts up to r1p2.
487 Affected Cortex-A57 parts might deadlock when exclusive load/store
488 instructions to Write-Back memory are mixed with Device loads.
490 The workaround is to promote device loads to use Load-Acquire
492 Please note that this does not necessarily enable the workaround,
493 as it depends on the alternative framework, which will only patch
494 the kernel if an affected CPU is detected.
498 config ARM64_ERRATUM_834220
499 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
503 This option adds an alternative code sequence to work around ARM
504 erratum 834220 on Cortex-A57 parts up to r1p2.
506 Affected Cortex-A57 parts might report a Stage 2 translation
507 fault as the result of a Stage 1 fault for load crossing a
508 page boundary when there is a permission or device memory
509 alignment fault at Stage 1 and a translation fault at Stage 2.
511 The workaround is to verify that the Stage 1 translation
512 doesn't generate a fault before handling the Stage 2 fault.
513 Please note that this does not necessarily enable the workaround,
514 as it depends on the alternative framework, which will only patch
515 the kernel if an affected CPU is detected.
519 config ARM64_ERRATUM_1742098
520 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
524 This option removes the AES hwcap for aarch32 user-space to
525 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
527 Affected parts may corrupt the AES state if an interrupt is
528 taken between a pair of AES instructions. These instructions
529 are only present if the cryptography extensions are present.
530 All software should have a fallback implementation for CPUs
531 that don't implement the cryptography extensions.
535 config ARM64_ERRATUM_845719
536 bool "Cortex-A53: 845719: a load might read incorrect data"
540 This option adds an alternative code sequence to work around ARM
541 erratum 845719 on Cortex-A53 parts up to r0p4.
543 When running a compat (AArch32) userspace on an affected Cortex-A53
544 part, a load at EL0 from a virtual address that matches the bottom 32
545 bits of the virtual address used by a recent load at (AArch64) EL1
546 might return incorrect data.
548 The workaround is to write the contextidr_el1 register on exception
549 return to a 32-bit task.
550 Please note that this does not necessarily enable the workaround,
551 as it depends on the alternative framework, which will only patch
552 the kernel if an affected CPU is detected.
556 config ARM64_ERRATUM_843419
557 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
559 select ARM64_MODULE_PLTS if MODULES
561 This option links the kernel with '--fix-cortex-a53-843419' and
562 enables PLT support to replace certain ADRP instructions, which can
563 cause subsequent memory accesses to use an incorrect address on
564 Cortex-A53 parts up to r0p4.
568 config ARM64_LD_HAS_FIX_ERRATUM_843419
569 def_bool $(ld-option,--fix-cortex-a53-843419)
571 config ARM64_ERRATUM_1024718
572 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
575 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
577 Affected Cortex-A55 cores (all revisions) could cause incorrect
578 update of the hardware dirty bit when the DBM/AP bits are updated
579 without a break-before-make. The workaround is to disable the usage
580 of hardware DBM locally on the affected cores. CPUs not affected by
581 this erratum will continue to use the feature.
585 config ARM64_ERRATUM_1418040
586 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
590 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
591 errata 1188873 and 1418040.
593 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
594 cause register corruption when accessing the timer registers
595 from AArch32 userspace.
599 config ARM64_WORKAROUND_SPECULATIVE_AT
602 config ARM64_ERRATUM_1165522
603 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
605 select ARM64_WORKAROUND_SPECULATIVE_AT
607 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
609 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
610 corrupted TLBs by speculating an AT instruction during a guest
615 config ARM64_ERRATUM_1319367
616 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
618 select ARM64_WORKAROUND_SPECULATIVE_AT
620 This option adds work arounds for ARM Cortex-A57 erratum 1319537
621 and A72 erratum 1319367
623 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
624 speculating an AT instruction during a guest context switch.
628 config ARM64_ERRATUM_1530923
629 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
631 select ARM64_WORKAROUND_SPECULATIVE_AT
633 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
635 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
636 corrupted TLBs by speculating an AT instruction during a guest
641 config ARM64_WORKAROUND_REPEAT_TLBI
644 config ARM64_ERRATUM_2441007
645 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
647 select ARM64_WORKAROUND_REPEAT_TLBI
649 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
651 Under very rare circumstances, affected Cortex-A55 CPUs
652 may not handle a race between a break-before-make sequence on one
653 CPU, and another CPU accessing the same page. This could allow a
654 store to a page that has been unmapped.
656 Work around this by adding the affected CPUs to the list that needs
657 TLB sequences to be done twice.
661 config ARM64_ERRATUM_1286807
662 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
664 select ARM64_WORKAROUND_REPEAT_TLBI
666 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
668 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
669 address for a cacheable mapping of a location is being
670 accessed by a core while another core is remapping the virtual
671 address to a new physical page using the recommended
672 break-before-make sequence, then under very rare circumstances
673 TLBI+DSB completes before a read using the translation being
674 invalidated has been observed by other observers. The
675 workaround repeats the TLBI+DSB operation.
677 config ARM64_ERRATUM_1463225
678 bool "Cortex-A76: Software Step might prevent interrupt recognition"
681 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
683 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
684 of a system call instruction (SVC) can prevent recognition of
685 subsequent interrupts when software stepping is disabled in the
686 exception handler of the system call and either kernel debugging
687 is enabled or VHE is in use.
689 Work around the erratum by triggering a dummy step exception
690 when handling a system call from a task that is being stepped
691 in a VHE configuration of the kernel.
695 config ARM64_ERRATUM_1542419
696 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
699 This option adds a workaround for ARM Neoverse-N1 erratum
702 Affected Neoverse-N1 cores could execute a stale instruction when
703 modified by another CPU. The workaround depends on a firmware
706 Workaround the issue by hiding the DIC feature from EL0. This
707 forces user-space to perform cache maintenance.
711 config ARM64_ERRATUM_1508412
712 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
715 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
717 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
718 of a store-exclusive or read of PAR_EL1 and a load with device or
719 non-cacheable memory attributes. The workaround depends on a firmware
722 KVM guests must also have the workaround implemented or they can
725 Work around the issue by inserting DMB SY barriers around PAR_EL1
726 register reads and warning KVM users. The DMB barrier is sufficient
727 to prevent a speculative PAR_EL1 read.
731 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
734 config ARM64_ERRATUM_2051678
735 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
738 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
739 Affected Cortex-A510 might not respect the ordering rules for
740 hardware update of the page table's dirty bit. The workaround
741 is to not enable the feature on affected CPUs.
745 config ARM64_ERRATUM_2077057
746 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
749 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
750 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
751 expected, but a Pointer Authentication trap is taken instead. The
752 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
753 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
755 This can only happen when EL2 is stepping EL1.
757 When these conditions occur, the SPSR_EL2 value is unchanged from the
758 previous guest entry, and can be restored from the in-memory copy.
762 config ARM64_ERRATUM_2658417
763 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
766 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
767 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
768 BFMMLA or VMMLA instructions in rare circumstances when a pair of
769 A510 CPUs are using shared neon hardware. As the sharing is not
770 discoverable by the kernel, hide the BF16 HWCAP to indicate that
771 user-space should not be using these instructions.
775 config ARM64_ERRATUM_2119858
776 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
778 depends on CORESIGHT_TRBE
779 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
781 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
783 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
784 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
785 the event of a WRAP event.
787 Work around the issue by always making sure we move the TRBPTR_EL1 by
788 256 bytes before enabling the buffer and filling the first 256 bytes of
789 the buffer with ETM ignore packets upon disabling.
793 config ARM64_ERRATUM_2139208
794 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
796 depends on CORESIGHT_TRBE
797 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
799 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
801 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
802 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
803 the event of a WRAP event.
805 Work around the issue by always making sure we move the TRBPTR_EL1 by
806 256 bytes before enabling the buffer and filling the first 256 bytes of
807 the buffer with ETM ignore packets upon disabling.
811 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
814 config ARM64_ERRATUM_2054223
815 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
817 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
819 Enable workaround for ARM Cortex-A710 erratum 2054223
821 Affected cores may fail to flush the trace data on a TSB instruction, when
822 the PE is in trace prohibited state. This will cause losing a few bytes
825 Workaround is to issue two TSB consecutively on affected cores.
829 config ARM64_ERRATUM_2067961
830 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
832 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
834 Enable workaround for ARM Neoverse-N2 erratum 2067961
836 Affected cores may fail to flush the trace data on a TSB instruction, when
837 the PE is in trace prohibited state. This will cause losing a few bytes
840 Workaround is to issue two TSB consecutively on affected cores.
844 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
847 config ARM64_ERRATUM_2253138
848 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
849 depends on CORESIGHT_TRBE
851 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
853 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
855 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
856 for TRBE. Under some conditions, the TRBE might generate a write to the next
857 virtually addressed page following the last page of the TRBE address space
858 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
860 Work around this in the driver by always making sure that there is a
861 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
865 config ARM64_ERRATUM_2224489
866 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
867 depends on CORESIGHT_TRBE
869 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
871 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
873 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
874 for TRBE. Under some conditions, the TRBE might generate a write to the next
875 virtually addressed page following the last page of the TRBE address space
876 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
878 Work around this in the driver by always making sure that there is a
879 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
883 config ARM64_ERRATUM_2441009
884 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
886 select ARM64_WORKAROUND_REPEAT_TLBI
888 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
890 Under very rare circumstances, affected Cortex-A510 CPUs
891 may not handle a race between a break-before-make sequence on one
892 CPU, and another CPU accessing the same page. This could allow a
893 store to a page that has been unmapped.
895 Work around this by adding the affected CPUs to the list that needs
896 TLB sequences to be done twice.
900 config ARM64_ERRATUM_2064142
901 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
902 depends on CORESIGHT_TRBE
905 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
907 Affected Cortex-A510 core might fail to write into system registers after the
908 TRBE has been disabled. Under some conditions after the TRBE has been disabled
909 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
910 and TRBTRG_EL1 will be ignored and will not be effected.
912 Work around this in the driver by executing TSB CSYNC and DSB after collection
913 is stopped and before performing a system register write to one of the affected
918 config ARM64_ERRATUM_2038923
919 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
920 depends on CORESIGHT_TRBE
923 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
925 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
926 prohibited within the CPU. As a result, the trace buffer or trace buffer state
927 might be corrupted. This happens after TRBE buffer has been enabled by setting
928 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
929 execution changes from a context, in which trace is prohibited to one where it
930 isn't, or vice versa. In these mentioned conditions, the view of whether trace
931 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
932 the trace buffer state might be corrupted.
934 Work around this in the driver by preventing an inconsistent view of whether the
935 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
936 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
937 two ISB instructions if no ERET is to take place.
941 config ARM64_ERRATUM_1902691
942 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
943 depends on CORESIGHT_TRBE
946 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
948 Affected Cortex-A510 core might cause trace data corruption, when being written
949 into the memory. Effectively TRBE is broken and hence cannot be used to capture
952 Work around this problem in the driver by just preventing TRBE initialization on
953 affected cpus. The firmware must have disabled the access to TRBE for the kernel
954 on such implementations. This will cover the kernel for any firmware that doesn't
959 config ARM64_ERRATUM_2457168
960 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
961 depends on ARM64_AMU_EXTN
964 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
966 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
967 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
968 incorrectly giving a significantly higher output value.
970 Work around this problem by returning 0 when reading the affected counter in
971 key locations that results in disabling all users of this counter. This effect
972 is the same to firmware disabling affected counters.
976 config CAVIUM_ERRATUM_22375
977 bool "Cavium erratum 22375, 24313"
980 Enable workaround for errata 22375 and 24313.
982 This implements two gicv3-its errata workarounds for ThunderX. Both
983 with a small impact affecting only ITS table allocation.
985 erratum 22375: only alloc 8MB table size
986 erratum 24313: ignore memory access type
988 The fixes are in ITS initialization and basically ignore memory access
989 type and table size provided by the TYPER and BASER registers.
993 config CAVIUM_ERRATUM_23144
994 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
998 ITS SYNC command hang for cross node io and collections/cpu mapping.
1002 config CAVIUM_ERRATUM_23154
1003 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1006 The ThunderX GICv3 implementation requires a modified version for
1007 reading the IAR status to ensure data synchronization
1008 (access to icc_iar1_el1 is not sync'ed before and after).
1010 It also suffers from erratum 38545 (also present on Marvell's
1011 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1012 spuriously presented to the CPU interface.
1016 config CAVIUM_ERRATUM_27456
1017 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1020 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1021 instructions may cause the icache to become corrupted if it
1022 contains data for a non-current ASID. The fix is to
1023 invalidate the icache when changing the mm context.
1027 config CAVIUM_ERRATUM_30115
1028 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1031 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1032 1.2, and T83 Pass 1.0, KVM guest execution may disable
1033 interrupts in host. Trapping both GICv3 group-0 and group-1
1034 accesses sidesteps the issue.
1038 config CAVIUM_TX2_ERRATUM_219
1039 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1042 On Cavium ThunderX2, a load, store or prefetch instruction between a
1043 TTBR update and the corresponding context synchronizing operation can
1044 cause a spurious Data Abort to be delivered to any hardware thread in
1047 Work around the issue by avoiding the problematic code sequence and
1048 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1049 trap handler performs the corresponding register access, skips the
1050 instruction and ensures context synchronization by virtue of the
1055 config FUJITSU_ERRATUM_010001
1056 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1059 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1060 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1061 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1062 This fault occurs under a specific hardware condition when a
1063 load/store instruction performs an address translation using:
1064 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1065 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1066 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1067 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1069 The workaround is to ensure these bits are clear in TCR_ELx.
1070 The workaround only affects the Fujitsu-A64FX.
1074 config HISILICON_ERRATUM_161600802
1075 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1078 The HiSilicon Hip07 SoC uses the wrong redistributor base
1079 when issued ITS commands such as VMOVP and VMAPP, and requires
1080 a 128kB offset to be applied to the target address in this commands.
1084 config QCOM_FALKOR_ERRATUM_1003
1085 bool "Falkor E1003: Incorrect translation due to ASID change"
1088 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1089 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1090 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1091 then only for entries in the walk cache, since the leaf translation
1092 is unchanged. Work around the erratum by invalidating the walk cache
1093 entries for the trampoline before entering the kernel proper.
1095 config QCOM_FALKOR_ERRATUM_1009
1096 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1098 select ARM64_WORKAROUND_REPEAT_TLBI
1100 On Falkor v1, the CPU may prematurely complete a DSB following a
1101 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1102 one more time to fix the issue.
1106 config QCOM_QDF2400_ERRATUM_0065
1107 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1110 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1111 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1112 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1116 config QCOM_FALKOR_ERRATUM_E1041
1117 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1120 Falkor CPU may speculatively fetch instructions from an improper
1121 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1122 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1126 config NVIDIA_CARMEL_CNP_ERRATUM
1127 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1130 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1131 invalidate shared TLB entries installed by a different core, as it would
1132 on standard ARM cores.
1136 config SOCIONEXT_SYNQUACER_PREITS
1137 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1140 Socionext Synquacer SoCs implement a separate h/w block to generate
1141 MSI doorbell writes with non-zero values for the device ID.
1145 endmenu # "ARM errata workarounds via the alternatives framework"
1149 default ARM64_4K_PAGES
1151 Page size (translation granule) configuration.
1153 config ARM64_4K_PAGES
1156 This feature enables 4KB pages support.
1158 config ARM64_16K_PAGES
1161 The system will use 16KB pages support. AArch32 emulation
1162 requires applications compiled with 16K (or a multiple of 16K)
1165 config ARM64_64K_PAGES
1168 This feature enables 64KB pages support (4KB by default)
1169 allowing only two levels of page tables and faster TLB
1170 look-up. AArch32 emulation requires applications compiled
1171 with 64K aligned segments.
1176 prompt "Virtual address space size"
1177 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1178 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1179 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1181 Allows choosing one of multiple possible virtual address
1182 space sizes. The level of translation table is determined by
1183 a combination of page size and virtual address space size.
1185 config ARM64_VA_BITS_36
1186 bool "36-bit" if EXPERT
1187 depends on ARM64_16K_PAGES
1189 config ARM64_VA_BITS_39
1191 depends on ARM64_4K_PAGES
1193 config ARM64_VA_BITS_42
1195 depends on ARM64_64K_PAGES
1197 config ARM64_VA_BITS_47
1199 depends on ARM64_16K_PAGES
1201 config ARM64_VA_BITS_48
1204 config ARM64_VA_BITS_52
1206 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1208 Enable 52-bit virtual addressing for userspace when explicitly
1209 requested via a hint to mmap(). The kernel will also use 52-bit
1210 virtual addresses for its own mappings (provided HW support for
1211 this feature is available, otherwise it reverts to 48-bit).
1213 NOTE: Enabling 52-bit virtual addressing in conjunction with
1214 ARMv8.3 Pointer Authentication will result in the PAC being
1215 reduced from 7 bits to 3 bits, which may have a significant
1216 impact on its susceptibility to brute-force attacks.
1218 If unsure, select 48-bit virtual addressing instead.
1222 config ARM64_FORCE_52BIT
1223 bool "Force 52-bit virtual addresses for userspace"
1224 depends on ARM64_VA_BITS_52 && EXPERT
1226 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1227 to maintain compatibility with older software by providing 48-bit VAs
1228 unless a hint is supplied to mmap.
1230 This configuration option disables the 48-bit compatibility logic, and
1231 forces all userspace addresses to be 52-bit on HW that supports it. One
1232 should only enable this configuration option for stress testing userspace
1233 memory management code. If unsure say N here.
1235 config ARM64_VA_BITS
1237 default 36 if ARM64_VA_BITS_36
1238 default 39 if ARM64_VA_BITS_39
1239 default 42 if ARM64_VA_BITS_42
1240 default 47 if ARM64_VA_BITS_47
1241 default 48 if ARM64_VA_BITS_48
1242 default 52 if ARM64_VA_BITS_52
1245 prompt "Physical address space size"
1246 default ARM64_PA_BITS_48
1248 Choose the maximum physical address range that the kernel will
1251 config ARM64_PA_BITS_48
1254 config ARM64_PA_BITS_52
1255 bool "52-bit (ARMv8.2)"
1256 depends on ARM64_64K_PAGES
1257 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1259 Enable support for a 52-bit physical address space, introduced as
1260 part of the ARMv8.2-LPA extension.
1262 With this enabled, the kernel will also continue to work on CPUs that
1263 do not support ARMv8.2-LPA, but with some added memory overhead (and
1264 minor performance overhead).
1268 config ARM64_PA_BITS
1270 default 48 if ARM64_PA_BITS_48
1271 default 52 if ARM64_PA_BITS_52
1275 default CPU_LITTLE_ENDIAN
1277 Select the endianness of data accesses performed by the CPU. Userspace
1278 applications will need to be compiled and linked for the endianness
1279 that is selected here.
1281 config CPU_BIG_ENDIAN
1282 bool "Build big-endian kernel"
1283 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1285 Say Y if you plan on running a kernel with a big-endian userspace.
1287 config CPU_LITTLE_ENDIAN
1288 bool "Build little-endian kernel"
1290 Say Y if you plan on running a kernel with a little-endian userspace.
1291 This is usually the case for distributions targeting arm64.
1296 bool "Multi-core scheduler support"
1298 Multi-core scheduler support improves the CPU scheduler's decision
1299 making when dealing with multi-core CPU chips at a cost of slightly
1300 increased overhead in some places. If unsure say N here.
1302 config SCHED_CLUSTER
1303 bool "Cluster scheduler support"
1305 Cluster scheduler support improves the CPU scheduler's decision
1306 making when dealing with machines that have clusters of CPUs.
1307 Cluster usually means a couple of CPUs which are placed closely
1308 by sharing mid-level caches, last-level cache tags or internal
1312 bool "SMT scheduler support"
1314 Improves the CPU scheduler's decision making when dealing with
1315 MultiThreading at a cost of slightly increased overhead in some
1316 places. If unsure say N here.
1319 int "Maximum number of CPUs (2-4096)"
1324 bool "Support for hot-pluggable CPUs"
1325 select GENERIC_IRQ_MIGRATION
1327 Say Y here to experiment with turning CPUs off and on. CPUs
1328 can be controlled through /sys/devices/system/cpu.
1330 # Common NUMA Features
1332 bool "NUMA Memory Allocation and Scheduler Support"
1333 select GENERIC_ARCH_NUMA
1334 select ACPI_NUMA if ACPI
1336 select HAVE_SETUP_PER_CPU_AREA
1337 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1338 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1339 select USE_PERCPU_NUMA_NODE_ID
1341 Enable NUMA (Non-Uniform Memory Access) support.
1343 The kernel will try to allocate memory used by a CPU on the
1344 local memory of the CPU and add some more
1345 NUMA awareness to the kernel.
1348 int "Maximum NUMA Nodes (as a power of 2)"
1353 Specify the maximum number of NUMA Nodes available on the target
1354 system. Increases memory reserved to accommodate various tables.
1356 source "kernel/Kconfig.hz"
1358 config ARCH_SPARSEMEM_ENABLE
1360 select SPARSEMEM_VMEMMAP_ENABLE
1361 select SPARSEMEM_VMEMMAP
1363 config HW_PERF_EVENTS
1367 # Supported by clang >= 7.0 or GCC >= 12.0.0
1368 config CC_HAVE_SHADOW_CALL_STACK
1369 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1372 bool "Enable paravirtualization code"
1374 This changes the kernel so it can modify itself when it is run
1375 under a hypervisor, potentially improving performance significantly
1376 over full virtualization.
1378 config PARAVIRT_TIME_ACCOUNTING
1379 bool "Paravirtual steal time accounting"
1382 Select this option to enable fine granularity task steal time
1383 accounting. Time spent executing other tasks in parallel with
1384 the current vCPU is discounted from the vCPU power. To account for
1385 that, there can be a small performance impact.
1387 If in doubt, say N here.
1390 depends on PM_SLEEP_SMP
1392 bool "kexec system call"
1394 kexec is a system call that implements the ability to shutdown your
1395 current kernel, and to start another kernel. It is like a reboot
1396 but it is independent of the system firmware. And like a reboot
1397 you can start any kernel with it, not just Linux.
1400 bool "kexec file based system call"
1402 select HAVE_IMA_KEXEC if IMA
1404 This is new version of kexec system call. This system call is
1405 file based and takes file descriptors as system call argument
1406 for kernel and initramfs as opposed to list of segments as
1407 accepted by previous system call.
1410 bool "Verify kernel signature during kexec_file_load() syscall"
1411 depends on KEXEC_FILE
1413 Select this option to verify a signature with loaded kernel
1414 image. If configured, any attempt of loading a image without
1415 valid signature will fail.
1417 In addition to that option, you need to enable signature
1418 verification for the corresponding kernel image type being
1419 loaded in order for this to work.
1421 config KEXEC_IMAGE_VERIFY_SIG
1422 bool "Enable Image signature verification support"
1424 depends on KEXEC_SIG
1425 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1427 Enable Image signature verification support.
1429 comment "Support for PE file signature verification disabled"
1430 depends on KEXEC_SIG
1431 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1434 bool "Build kdump crash kernel"
1436 Generate crash dump after being started by kexec. This should
1437 be normally only set in special crash dump kernels which are
1438 loaded in the main kernel with kexec-tools into a specially
1439 reserved region and then later executed after a crash by
1442 For more details see Documentation/admin-guide/kdump/kdump.rst
1446 depends on HIBERNATION || KEXEC_CORE
1453 bool "Xen guest support on ARM64"
1454 depends on ARM64 && OF
1458 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1460 config ARCH_FORCE_MAX_ORDER
1462 default "14" if ARM64_64K_PAGES
1463 default "12" if ARM64_16K_PAGES
1466 The kernel memory allocator divides physically contiguous memory
1467 blocks into "zones", where each zone is a power of two number of
1468 pages. This option selects the largest power of two that the kernel
1469 keeps in the memory allocator. If you need to allocate very large
1470 blocks of physically contiguous memory, then you may need to
1471 increase this value.
1473 This config option is actually maximum order plus one. For example,
1474 a value of 11 means that the largest free memory block is 2^10 pages.
1476 We make sure that we can allocate upto a HugePage size for each configuration.
1478 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1480 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1481 4M allocations matching the default size used by generic code.
1483 config UNMAP_KERNEL_AT_EL0
1484 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1487 Speculation attacks against some high-performance processors can
1488 be used to bypass MMU permission checks and leak kernel data to
1489 userspace. This can be defended against by unmapping the kernel
1490 when running in userspace, mapping it back in on exception entry
1491 via a trampoline page in the vector table.
1495 config MITIGATE_SPECTRE_BRANCH_HISTORY
1496 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1499 Speculation attacks against some high-performance processors can
1500 make use of branch history to influence future speculation.
1501 When taking an exception from user-space, a sequence of branches
1502 or a firmware call overwrites the branch history.
1504 config RODATA_FULL_DEFAULT_ENABLED
1505 bool "Apply r/o permissions of VM areas also to their linear aliases"
1508 Apply read-only attributes of VM areas to the linear alias of
1509 the backing pages as well. This prevents code or read-only data
1510 from being modified (inadvertently or intentionally) via another
1511 mapping of the same memory page. This additional enhancement can
1512 be turned off at runtime by passing rodata=[off|on] (and turned on
1513 with rodata=full if this option is set to 'n')
1515 This requires the linear region to be mapped down to pages,
1516 which may adversely affect performance in some cases.
1518 config ARM64_SW_TTBR0_PAN
1519 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1521 Enabling this option prevents the kernel from accessing
1522 user-space memory directly by pointing TTBR0_EL1 to a reserved
1523 zeroed area and reserved ASID. The user access routines
1524 restore the valid TTBR0_EL1 temporarily.
1526 config ARM64_TAGGED_ADDR_ABI
1527 bool "Enable the tagged user addresses syscall ABI"
1530 When this option is enabled, user applications can opt in to a
1531 relaxed ABI via prctl() allowing tagged addresses to be passed
1532 to system calls as pointer arguments. For details, see
1533 Documentation/arm64/tagged-address-abi.rst.
1536 bool "Kernel support for 32-bit EL0"
1537 depends on ARM64_4K_PAGES || EXPERT
1539 select OLD_SIGSUSPEND3
1540 select COMPAT_OLD_SIGACTION
1542 This option enables support for a 32-bit EL0 running under a 64-bit
1543 kernel at EL1. AArch32-specific components such as system calls,
1544 the user helper functions, VFP support and the ptrace interface are
1545 handled appropriately by the kernel.
1547 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1548 that you will only be able to execute AArch32 binaries that were compiled
1549 with page size aligned segments.
1551 If you want to execute 32-bit userspace applications, say Y.
1555 config KUSER_HELPERS
1556 bool "Enable kuser helpers page for 32-bit applications"
1559 Warning: disabling this option may break 32-bit user programs.
1561 Provide kuser helpers to compat tasks. The kernel provides
1562 helper code to userspace in read only form at a fixed location
1563 to allow userspace to be independent of the CPU type fitted to
1564 the system. This permits binaries to be run on ARMv4 through
1565 to ARMv8 without modification.
1567 See Documentation/arm/kernel_user_helpers.rst for details.
1569 However, the fixed address nature of these helpers can be used
1570 by ROP (return orientated programming) authors when creating
1573 If all of the binaries and libraries which run on your platform
1574 are built specifically for your platform, and make no use of
1575 these helpers, then you can turn this option off to hinder
1576 such exploits. However, in that case, if a binary or library
1577 relying on those helpers is run, it will not function correctly.
1579 Say N here only if you are absolutely certain that you do not
1580 need these helpers; otherwise, the safe option is to say Y.
1583 bool "Enable vDSO for 32-bit applications"
1584 depends on !CPU_BIG_ENDIAN
1585 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1586 select GENERIC_COMPAT_VDSO
1589 Place in the process address space of 32-bit applications an
1590 ELF shared object providing fast implementations of gettimeofday
1593 You must have a 32-bit build of glibc 2.22 or later for programs
1594 to seamlessly take advantage of this.
1596 config THUMB2_COMPAT_VDSO
1597 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1598 depends on COMPAT_VDSO
1601 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1602 otherwise with '-marm'.
1604 config COMPAT_ALIGNMENT_FIXUPS
1605 bool "Fix up misaligned multi-word loads and stores in user space"
1607 menuconfig ARMV8_DEPRECATED
1608 bool "Emulate deprecated/obsolete ARMv8 instructions"
1611 Legacy software support may require certain instructions
1612 that have been deprecated or obsoleted in the architecture.
1614 Enable this config to enable selective emulation of these
1621 config SWP_EMULATION
1622 bool "Emulate SWP/SWPB instructions"
1624 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1625 they are always undefined. Say Y here to enable software
1626 emulation of these instructions for userspace using LDXR/STXR.
1627 This feature can be controlled at runtime with the abi.swp
1628 sysctl which is disabled by default.
1630 In some older versions of glibc [<=2.8] SWP is used during futex
1631 trylock() operations with the assumption that the code will not
1632 be preempted. This invalid assumption may be more likely to fail
1633 with SWP emulation enabled, leading to deadlock of the user
1636 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1637 on an external transaction monitoring block called a global
1638 monitor to maintain update atomicity. If your system does not
1639 implement a global monitor, this option can cause programs that
1640 perform SWP operations to uncached memory to deadlock.
1644 config CP15_BARRIER_EMULATION
1645 bool "Emulate CP15 Barrier instructions"
1647 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1648 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1649 strongly recommended to use the ISB, DSB, and DMB
1650 instructions instead.
1652 Say Y here to enable software emulation of these
1653 instructions for AArch32 userspace code. When this option is
1654 enabled, CP15 barrier usage is traced which can help
1655 identify software that needs updating. This feature can be
1656 controlled at runtime with the abi.cp15_barrier sysctl.
1660 config SETEND_EMULATION
1661 bool "Emulate SETEND instruction"
1663 The SETEND instruction alters the data-endianness of the
1664 AArch32 EL0, and is deprecated in ARMv8.
1666 Say Y here to enable software emulation of the instruction
1667 for AArch32 userspace code. This feature can be controlled
1668 at runtime with the abi.setend sysctl.
1670 Note: All the cpus on the system must have mixed endian support at EL0
1671 for this feature to be enabled. If a new CPU - which doesn't support mixed
1672 endian - is hotplugged in after this feature has been enabled, there could
1673 be unexpected results in the applications.
1676 endif # ARMV8_DEPRECATED
1680 menu "ARMv8.1 architectural features"
1682 config ARM64_HW_AFDBM
1683 bool "Support for hardware updates of the Access and Dirty page flags"
1686 The ARMv8.1 architecture extensions introduce support for
1687 hardware updates of the access and dirty information in page
1688 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1689 capable processors, accesses to pages with PTE_AF cleared will
1690 set this bit instead of raising an access flag fault.
1691 Similarly, writes to read-only pages with the DBM bit set will
1692 clear the read-only bit (AP[2]) instead of raising a
1695 Kernels built with this configuration option enabled continue
1696 to work on pre-ARMv8.1 hardware and the performance impact is
1697 minimal. If unsure, say Y.
1700 bool "Enable support for Privileged Access Never (PAN)"
1703 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1704 prevents the kernel or hypervisor from accessing user-space (EL0)
1707 Choosing this option will cause any unprotected (not using
1708 copy_to_user et al) memory access to fail with a permission fault.
1710 The feature is detected at runtime, and will remain as a 'nop'
1711 instruction if the cpu does not implement the feature.
1714 def_bool $(as-instr,.arch_extension rcpc)
1716 config AS_HAS_LSE_ATOMICS
1717 def_bool $(as-instr,.arch_extension lse)
1719 config ARM64_LSE_ATOMICS
1721 default ARM64_USE_LSE_ATOMICS
1722 depends on AS_HAS_LSE_ATOMICS
1724 config ARM64_USE_LSE_ATOMICS
1725 bool "Atomic instructions"
1728 As part of the Large System Extensions, ARMv8.1 introduces new
1729 atomic instructions that are designed specifically to scale in
1732 Say Y here to make use of these instructions for the in-kernel
1733 atomic routines. This incurs a small overhead on CPUs that do
1734 not support these instructions and requires the kernel to be
1735 built with binutils >= 2.25 in order for the new instructions
1738 endmenu # "ARMv8.1 architectural features"
1740 menu "ARMv8.2 architectural features"
1742 config AS_HAS_ARMV8_2
1743 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1746 def_bool $(as-instr,.arch armv8.2-a+sha3)
1749 bool "Enable support for persistent memory"
1750 select ARCH_HAS_PMEM_API
1751 select ARCH_HAS_UACCESS_FLUSHCACHE
1753 Say Y to enable support for the persistent memory API based on the
1754 ARMv8.2 DCPoP feature.
1756 The feature is detected at runtime, and the kernel will use DC CVAC
1757 operations if DC CVAP is not supported (following the behaviour of
1758 DC CVAP itself if the system does not define a point of persistence).
1760 config ARM64_RAS_EXTN
1761 bool "Enable support for RAS CPU Extensions"
1764 CPUs that support the Reliability, Availability and Serviceability
1765 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1766 errors, classify them and report them to software.
1768 On CPUs with these extensions system software can use additional
1769 barriers to determine if faults are pending and read the
1770 classification from a new set of registers.
1772 Selecting this feature will allow the kernel to use these barriers
1773 and access the new registers if the system supports the extension.
1774 Platform RAS features may additionally depend on firmware support.
1777 bool "Enable support for Common Not Private (CNP) translations"
1779 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1781 Common Not Private (CNP) allows translation table entries to
1782 be shared between different PEs in the same inner shareable
1783 domain, so the hardware can use this fact to optimise the
1784 caching of such entries in the TLB.
1786 Selecting this option allows the CNP feature to be detected
1787 at runtime, and does not affect PEs that do not implement
1790 endmenu # "ARMv8.2 architectural features"
1792 menu "ARMv8.3 architectural features"
1794 config ARM64_PTR_AUTH
1795 bool "Enable support for pointer authentication"
1798 Pointer authentication (part of the ARMv8.3 Extensions) provides
1799 instructions for signing and authenticating pointers against secret
1800 keys, which can be used to mitigate Return Oriented Programming (ROP)
1803 This option enables these instructions at EL0 (i.e. for userspace).
1804 Choosing this option will cause the kernel to initialise secret keys
1805 for each process at exec() time, with these keys being
1806 context-switched along with the process.
1808 The feature is detected at runtime. If the feature is not present in
1809 hardware it will not be advertised to userspace/KVM guest nor will it
1812 If the feature is present on the boot CPU but not on a late CPU, then
1813 the late CPU will be parked. Also, if the boot CPU does not have
1814 address auth and the late CPU has then the late CPU will still boot
1815 but with the feature disabled. On such a system, this option should
1818 config ARM64_PTR_AUTH_KERNEL
1819 bool "Use pointer authentication for kernel"
1821 depends on ARM64_PTR_AUTH
1822 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC
1823 # Modern compilers insert a .note.gnu.property section note for PAC
1824 # which is only understood by binutils starting with version 2.33.1.
1825 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1826 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1827 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1829 If the compiler supports the -mbranch-protection or
1830 -msign-return-address flag (e.g. GCC 7 or later), then this option
1831 will cause the kernel itself to be compiled with return address
1832 protection. In this case, and if the target hardware is known to
1833 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1834 disabled with minimal loss of protection.
1836 This feature works with FUNCTION_GRAPH_TRACER option only if
1837 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1839 config CC_HAS_BRANCH_PROT_PAC_RET
1840 # GCC 9 or later, clang 8 or later
1841 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1843 config CC_HAS_SIGN_RETURN_ADDRESS
1845 def_bool $(cc-option,-msign-return-address=all)
1848 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1850 config AS_HAS_CFI_NEGATE_RA_STATE
1851 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1853 endmenu # "ARMv8.3 architectural features"
1855 menu "ARMv8.4 architectural features"
1857 config ARM64_AMU_EXTN
1858 bool "Enable support for the Activity Monitors Unit CPU extension"
1861 The activity monitors extension is an optional extension introduced
1862 by the ARMv8.4 CPU architecture. This enables support for version 1
1863 of the activity monitors architecture, AMUv1.
1865 To enable the use of this extension on CPUs that implement it, say Y.
1867 Note that for architectural reasons, firmware _must_ implement AMU
1868 support when running on CPUs that present the activity monitors
1869 extension. The required support is present in:
1870 * Version 1.5 and later of the ARM Trusted Firmware
1872 For kernels that have this configuration enabled but boot with broken
1873 firmware, you may need to say N here until the firmware is fixed.
1874 Otherwise you may experience firmware panics or lockups when
1875 accessing the counter registers. Even if you are not observing these
1876 symptoms, the values returned by the register reads might not
1877 correctly reflect reality. Most commonly, the value read will be 0,
1878 indicating that the counter is not enabled.
1880 config AS_HAS_ARMV8_4
1881 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1883 config ARM64_TLB_RANGE
1884 bool "Enable support for tlbi range feature"
1886 depends on AS_HAS_ARMV8_4
1888 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1889 range of input addresses.
1891 The feature introduces new assembly instructions, and they were
1892 support when binutils >= 2.30.
1894 endmenu # "ARMv8.4 architectural features"
1896 menu "ARMv8.5 architectural features"
1898 config AS_HAS_ARMV8_5
1899 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1902 bool "Branch Target Identification support"
1905 Branch Target Identification (part of the ARMv8.5 Extensions)
1906 provides a mechanism to limit the set of locations to which computed
1907 branch instructions such as BR or BLR can jump.
1909 To make use of BTI on CPUs that support it, say Y.
1911 BTI is intended to provide complementary protection to other control
1912 flow integrity protection mechanisms, such as the Pointer
1913 authentication mechanism provided as part of the ARMv8.3 Extensions.
1914 For this reason, it does not make sense to enable this option without
1915 also enabling support for pointer authentication. Thus, when
1916 enabling this option you should also select ARM64_PTR_AUTH=y.
1918 Userspace binaries must also be specifically compiled to make use of
1919 this mechanism. If you say N here or the hardware does not support
1920 BTI, such binaries can still run, but you get no additional
1921 enforcement of branch destinations.
1923 config ARM64_BTI_KERNEL
1924 bool "Use Branch Target Identification for kernel"
1926 depends on ARM64_BTI
1927 depends on ARM64_PTR_AUTH_KERNEL
1928 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1929 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1930 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1931 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1932 depends on !CC_IS_GCC
1933 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1934 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1935 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1937 Build the kernel with Branch Target Identification annotations
1938 and enable enforcement of this for kernel code. When this option
1939 is enabled and the system supports BTI all kernel code including
1940 modular code must have BTI enabled.
1942 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1943 # GCC 9 or later, clang 8 or later
1944 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1947 bool "Enable support for E0PD"
1950 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1951 that EL0 accesses made via TTBR1 always fault in constant time,
1952 providing similar benefits to KASLR as those provided by KPTI, but
1953 with lower overhead and without disrupting legitimate access to
1954 kernel memory such as SPE.
1956 This option enables E0PD for TTBR1 where available.
1958 config ARM64_AS_HAS_MTE
1959 # Initial support for MTE went in binutils 2.32.0, checked with
1960 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1961 # as a late addition to the final architecture spec (LDGM/STGM)
1962 # is only supported in the newer 2.32.x and 2.33 binutils
1963 # versions, hence the extra "stgm" instruction check below.
1964 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1967 bool "Memory Tagging Extension support"
1969 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
1970 depends on AS_HAS_ARMV8_5
1971 depends on AS_HAS_LSE_ATOMICS
1972 # Required for tag checking in the uaccess routines
1973 depends on ARM64_PAN
1974 select ARCH_HAS_SUBPAGE_FAULTS
1975 select ARCH_USES_HIGH_VMA_FLAGS
1976 select ARCH_USES_PG_ARCH_X
1978 Memory Tagging (part of the ARMv8.5 Extensions) provides
1979 architectural support for run-time, always-on detection of
1980 various classes of memory error to aid with software debugging
1981 to eliminate vulnerabilities arising from memory-unsafe
1984 This option enables the support for the Memory Tagging
1985 Extension at EL0 (i.e. for userspace).
1987 Selecting this option allows the feature to be detected at
1988 runtime. Any secondary CPU not implementing this feature will
1989 not be allowed a late bring-up.
1991 Userspace binaries that want to use this feature must
1992 explicitly opt in. The mechanism for the userspace is
1995 Documentation/arm64/memory-tagging-extension.rst.
1997 endmenu # "ARMv8.5 architectural features"
1999 menu "ARMv8.7 architectural features"
2002 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2004 depends on ARM64_PAN
2006 Enhanced Privileged Access Never (EPAN) allows Privileged
2007 Access Never to be used with Execute-only mappings.
2009 The feature is detected at runtime, and will remain disabled
2010 if the cpu does not implement the feature.
2011 endmenu # "ARMv8.7 architectural features"
2014 bool "ARM Scalable Vector Extension support"
2017 The Scalable Vector Extension (SVE) is an extension to the AArch64
2018 execution state which complements and extends the SIMD functionality
2019 of the base architecture to support much larger vectors and to enable
2020 additional vectorisation opportunities.
2022 To enable use of this extension on CPUs that implement it, say Y.
2024 On CPUs that support the SVE2 extensions, this option will enable
2027 Note that for architectural reasons, firmware _must_ implement SVE
2028 support when running on SVE capable hardware. The required support
2031 * version 1.5 and later of the ARM Trusted Firmware
2032 * the AArch64 boot wrapper since commit 5e1261e08abf
2033 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2035 For other firmware implementations, consult the firmware documentation
2038 If you need the kernel to boot on SVE-capable hardware with broken
2039 firmware, you may need to say N here until you get your firmware
2040 fixed. Otherwise, you may experience firmware panics or lockups when
2041 booting the kernel. If unsure and you are not observing these
2042 symptoms, you should assume that it is safe to say Y.
2045 bool "ARM Scalable Matrix Extension support"
2047 depends on ARM64_SVE
2049 The Scalable Matrix Extension (SME) is an extension to the AArch64
2050 execution state which utilises a substantial subset of the SVE
2051 instruction set, together with the addition of new architectural
2052 register state capable of holding two dimensional matrix tiles to
2053 enable various matrix operations.
2055 config ARM64_MODULE_PLTS
2056 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2058 select HAVE_MOD_ARCH_SPECIFIC
2060 Allocate PLTs when loading modules so that jumps and calls whose
2061 targets are too far away for their relative offsets to be encoded
2062 in the instructions themselves can be bounced via veneers in the
2063 module's PLT. This allows modules to be allocated in the generic
2064 vmalloc area after the dedicated module memory area has been
2067 When running with address space randomization (KASLR), the module
2068 region itself may be too far away for ordinary relative jumps and
2069 calls, and so in that case, module PLTs are required and cannot be
2072 Specific errata workaround(s) might also force module PLTs to be
2073 enabled (ARM64_ERRATUM_843419).
2075 config ARM64_PSEUDO_NMI
2076 bool "Support for NMI-like interrupts"
2079 Adds support for mimicking Non-Maskable Interrupts through the use of
2080 GIC interrupt priority. This support requires version 3 or later of
2083 This high priority configuration for interrupts needs to be
2084 explicitly enabled by setting the kernel parameter
2085 "irqchip.gicv3_pseudo_nmi" to 1.
2090 config ARM64_DEBUG_PRIORITY_MASKING
2091 bool "Debug interrupt priority masking"
2093 This adds runtime checks to functions enabling/disabling
2094 interrupts when using priority masking. The additional checks verify
2095 the validity of ICC_PMR_EL1 when calling concerned functions.
2098 endif # ARM64_PSEUDO_NMI
2101 bool "Build a relocatable kernel image" if EXPERT
2102 select ARCH_HAS_RELR
2105 This builds the kernel as a Position Independent Executable (PIE),
2106 which retains all relocation metadata required to relocate the
2107 kernel binary at runtime to a different virtual address than the
2108 address it was linked at.
2109 Since AArch64 uses the RELA relocation format, this requires a
2110 relocation pass at runtime even if the kernel is loaded at the
2111 same address it was linked at.
2113 config RANDOMIZE_BASE
2114 bool "Randomize the address of the kernel image"
2115 select ARM64_MODULE_PLTS if MODULES
2118 Randomizes the virtual address at which the kernel image is
2119 loaded, as a security feature that deters exploit attempts
2120 relying on knowledge of the location of kernel internals.
2122 It is the bootloader's job to provide entropy, by passing a
2123 random u64 value in /chosen/kaslr-seed at kernel entry.
2125 When booting via the UEFI stub, it will invoke the firmware's
2126 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2127 to the kernel proper. In addition, it will randomise the physical
2128 location of the kernel Image as well.
2132 config RANDOMIZE_MODULE_REGION_FULL
2133 bool "Randomize the module region over a 2 GB range"
2134 depends on RANDOMIZE_BASE
2137 Randomizes the location of the module region inside a 2 GB window
2138 covering the core kernel. This way, it is less likely for modules
2139 to leak information about the location of core kernel data structures
2140 but it does imply that function calls between modules and the core
2141 kernel will need to be resolved via veneers in the module PLT.
2143 When this option is not set, the module region will be randomized over
2144 a limited range that contains the [_stext, _etext] interval of the
2145 core kernel, so branch relocations are almost always in range unless
2146 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2147 particular case of region exhaustion, modules might be able to fall
2148 back to a larger 2GB area.
2150 config CC_HAVE_STACKPROTECTOR_SYSREG
2151 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2153 config STACKPROTECTOR_PER_TASK
2155 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2157 config UNWIND_PATCH_PAC_INTO_SCS
2158 bool "Enable shadow call stack dynamically using code patching"
2159 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2160 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2161 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2162 depends on SHADOW_CALL_STACK
2163 select UNWIND_TABLES
2166 endmenu # "Kernel Features"
2170 config ARM64_ACPI_PARKING_PROTOCOL
2171 bool "Enable support for the ARM64 ACPI parking protocol"
2174 Enable support for the ARM64 ACPI parking protocol. If disabled
2175 the kernel will not allow booting through the ARM64 ACPI parking
2176 protocol even if the corresponding data is present in the ACPI
2180 string "Default kernel command string"
2183 Provide a set of default command-line options at build time by
2184 entering them here. As a minimum, you should specify the the
2185 root device (e.g. root=/dev/nfs).
2188 prompt "Kernel command line type" if CMDLINE != ""
2189 default CMDLINE_FROM_BOOTLOADER
2191 Choose how the kernel will handle the provided default kernel
2192 command line string.
2194 config CMDLINE_FROM_BOOTLOADER
2195 bool "Use bootloader kernel arguments if available"
2197 Uses the command-line options passed by the boot loader. If
2198 the boot loader doesn't provide any, the default kernel command
2199 string provided in CMDLINE will be used.
2201 config CMDLINE_FORCE
2202 bool "Always use the default kernel command string"
2204 Always use the default kernel command string, even if the boot
2205 loader passes other arguments to the kernel.
2206 This is useful if you cannot or don't want to change the
2207 command-line options your boot loader passes to the kernel.
2215 bool "UEFI runtime support"
2216 depends on OF && !CPU_BIG_ENDIAN
2217 depends on KERNEL_MODE_NEON
2218 select ARCH_SUPPORTS_ACPI
2221 select EFI_PARAMS_FROM_FDT
2222 select EFI_RUNTIME_WRAPPERS
2224 select EFI_GENERIC_STUB
2225 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2228 This option provides support for runtime services provided
2229 by UEFI firmware (such as non-volatile variables, realtime
2230 clock, and platform reset). A UEFI stub is also provided to
2231 allow the kernel to be booted as an EFI application. This
2232 is only useful on systems that have UEFI firmware.
2235 bool "Enable support for SMBIOS (DMI) tables"
2239 This enables SMBIOS/DMI feature for systems.
2241 This option is only useful on systems that have UEFI firmware.
2242 However, even with this option, the resultant kernel should
2243 continue to boot on existing non-UEFI platforms.
2245 endmenu # "Boot options"
2247 menu "Power management options"
2249 source "kernel/power/Kconfig"
2251 config ARCH_HIBERNATION_POSSIBLE
2255 config ARCH_HIBERNATION_HEADER
2257 depends on HIBERNATION
2259 config ARCH_SUSPEND_POSSIBLE
2262 endmenu # "Power management options"
2264 menu "CPU Power Management"
2266 source "drivers/cpuidle/Kconfig"
2268 source "drivers/cpufreq/Kconfig"
2270 endmenu # "CPU Power Management"
2272 source "drivers/acpi/Kconfig"
2274 source "arch/arm64/kvm/Kconfig"