1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_CCA_REQUIRED if ACPI
5 select ACPI_GENERIC_GSI if ACPI
6 select ACPI_GTDT if ACPI
7 select ACPI_IORT if ACPI
8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
9 select ACPI_MCFG if (ACPI && PCI)
10 select ACPI_SPCR_TABLE if ACPI
11 select ACPI_PPTT if ACPI
12 select ARCH_CLOCKSOURCE_DATA
13 select ARCH_HAS_DEBUG_VIRTUAL
14 select ARCH_HAS_DEVMEM_IS_ALLOWED
15 select ARCH_HAS_DMA_COHERENT_TO_PFN
16 select ARCH_HAS_DMA_PREP_COHERENT
17 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
18 select ARCH_HAS_ELF_RANDOMIZE
19 select ARCH_HAS_FAST_MULTIPLIER
20 select ARCH_HAS_FORTIFY_SOURCE
21 select ARCH_HAS_GCOV_PROFILE_ALL
22 select ARCH_HAS_GIGANTIC_PAGE
24 select ARCH_HAS_KEEPINITRD
25 select ARCH_HAS_MEMBARRIER_SYNC_CORE
26 select ARCH_HAS_PTE_DEVMAP
27 select ARCH_HAS_PTE_SPECIAL
28 select ARCH_HAS_SETUP_DMA_OPS
29 select ARCH_HAS_SET_DIRECT_MAP
30 select ARCH_HAS_SET_MEMORY
31 select ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_HAS_STRICT_MODULE_RWX
33 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
34 select ARCH_HAS_SYNC_DMA_FOR_CPU
35 select ARCH_HAS_SYSCALL_WRAPPER
36 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
37 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
38 select ARCH_HAVE_NMI_SAFE_CMPXCHG
39 select ARCH_INLINE_READ_LOCK if !PREEMPT
40 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
41 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
42 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
43 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
44 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
45 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
46 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
47 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
48 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
49 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
50 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
51 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
52 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
53 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
54 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
55 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
56 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
57 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
58 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
59 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
60 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
61 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
62 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
63 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
64 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
65 select ARCH_KEEP_MEMBLOCK
66 select ARCH_USE_CMPXCHG_LOCKREF
67 select ARCH_USE_QUEUED_RWLOCKS
68 select ARCH_USE_QUEUED_SPINLOCKS
69 select ARCH_SUPPORTS_MEMORY_FAILURE
70 select ARCH_SUPPORTS_ATOMIC_RMW
71 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
72 select ARCH_SUPPORTS_NUMA_BALANCING
73 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
74 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
75 select ARCH_WANT_FRAME_POINTERS
76 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
77 select ARCH_HAS_UBSAN_SANITIZE_ALL
81 select AUDIT_ARCH_COMPAT_GENERIC
82 select ARM_GIC_V2M if PCI
84 select ARM_GIC_V3_ITS if PCI
86 select BUILDTIME_EXTABLE_SORT
87 select CLONE_BACKWARDS
89 select CPU_PM if (SUSPEND || CPU_IDLE)
91 select DCACHE_WORD_ACCESS
92 select DMA_DIRECT_REMAP
95 select GENERIC_ALLOCATOR
96 select GENERIC_ARCH_TOPOLOGY
97 select GENERIC_CLOCKEVENTS
98 select GENERIC_CLOCKEVENTS_BROADCAST
99 select GENERIC_CPU_AUTOPROBE
100 select GENERIC_CPU_VULNERABILITIES
101 select GENERIC_EARLY_IOREMAP
102 select GENERIC_IDLE_POLL_SETUP
103 select GENERIC_IRQ_MULTI_HANDLER
104 select GENERIC_IRQ_PROBE
105 select GENERIC_IRQ_SHOW
106 select GENERIC_IRQ_SHOW_LEVEL
107 select GENERIC_PCI_IOMAP
108 select GENERIC_SCHED_CLOCK
109 select GENERIC_SMP_IDLE_THREAD
110 select GENERIC_STRNCPY_FROM_USER
111 select GENERIC_STRNLEN_USER
112 select GENERIC_TIME_VSYSCALL
113 select GENERIC_GETTIMEOFDAY
114 select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
115 select HANDLE_DOMAIN_IRQ
116 select HARDIRQS_SW_RESEND
118 select HAVE_ACPI_APEI if (ACPI && EFI)
119 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
120 select HAVE_ARCH_AUDITSYSCALL
121 select HAVE_ARCH_BITREVERSE
122 select HAVE_ARCH_HUGE_VMAP
123 select HAVE_ARCH_JUMP_LABEL
124 select HAVE_ARCH_JUMP_LABEL_RELATIVE
125 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
126 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
127 select HAVE_ARCH_KGDB
128 select HAVE_ARCH_MMAP_RND_BITS
129 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
130 select HAVE_ARCH_PREL32_RELOCATIONS
131 select HAVE_ARCH_SECCOMP_FILTER
132 select HAVE_ARCH_STACKLEAK
133 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
134 select HAVE_ARCH_TRACEHOOK
135 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
136 select HAVE_ARCH_VMAP_STACK
137 select HAVE_ARM_SMCCC
138 select HAVE_ASM_MODVERSIONS
140 select HAVE_C_RECORDMCOUNT
141 select HAVE_CMPXCHG_DOUBLE
142 select HAVE_CMPXCHG_LOCAL
143 select HAVE_CONTEXT_TRACKING
144 select HAVE_DEBUG_BUGVERBOSE
145 select HAVE_DEBUG_KMEMLEAK
146 select HAVE_DMA_CONTIGUOUS
147 select HAVE_DYNAMIC_FTRACE
148 select HAVE_EFFICIENT_UNALIGNED_ACCESS
150 select HAVE_FTRACE_MCOUNT_RECORD
151 select HAVE_FUNCTION_TRACER
152 select HAVE_FUNCTION_ERROR_INJECTION
153 select HAVE_FUNCTION_GRAPH_TRACER
154 select HAVE_GCC_PLUGINS
155 select HAVE_HW_BREAKPOINT if PERF_EVENTS
156 select HAVE_IRQ_TIME_ACCOUNTING
157 select HAVE_MEMBLOCK_NODE_MAP if NUMA
159 select HAVE_PATA_PLATFORM
160 select HAVE_PERF_EVENTS
161 select HAVE_PERF_REGS
162 select HAVE_PERF_USER_STACK_DUMP
163 select HAVE_REGS_AND_STACK_ACCESS_API
164 select HAVE_FUNCTION_ARG_ACCESS_API
165 select HAVE_RCU_TABLE_FREE
167 select HAVE_STACKPROTECTOR
168 select HAVE_SYSCALL_TRACEPOINTS
170 select HAVE_KRETPROBES
171 select HAVE_GENERIC_VDSO
172 select IOMMU_DMA if IOMMU_SUPPORT
174 select IRQ_FORCED_THREADING
175 select MODULES_USE_ELF_RELA
176 select NEED_DMA_MAP_STATE
177 select NEED_SG_DMA_LENGTH
179 select OF_EARLY_FLATTREE
180 select PCI_DOMAINS_GENERIC if PCI
181 select PCI_ECAM if (ACPI && PCI)
182 select PCI_SYSCALL if PCI
188 select SYSCTL_EXCEPTION_TRACE
189 select THREAD_INFO_IN_TASK
191 ARM 64-bit (AArch64) Linux support.
199 config ARM64_PAGE_SHIFT
201 default 16 if ARM64_64K_PAGES
202 default 14 if ARM64_16K_PAGES
205 config ARM64_CONT_SHIFT
207 default 5 if ARM64_64K_PAGES
208 default 7 if ARM64_16K_PAGES
211 config ARCH_MMAP_RND_BITS_MIN
212 default 14 if ARM64_64K_PAGES
213 default 16 if ARM64_16K_PAGES
216 # max bits determined by the following formula:
217 # VA_BITS - PAGE_SHIFT - 3
218 config ARCH_MMAP_RND_BITS_MAX
219 default 19 if ARM64_VA_BITS=36
220 default 24 if ARM64_VA_BITS=39
221 default 27 if ARM64_VA_BITS=42
222 default 30 if ARM64_VA_BITS=47
223 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
224 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
225 default 33 if ARM64_VA_BITS=48
226 default 14 if ARM64_64K_PAGES
227 default 16 if ARM64_16K_PAGES
230 config ARCH_MMAP_RND_COMPAT_BITS_MIN
231 default 7 if ARM64_64K_PAGES
232 default 9 if ARM64_16K_PAGES
235 config ARCH_MMAP_RND_COMPAT_BITS_MAX
241 config STACKTRACE_SUPPORT
244 config ILLEGAL_POINTER_VALUE
246 default 0xdead000000000000
248 config LOCKDEP_SUPPORT
251 config TRACE_IRQFLAGS_SUPPORT
258 config GENERIC_BUG_RELATIVE_POINTERS
260 depends on GENERIC_BUG
262 config GENERIC_HWEIGHT
268 config GENERIC_CALIBRATE_DELAY
272 bool "Support DMA32 zone" if EXPERT
275 config ARCH_ENABLE_MEMORY_HOTPLUG
281 config KERNEL_MODE_NEON
284 config FIX_EARLYCON_MEM
287 config PGTABLE_LEVELS
289 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
290 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
291 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
292 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
293 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
294 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
296 config ARCH_SUPPORTS_UPROBES
299 config ARCH_PROC_KCORE_TEXT
302 config KASAN_SHADOW_OFFSET
305 default 0xdfffa00000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
306 default 0xdfffd00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
307 default 0xdffffe8000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
308 default 0xdfffffd000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
309 default 0xdffffffa00000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
310 default 0xefff900000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
311 default 0xefffc80000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
312 default 0xeffffe4000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
313 default 0xefffffc800000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
314 default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
315 default 0xffffffffffffffff
317 source "arch/arm64/Kconfig.platforms"
319 menu "Kernel Features"
321 menu "ARM errata workarounds via the alternatives framework"
323 config ARM64_WORKAROUND_CLEAN_CACHE
326 config ARM64_ERRATUM_826319
327 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
329 select ARM64_WORKAROUND_CLEAN_CACHE
331 This option adds an alternative code sequence to work around ARM
332 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
333 AXI master interface and an L2 cache.
335 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
336 and is unable to accept a certain write via this interface, it will
337 not progress on read data presented on the read data channel and the
340 The workaround promotes data cache clean instructions to
341 data cache clean-and-invalidate.
342 Please note that this does not necessarily enable the workaround,
343 as it depends on the alternative framework, which will only patch
344 the kernel if an affected CPU is detected.
348 config ARM64_ERRATUM_827319
349 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
351 select ARM64_WORKAROUND_CLEAN_CACHE
353 This option adds an alternative code sequence to work around ARM
354 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
355 master interface and an L2 cache.
357 Under certain conditions this erratum can cause a clean line eviction
358 to occur at the same time as another transaction to the same address
359 on the AMBA 5 CHI interface, which can cause data corruption if the
360 interconnect reorders the two transactions.
362 The workaround promotes data cache clean instructions to
363 data cache clean-and-invalidate.
364 Please note that this does not necessarily enable the workaround,
365 as it depends on the alternative framework, which will only patch
366 the kernel if an affected CPU is detected.
370 config ARM64_ERRATUM_824069
371 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
373 select ARM64_WORKAROUND_CLEAN_CACHE
375 This option adds an alternative code sequence to work around ARM
376 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
377 to a coherent interconnect.
379 If a Cortex-A53 processor is executing a store or prefetch for
380 write instruction at the same time as a processor in another
381 cluster is executing a cache maintenance operation to the same
382 address, then this erratum might cause a clean cache line to be
383 incorrectly marked as dirty.
385 The workaround promotes data cache clean instructions to
386 data cache clean-and-invalidate.
387 Please note that this option does not necessarily enable the
388 workaround, as it depends on the alternative framework, which will
389 only patch the kernel if an affected CPU is detected.
393 config ARM64_ERRATUM_819472
394 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
396 select ARM64_WORKAROUND_CLEAN_CACHE
398 This option adds an alternative code sequence to work around ARM
399 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
400 present when it is connected to a coherent interconnect.
402 If the processor is executing a load and store exclusive sequence at
403 the same time as a processor in another cluster is executing a cache
404 maintenance operation to the same address, then this erratum might
405 cause data corruption.
407 The workaround promotes data cache clean instructions to
408 data cache clean-and-invalidate.
409 Please note that this does not necessarily enable the workaround,
410 as it depends on the alternative framework, which will only patch
411 the kernel if an affected CPU is detected.
415 config ARM64_ERRATUM_832075
416 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
419 This option adds an alternative code sequence to work around ARM
420 erratum 832075 on Cortex-A57 parts up to r1p2.
422 Affected Cortex-A57 parts might deadlock when exclusive load/store
423 instructions to Write-Back memory are mixed with Device loads.
425 The workaround is to promote device loads to use Load-Acquire
427 Please note that this does not necessarily enable the workaround,
428 as it depends on the alternative framework, which will only patch
429 the kernel if an affected CPU is detected.
433 config ARM64_ERRATUM_834220
434 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
438 This option adds an alternative code sequence to work around ARM
439 erratum 834220 on Cortex-A57 parts up to r1p2.
441 Affected Cortex-A57 parts might report a Stage 2 translation
442 fault as the result of a Stage 1 fault for load crossing a
443 page boundary when there is a permission or device memory
444 alignment fault at Stage 1 and a translation fault at Stage 2.
446 The workaround is to verify that the Stage 1 translation
447 doesn't generate a fault before handling the Stage 2 fault.
448 Please note that this does not necessarily enable the workaround,
449 as it depends on the alternative framework, which will only patch
450 the kernel if an affected CPU is detected.
454 config ARM64_ERRATUM_845719
455 bool "Cortex-A53: 845719: a load might read incorrect data"
459 This option adds an alternative code sequence to work around ARM
460 erratum 845719 on Cortex-A53 parts up to r0p4.
462 When running a compat (AArch32) userspace on an affected Cortex-A53
463 part, a load at EL0 from a virtual address that matches the bottom 32
464 bits of the virtual address used by a recent load at (AArch64) EL1
465 might return incorrect data.
467 The workaround is to write the contextidr_el1 register on exception
468 return to a 32-bit task.
469 Please note that this does not necessarily enable the workaround,
470 as it depends on the alternative framework, which will only patch
471 the kernel if an affected CPU is detected.
475 config ARM64_ERRATUM_843419
476 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
478 select ARM64_MODULE_PLTS if MODULES
480 This option links the kernel with '--fix-cortex-a53-843419' and
481 enables PLT support to replace certain ADRP instructions, which can
482 cause subsequent memory accesses to use an incorrect address on
483 Cortex-A53 parts up to r0p4.
487 config ARM64_ERRATUM_1024718
488 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
491 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
493 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
494 update of the hardware dirty bit when the DBM/AP bits are updated
495 without a break-before-make. The workaround is to disable the usage
496 of hardware DBM locally on the affected cores. CPUs not affected by
497 this erratum will continue to use the feature.
501 config ARM64_ERRATUM_1418040
502 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
506 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
507 errata 1188873 and 1418040.
509 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
510 cause register corruption when accessing the timer registers
511 from AArch32 userspace.
515 config ARM64_ERRATUM_1165522
516 bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
519 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
521 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
522 corrupted TLBs by speculating an AT instruction during a guest
527 config ARM64_ERRATUM_1286807
528 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
530 select ARM64_WORKAROUND_REPEAT_TLBI
532 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
534 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
535 address for a cacheable mapping of a location is being
536 accessed by a core while another core is remapping the virtual
537 address to a new physical page using the recommended
538 break-before-make sequence, then under very rare circumstances
539 TLBI+DSB completes before a read using the translation being
540 invalidated has been observed by other observers. The
541 workaround repeats the TLBI+DSB operation.
545 config ARM64_ERRATUM_1463225
546 bool "Cortex-A76: Software Step might prevent interrupt recognition"
549 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
551 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
552 of a system call instruction (SVC) can prevent recognition of
553 subsequent interrupts when software stepping is disabled in the
554 exception handler of the system call and either kernel debugging
555 is enabled or VHE is in use.
557 Work around the erratum by triggering a dummy step exception
558 when handling a system call from a task that is being stepped
559 in a VHE configuration of the kernel.
563 config CAVIUM_ERRATUM_22375
564 bool "Cavium erratum 22375, 24313"
567 Enable workaround for errata 22375 and 24313.
569 This implements two gicv3-its errata workarounds for ThunderX. Both
570 with a small impact affecting only ITS table allocation.
572 erratum 22375: only alloc 8MB table size
573 erratum 24313: ignore memory access type
575 The fixes are in ITS initialization and basically ignore memory access
576 type and table size provided by the TYPER and BASER registers.
580 config CAVIUM_ERRATUM_23144
581 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
585 ITS SYNC command hang for cross node io and collections/cpu mapping.
589 config CAVIUM_ERRATUM_23154
590 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
593 The gicv3 of ThunderX requires a modified version for
594 reading the IAR status to ensure data synchronization
595 (access to icc_iar1_el1 is not sync'ed before and after).
599 config CAVIUM_ERRATUM_27456
600 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
603 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
604 instructions may cause the icache to become corrupted if it
605 contains data for a non-current ASID. The fix is to
606 invalidate the icache when changing the mm context.
610 config CAVIUM_ERRATUM_30115
611 bool "Cavium erratum 30115: Guest may disable interrupts in host"
614 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
615 1.2, and T83 Pass 1.0, KVM guest execution may disable
616 interrupts in host. Trapping both GICv3 group-0 and group-1
617 accesses sidesteps the issue.
621 config QCOM_FALKOR_ERRATUM_1003
622 bool "Falkor E1003: Incorrect translation due to ASID change"
625 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
626 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
627 in TTBR1_EL1, this situation only occurs in the entry trampoline and
628 then only for entries in the walk cache, since the leaf translation
629 is unchanged. Work around the erratum by invalidating the walk cache
630 entries for the trampoline before entering the kernel proper.
632 config ARM64_WORKAROUND_REPEAT_TLBI
635 config QCOM_FALKOR_ERRATUM_1009
636 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
638 select ARM64_WORKAROUND_REPEAT_TLBI
640 On Falkor v1, the CPU may prematurely complete a DSB following a
641 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
642 one more time to fix the issue.
646 config QCOM_QDF2400_ERRATUM_0065
647 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
650 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
651 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
652 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
656 config SOCIONEXT_SYNQUACER_PREITS
657 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
660 Socionext Synquacer SoCs implement a separate h/w block to generate
661 MSI doorbell writes with non-zero values for the device ID.
665 config HISILICON_ERRATUM_161600802
666 bool "Hip07 161600802: Erroneous redistributor VLPI base"
669 The HiSilicon Hip07 SoC uses the wrong redistributor base
670 when issued ITS commands such as VMOVP and VMAPP, and requires
671 a 128kB offset to be applied to the target address in this commands.
675 config QCOM_FALKOR_ERRATUM_E1041
676 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
679 Falkor CPU may speculatively fetch instructions from an improper
680 memory location when MMU translation is changed from SCTLR_ELn[M]=1
681 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
685 config FUJITSU_ERRATUM_010001
686 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
689 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
690 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
691 accesses may cause undefined fault (Data abort, DFSC=0b111111).
692 This fault occurs under a specific hardware condition when a
693 load/store instruction performs an address translation using:
694 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
695 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
696 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
697 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
699 The workaround is to ensure these bits are clear in TCR_ELx.
700 The workaround only affects the Fujitsu-A64FX.
709 default ARM64_4K_PAGES
711 Page size (translation granule) configuration.
713 config ARM64_4K_PAGES
716 This feature enables 4KB pages support.
718 config ARM64_16K_PAGES
721 The system will use 16KB pages support. AArch32 emulation
722 requires applications compiled with 16K (or a multiple of 16K)
725 config ARM64_64K_PAGES
728 This feature enables 64KB pages support (4KB by default)
729 allowing only two levels of page tables and faster TLB
730 look-up. AArch32 emulation requires applications compiled
731 with 64K aligned segments.
736 prompt "Virtual address space size"
737 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
738 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
739 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
741 Allows choosing one of multiple possible virtual address
742 space sizes. The level of translation table is determined by
743 a combination of page size and virtual address space size.
745 config ARM64_VA_BITS_36
746 bool "36-bit" if EXPERT
747 depends on ARM64_16K_PAGES
749 config ARM64_VA_BITS_39
751 depends on ARM64_4K_PAGES
753 config ARM64_VA_BITS_42
755 depends on ARM64_64K_PAGES
757 config ARM64_VA_BITS_47
759 depends on ARM64_16K_PAGES
761 config ARM64_VA_BITS_48
764 config ARM64_VA_BITS_52
766 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
768 Enable 52-bit virtual addressing for userspace when explicitly
769 requested via a hint to mmap(). The kernel will also use 52-bit
770 virtual addresses for its own mappings (provided HW support for
771 this feature is available, otherwise it reverts to 48-bit).
773 NOTE: Enabling 52-bit virtual addressing in conjunction with
774 ARMv8.3 Pointer Authentication will result in the PAC being
775 reduced from 7 bits to 3 bits, which may have a significant
776 impact on its susceptibility to brute-force attacks.
778 If unsure, select 48-bit virtual addressing instead.
782 config ARM64_FORCE_52BIT
783 bool "Force 52-bit virtual addresses for userspace"
784 depends on ARM64_VA_BITS_52 && EXPERT
786 For systems with 52-bit userspace VAs enabled, the kernel will attempt
787 to maintain compatibility with older software by providing 48-bit VAs
788 unless a hint is supplied to mmap.
790 This configuration option disables the 48-bit compatibility logic, and
791 forces all userspace addresses to be 52-bit on HW that supports it. One
792 should only enable this configuration option for stress testing userspace
793 memory management code. If unsure say N here.
797 default 36 if ARM64_VA_BITS_36
798 default 39 if ARM64_VA_BITS_39
799 default 42 if ARM64_VA_BITS_42
800 default 47 if ARM64_VA_BITS_47
801 default 48 if ARM64_VA_BITS_48
802 default 52 if ARM64_VA_BITS_52
805 prompt "Physical address space size"
806 default ARM64_PA_BITS_48
808 Choose the maximum physical address range that the kernel will
811 config ARM64_PA_BITS_48
814 config ARM64_PA_BITS_52
815 bool "52-bit (ARMv8.2)"
816 depends on ARM64_64K_PAGES
817 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
819 Enable support for a 52-bit physical address space, introduced as
820 part of the ARMv8.2-LPA extension.
822 With this enabled, the kernel will also continue to work on CPUs that
823 do not support ARMv8.2-LPA, but with some added memory overhead (and
824 minor performance overhead).
830 default 48 if ARM64_PA_BITS_48
831 default 52 if ARM64_PA_BITS_52
833 config CPU_BIG_ENDIAN
834 bool "Build big-endian kernel"
836 Say Y if you plan on running a kernel in big-endian mode.
839 bool "Multi-core scheduler support"
841 Multi-core scheduler support improves the CPU scheduler's decision
842 making when dealing with multi-core CPU chips at a cost of slightly
843 increased overhead in some places. If unsure say N here.
846 bool "SMT scheduler support"
848 Improves the CPU scheduler's decision making when dealing with
849 MultiThreading at a cost of slightly increased overhead in some
850 places. If unsure say N here.
853 int "Maximum number of CPUs (2-4096)"
858 bool "Support for hot-pluggable CPUs"
859 select GENERIC_IRQ_MIGRATION
861 Say Y here to experiment with turning CPUs off and on. CPUs
862 can be controlled through /sys/devices/system/cpu.
864 # Common NUMA Features
866 bool "Numa Memory Allocation and Scheduler Support"
867 select ACPI_NUMA if ACPI
870 Enable NUMA (Non Uniform Memory Access) support.
872 The kernel will try to allocate memory used by a CPU on the
873 local memory of the CPU and add some more
874 NUMA awareness to the kernel.
877 int "Maximum NUMA Nodes (as a power of 2)"
880 depends on NEED_MULTIPLE_NODES
882 Specify the maximum number of NUMA Nodes available on the target
883 system. Increases memory reserved to accommodate various tables.
885 config USE_PERCPU_NUMA_NODE_ID
889 config HAVE_SETUP_PER_CPU_AREA
893 config NEED_PER_CPU_EMBED_FIRST_CHUNK
900 source "kernel/Kconfig.hz"
902 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
905 config ARCH_SPARSEMEM_ENABLE
907 select SPARSEMEM_VMEMMAP_ENABLE
909 config ARCH_SPARSEMEM_DEFAULT
910 def_bool ARCH_SPARSEMEM_ENABLE
912 config ARCH_SELECT_MEMORY_MODEL
913 def_bool ARCH_SPARSEMEM_ENABLE
915 config ARCH_FLATMEM_ENABLE
918 config HAVE_ARCH_PFN_VALID
921 config HW_PERF_EVENTS
925 config SYS_SUPPORTS_HUGETLBFS
928 config ARCH_WANT_HUGE_PMD_SHARE
930 config ARCH_HAS_CACHE_LINE_SIZE
933 config ARCH_ENABLE_SPLIT_PMD_PTLOCK
934 def_bool y if PGTABLE_LEVELS > 2
937 bool "Enable seccomp to safely compute untrusted bytecode"
939 This kernel feature is useful for number crunching applications
940 that may need to compute untrusted bytecode during their
941 execution. By using pipes or other transports made available to
942 the process as file descriptors supporting the read/write
943 syscalls, it's possible to isolate those applications in
944 their own address space using seccomp. Once seccomp is
945 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
946 and the task is only allowed to execute a few safe syscalls
947 defined by each seccomp mode.
950 bool "Enable paravirtualization code"
952 This changes the kernel so it can modify itself when it is run
953 under a hypervisor, potentially improving performance significantly
954 over full virtualization.
956 config PARAVIRT_TIME_ACCOUNTING
957 bool "Paravirtual steal time accounting"
960 Select this option to enable fine granularity task steal time
961 accounting. Time spent executing other tasks in parallel with
962 the current vCPU is discounted from the vCPU power. To account for
963 that, there can be a small performance impact.
965 If in doubt, say N here.
968 depends on PM_SLEEP_SMP
970 bool "kexec system call"
972 kexec is a system call that implements the ability to shutdown your
973 current kernel, and to start another kernel. It is like a reboot
974 but it is independent of the system firmware. And like a reboot
975 you can start any kernel with it, not just Linux.
978 bool "kexec file based system call"
981 This is new version of kexec system call. This system call is
982 file based and takes file descriptors as system call argument
983 for kernel and initramfs as opposed to list of segments as
984 accepted by previous system call.
986 config KEXEC_VERIFY_SIG
987 bool "Verify kernel signature during kexec_file_load() syscall"
988 depends on KEXEC_FILE
990 Select this option to verify a signature with loaded kernel
991 image. If configured, any attempt of loading a image without
992 valid signature will fail.
994 In addition to that option, you need to enable signature
995 verification for the corresponding kernel image type being
996 loaded in order for this to work.
998 config KEXEC_IMAGE_VERIFY_SIG
999 bool "Enable Image signature verification support"
1001 depends on KEXEC_VERIFY_SIG
1002 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1004 Enable Image signature verification support.
1006 comment "Support for PE file signature verification disabled"
1007 depends on KEXEC_VERIFY_SIG
1008 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1011 bool "Build kdump crash kernel"
1013 Generate crash dump after being started by kexec. This should
1014 be normally only set in special crash dump kernels which are
1015 loaded in the main kernel with kexec-tools into a specially
1016 reserved region and then later executed after a crash by
1019 For more details see Documentation/admin-guide/kdump/kdump.rst
1026 bool "Xen guest support on ARM64"
1027 depends on ARM64 && OF
1031 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1033 config FORCE_MAX_ZONEORDER
1035 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
1036 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
1039 The kernel memory allocator divides physically contiguous memory
1040 blocks into "zones", where each zone is a power of two number of
1041 pages. This option selects the largest power of two that the kernel
1042 keeps in the memory allocator. If you need to allocate very large
1043 blocks of physically contiguous memory, then you may need to
1044 increase this value.
1046 This config option is actually maximum order plus one. For example,
1047 a value of 11 means that the largest free memory block is 2^10 pages.
1049 We make sure that we can allocate upto a HugePage size for each configuration.
1051 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1053 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1054 4M allocations matching the default size used by generic code.
1056 config UNMAP_KERNEL_AT_EL0
1057 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1060 Speculation attacks against some high-performance processors can
1061 be used to bypass MMU permission checks and leak kernel data to
1062 userspace. This can be defended against by unmapping the kernel
1063 when running in userspace, mapping it back in on exception entry
1064 via a trampoline page in the vector table.
1068 config HARDEN_BRANCH_PREDICTOR
1069 bool "Harden the branch predictor against aliasing attacks" if EXPERT
1072 Speculation attacks against some high-performance processors rely on
1073 being able to manipulate the branch predictor for a victim context by
1074 executing aliasing branches in the attacker context. Such attacks
1075 can be partially mitigated against by clearing internal branch
1076 predictor state and limiting the prediction logic in some situations.
1078 This config option will take CPU-specific actions to harden the
1079 branch predictor against aliasing attacks and may rely on specific
1080 instruction sequences or control bits being set by the system
1085 config HARDEN_EL2_VECTORS
1086 bool "Harden EL2 vector mapping against system register leak" if EXPERT
1089 Speculation attacks against some high-performance processors can
1090 be used to leak privileged information such as the vector base
1091 register, resulting in a potential defeat of the EL2 layout
1094 This config option will map the vectors to a fixed location,
1095 independent of the EL2 code mapping, so that revealing VBAR_EL2
1096 to an attacker does not give away any extra information. This
1097 only gets enabled on affected CPUs.
1102 bool "Speculative Store Bypass Disable" if EXPERT
1105 This enables mitigation of the bypassing of previous stores
1106 by speculative loads.
1110 config RODATA_FULL_DEFAULT_ENABLED
1111 bool "Apply r/o permissions of VM areas also to their linear aliases"
1114 Apply read-only attributes of VM areas to the linear alias of
1115 the backing pages as well. This prevents code or read-only data
1116 from being modified (inadvertently or intentionally) via another
1117 mapping of the same memory page. This additional enhancement can
1118 be turned off at runtime by passing rodata=[off|on] (and turned on
1119 with rodata=full if this option is set to 'n')
1121 This requires the linear region to be mapped down to pages,
1122 which may adversely affect performance in some cases.
1124 config ARM64_SW_TTBR0_PAN
1125 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1127 Enabling this option prevents the kernel from accessing
1128 user-space memory directly by pointing TTBR0_EL1 to a reserved
1129 zeroed area and reserved ASID. The user access routines
1130 restore the valid TTBR0_EL1 temporarily.
1132 config ARM64_TAGGED_ADDR_ABI
1133 bool "Enable the tagged user addresses syscall ABI"
1136 When this option is enabled, user applications can opt in to a
1137 relaxed ABI via prctl() allowing tagged addresses to be passed
1138 to system calls as pointer arguments. For details, see
1139 Documentation/arm64/tagged-address-abi.rst.
1142 bool "Kernel support for 32-bit EL0"
1143 depends on ARM64_4K_PAGES || EXPERT
1144 select COMPAT_BINFMT_ELF if BINFMT_ELF
1146 select OLD_SIGSUSPEND3
1147 select COMPAT_OLD_SIGACTION
1149 This option enables support for a 32-bit EL0 running under a 64-bit
1150 kernel at EL1. AArch32-specific components such as system calls,
1151 the user helper functions, VFP support and the ptrace interface are
1152 handled appropriately by the kernel.
1154 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1155 that you will only be able to execute AArch32 binaries that were compiled
1156 with page size aligned segments.
1158 If you want to execute 32-bit userspace applications, say Y.
1162 config KUSER_HELPERS
1163 bool "Enable kuser helpers page for 32 bit applications"
1166 Warning: disabling this option may break 32-bit user programs.
1168 Provide kuser helpers to compat tasks. The kernel provides
1169 helper code to userspace in read only form at a fixed location
1170 to allow userspace to be independent of the CPU type fitted to
1171 the system. This permits binaries to be run on ARMv4 through
1172 to ARMv8 without modification.
1174 See Documentation/arm/kernel_user_helpers.rst for details.
1176 However, the fixed address nature of these helpers can be used
1177 by ROP (return orientated programming) authors when creating
1180 If all of the binaries and libraries which run on your platform
1181 are built specifically for your platform, and make no use of
1182 these helpers, then you can turn this option off to hinder
1183 such exploits. However, in that case, if a binary or library
1184 relying on those helpers is run, it will not function correctly.
1186 Say N here only if you are absolutely certain that you do not
1187 need these helpers; otherwise, the safe option is to say Y.
1190 menuconfig ARMV8_DEPRECATED
1191 bool "Emulate deprecated/obsolete ARMv8 instructions"
1194 Legacy software support may require certain instructions
1195 that have been deprecated or obsoleted in the architecture.
1197 Enable this config to enable selective emulation of these
1204 config SWP_EMULATION
1205 bool "Emulate SWP/SWPB instructions"
1207 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1208 they are always undefined. Say Y here to enable software
1209 emulation of these instructions for userspace using LDXR/STXR.
1211 In some older versions of glibc [<=2.8] SWP is used during futex
1212 trylock() operations with the assumption that the code will not
1213 be preempted. This invalid assumption may be more likely to fail
1214 with SWP emulation enabled, leading to deadlock of the user
1217 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1218 on an external transaction monitoring block called a global
1219 monitor to maintain update atomicity. If your system does not
1220 implement a global monitor, this option can cause programs that
1221 perform SWP operations to uncached memory to deadlock.
1225 config CP15_BARRIER_EMULATION
1226 bool "Emulate CP15 Barrier instructions"
1228 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1229 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1230 strongly recommended to use the ISB, DSB, and DMB
1231 instructions instead.
1233 Say Y here to enable software emulation of these
1234 instructions for AArch32 userspace code. When this option is
1235 enabled, CP15 barrier usage is traced which can help
1236 identify software that needs updating.
1240 config SETEND_EMULATION
1241 bool "Emulate SETEND instruction"
1243 The SETEND instruction alters the data-endianness of the
1244 AArch32 EL0, and is deprecated in ARMv8.
1246 Say Y here to enable software emulation of the instruction
1247 for AArch32 userspace code.
1249 Note: All the cpus on the system must have mixed endian support at EL0
1250 for this feature to be enabled. If a new CPU - which doesn't support mixed
1251 endian - is hotplugged in after this feature has been enabled, there could
1252 be unexpected results in the applications.
1259 menu "ARMv8.1 architectural features"
1261 config ARM64_HW_AFDBM
1262 bool "Support for hardware updates of the Access and Dirty page flags"
1265 The ARMv8.1 architecture extensions introduce support for
1266 hardware updates of the access and dirty information in page
1267 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1268 capable processors, accesses to pages with PTE_AF cleared will
1269 set this bit instead of raising an access flag fault.
1270 Similarly, writes to read-only pages with the DBM bit set will
1271 clear the read-only bit (AP[2]) instead of raising a
1274 Kernels built with this configuration option enabled continue
1275 to work on pre-ARMv8.1 hardware and the performance impact is
1276 minimal. If unsure, say Y.
1279 bool "Enable support for Privileged Access Never (PAN)"
1282 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1283 prevents the kernel or hypervisor from accessing user-space (EL0)
1286 Choosing this option will cause any unprotected (not using
1287 copy_to_user et al) memory access to fail with a permission fault.
1289 The feature is detected at runtime, and will remain as a 'nop'
1290 instruction if the cpu does not implement the feature.
1292 config ARM64_LSE_ATOMICS
1293 bool "Atomic instructions"
1294 depends on JUMP_LABEL
1297 As part of the Large System Extensions, ARMv8.1 introduces new
1298 atomic instructions that are designed specifically to scale in
1301 Say Y here to make use of these instructions for the in-kernel
1302 atomic routines. This incurs a small overhead on CPUs that do
1303 not support these instructions and requires the kernel to be
1304 built with binutils >= 2.25 in order for the new instructions
1308 bool "Enable support for Virtualization Host Extensions (VHE)"
1311 Virtualization Host Extensions (VHE) allow the kernel to run
1312 directly at EL2 (instead of EL1) on processors that support
1313 it. This leads to better performance for KVM, as they reduce
1314 the cost of the world switch.
1316 Selecting this option allows the VHE feature to be detected
1317 at runtime, and does not affect processors that do not
1318 implement this feature.
1322 menu "ARMv8.2 architectural features"
1325 bool "Enable support for User Access Override (UAO)"
1328 User Access Override (UAO; part of the ARMv8.2 Extensions)
1329 causes the 'unprivileged' variant of the load/store instructions to
1330 be overridden to be privileged.
1332 This option changes get_user() and friends to use the 'unprivileged'
1333 variant of the load/store instructions. This ensures that user-space
1334 really did have access to the supplied memory. When addr_limit is
1335 set to kernel memory the UAO bit will be set, allowing privileged
1336 access to kernel memory.
1338 Choosing this option will cause copy_to_user() et al to use user-space
1341 The feature is detected at runtime, the kernel will use the
1342 regular load/store instructions if the cpu does not implement the
1346 bool "Enable support for persistent memory"
1347 select ARCH_HAS_PMEM_API
1348 select ARCH_HAS_UACCESS_FLUSHCACHE
1350 Say Y to enable support for the persistent memory API based on the
1351 ARMv8.2 DCPoP feature.
1353 The feature is detected at runtime, and the kernel will use DC CVAC
1354 operations if DC CVAP is not supported (following the behaviour of
1355 DC CVAP itself if the system does not define a point of persistence).
1357 config ARM64_RAS_EXTN
1358 bool "Enable support for RAS CPU Extensions"
1361 CPUs that support the Reliability, Availability and Serviceability
1362 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1363 errors, classify them and report them to software.
1365 On CPUs with these extensions system software can use additional
1366 barriers to determine if faults are pending and read the
1367 classification from a new set of registers.
1369 Selecting this feature will allow the kernel to use these barriers
1370 and access the new registers if the system supports the extension.
1371 Platform RAS features may additionally depend on firmware support.
1374 bool "Enable support for Common Not Private (CNP) translations"
1376 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1378 Common Not Private (CNP) allows translation table entries to
1379 be shared between different PEs in the same inner shareable
1380 domain, so the hardware can use this fact to optimise the
1381 caching of such entries in the TLB.
1383 Selecting this option allows the CNP feature to be detected
1384 at runtime, and does not affect PEs that do not implement
1389 menu "ARMv8.3 architectural features"
1391 config ARM64_PTR_AUTH
1392 bool "Enable support for pointer authentication"
1394 depends on !KVM || ARM64_VHE
1396 Pointer authentication (part of the ARMv8.3 Extensions) provides
1397 instructions for signing and authenticating pointers against secret
1398 keys, which can be used to mitigate Return Oriented Programming (ROP)
1401 This option enables these instructions at EL0 (i.e. for userspace).
1403 Choosing this option will cause the kernel to initialise secret keys
1404 for each process at exec() time, with these keys being
1405 context-switched along with the process.
1407 The feature is detected at runtime. If the feature is not present in
1408 hardware it will not be advertised to userspace/KVM guest nor will it
1409 be enabled. However, KVM guest also require VHE mode and hence
1410 CONFIG_ARM64_VHE=y option to use this feature.
1415 bool "ARM Scalable Vector Extension support"
1417 depends on !KVM || ARM64_VHE
1419 The Scalable Vector Extension (SVE) is an extension to the AArch64
1420 execution state which complements and extends the SIMD functionality
1421 of the base architecture to support much larger vectors and to enable
1422 additional vectorisation opportunities.
1424 To enable use of this extension on CPUs that implement it, say Y.
1426 On CPUs that support the SVE2 extensions, this option will enable
1429 Note that for architectural reasons, firmware _must_ implement SVE
1430 support when running on SVE capable hardware. The required support
1433 * version 1.5 and later of the ARM Trusted Firmware
1434 * the AArch64 boot wrapper since commit 5e1261e08abf
1435 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1437 For other firmware implementations, consult the firmware documentation
1440 If you need the kernel to boot on SVE-capable hardware with broken
1441 firmware, you may need to say N here until you get your firmware
1442 fixed. Otherwise, you may experience firmware panics or lockups when
1443 booting the kernel. If unsure and you are not observing these
1444 symptoms, you should assume that it is safe to say Y.
1446 CPUs that support SVE are architecturally required to support the
1447 Virtualization Host Extensions (VHE), so the kernel makes no
1448 provision for supporting SVE alongside KVM without VHE enabled.
1449 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1450 KVM in the same kernel image.
1452 config ARM64_MODULE_PLTS
1453 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1455 select HAVE_MOD_ARCH_SPECIFIC
1457 Allocate PLTs when loading modules so that jumps and calls whose
1458 targets are too far away for their relative offsets to be encoded
1459 in the instructions themselves can be bounced via veneers in the
1460 module's PLT. This allows modules to be allocated in the generic
1461 vmalloc area after the dedicated module memory area has been
1464 When running with address space randomization (KASLR), the module
1465 region itself may be too far away for ordinary relative jumps and
1466 calls, and so in that case, module PLTs are required and cannot be
1469 Specific errata workaround(s) might also force module PLTs to be
1470 enabled (ARM64_ERRATUM_843419).
1472 config ARM64_PSEUDO_NMI
1473 bool "Support for NMI-like interrupts"
1474 select CONFIG_ARM_GIC_V3
1476 Adds support for mimicking Non-Maskable Interrupts through the use of
1477 GIC interrupt priority. This support requires version 3 or later of
1480 This high priority configuration for interrupts needs to be
1481 explicitly enabled by setting the kernel parameter
1482 "irqchip.gicv3_pseudo_nmi" to 1.
1487 config ARM64_DEBUG_PRIORITY_MASKING
1488 bool "Debug interrupt priority masking"
1490 This adds runtime checks to functions enabling/disabling
1491 interrupts when using priority masking. The additional checks verify
1492 the validity of ICC_PMR_EL1 when calling concerned functions.
1499 select ARCH_HAS_RELR
1501 This builds the kernel as a Position Independent Executable (PIE),
1502 which retains all relocation metadata required to relocate the
1503 kernel binary at runtime to a different virtual address than the
1504 address it was linked at.
1505 Since AArch64 uses the RELA relocation format, this requires a
1506 relocation pass at runtime even if the kernel is loaded at the
1507 same address it was linked at.
1509 config RANDOMIZE_BASE
1510 bool "Randomize the address of the kernel image"
1511 select ARM64_MODULE_PLTS if MODULES
1514 Randomizes the virtual address at which the kernel image is
1515 loaded, as a security feature that deters exploit attempts
1516 relying on knowledge of the location of kernel internals.
1518 It is the bootloader's job to provide entropy, by passing a
1519 random u64 value in /chosen/kaslr-seed at kernel entry.
1521 When booting via the UEFI stub, it will invoke the firmware's
1522 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1523 to the kernel proper. In addition, it will randomise the physical
1524 location of the kernel Image as well.
1528 config RANDOMIZE_MODULE_REGION_FULL
1529 bool "Randomize the module region over a 4 GB range"
1530 depends on RANDOMIZE_BASE
1533 Randomizes the location of the module region inside a 4 GB window
1534 covering the core kernel. This way, it is less likely for modules
1535 to leak information about the location of core kernel data structures
1536 but it does imply that function calls between modules and the core
1537 kernel will need to be resolved via veneers in the module PLT.
1539 When this option is not set, the module region will be randomized over
1540 a limited range that contains the [_stext, _etext] interval of the
1541 core kernel, so branch relocations are always in range.
1543 config CC_HAVE_STACKPROTECTOR_SYSREG
1544 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
1546 config STACKPROTECTOR_PER_TASK
1548 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
1554 config ARM64_ACPI_PARKING_PROTOCOL
1555 bool "Enable support for the ARM64 ACPI parking protocol"
1558 Enable support for the ARM64 ACPI parking protocol. If disabled
1559 the kernel will not allow booting through the ARM64 ACPI parking
1560 protocol even if the corresponding data is present in the ACPI
1564 string "Default kernel command string"
1567 Provide a set of default command-line options at build time by
1568 entering them here. As a minimum, you should specify the the
1569 root device (e.g. root=/dev/nfs).
1571 config CMDLINE_FORCE
1572 bool "Always use the default kernel command string"
1574 Always use the default kernel command string, even if the boot
1575 loader passes other arguments to the kernel.
1576 This is useful if you cannot or don't want to change the
1577 command-line options your boot loader passes to the kernel.
1583 bool "UEFI runtime support"
1584 depends on OF && !CPU_BIG_ENDIAN
1585 depends on KERNEL_MODE_NEON
1586 select ARCH_SUPPORTS_ACPI
1589 select EFI_PARAMS_FROM_FDT
1590 select EFI_RUNTIME_WRAPPERS
1595 This option provides support for runtime services provided
1596 by UEFI firmware (such as non-volatile variables, realtime
1597 clock, and platform reset). A UEFI stub is also provided to
1598 allow the kernel to be booted as an EFI application. This
1599 is only useful on systems that have UEFI firmware.
1602 bool "Enable support for SMBIOS (DMI) tables"
1606 This enables SMBIOS/DMI feature for systems.
1608 This option is only useful on systems that have UEFI firmware.
1609 However, even with this option, the resultant kernel should
1610 continue to boot on existing non-UEFI platforms.
1614 config SYSVIPC_COMPAT
1616 depends on COMPAT && SYSVIPC
1618 config ARCH_ENABLE_HUGEPAGE_MIGRATION
1620 depends on HUGETLB_PAGE && MIGRATION
1622 menu "Power management options"
1624 source "kernel/power/Kconfig"
1626 config ARCH_HIBERNATION_POSSIBLE
1630 config ARCH_HIBERNATION_HEADER
1632 depends on HIBERNATION
1634 config ARCH_SUSPEND_POSSIBLE
1639 menu "CPU Power Management"
1641 source "drivers/cpuidle/Kconfig"
1643 source "drivers/cpufreq/Kconfig"
1647 source "drivers/firmware/Kconfig"
1649 source "drivers/acpi/Kconfig"
1651 source "arch/arm64/kvm/Kconfig"
1654 source "arch/arm64/crypto/Kconfig"