1 # SPDX-License-Identifier: GPL-2.0-only
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI
9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10 select ACPI_MCFG if (ACPI && PCI)
11 select ACPI_SPCR_TABLE if ACPI
12 select ACPI_PPTT if ACPI
13 select ARCH_HAS_DEBUG_WX
14 select ARCH_BINFMT_ELF_EXTRA_PHDRS
15 select ARCH_BINFMT_ELF_STATE
16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18 select ARCH_ENABLE_MEMORY_HOTPLUG
19 select ARCH_ENABLE_MEMORY_HOTREMOVE
20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22 select ARCH_HAS_CACHE_LINE_SIZE
23 select ARCH_HAS_CURRENT_STACK_POINTER
24 select ARCH_HAS_DEBUG_VIRTUAL
25 select ARCH_HAS_DEBUG_VM_PGTABLE
26 select ARCH_HAS_DMA_PREP_COHERENT
27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28 select ARCH_HAS_FAST_MULTIPLIER
29 select ARCH_HAS_FORTIFY_SOURCE
30 select ARCH_HAS_GCOV_PROFILE_ALL
31 select ARCH_HAS_GIGANTIC_PAGE
33 select ARCH_HAS_KEEPINITRD
34 select ARCH_HAS_MEMBARRIER_SYNC_CORE
35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37 select ARCH_HAS_PTE_DEVMAP
38 select ARCH_HAS_PTE_SPECIAL
39 select ARCH_HAS_SETUP_DMA_OPS
40 select ARCH_HAS_SET_DIRECT_MAP
41 select ARCH_HAS_SET_MEMORY
43 select ARCH_HAS_STRICT_KERNEL_RWX
44 select ARCH_HAS_STRICT_MODULE_RWX
45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
46 select ARCH_HAS_SYNC_DMA_FOR_CPU
47 select ARCH_HAS_SYSCALL_WRAPPER
48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
50 select ARCH_HAS_ZONE_DMA_SET if EXPERT
51 select ARCH_HAVE_ELF_PROT
52 select ARCH_HAVE_NMI_SAFE_CMPXCHG
53 select ARCH_HAVE_TRACE_MMIO_ACCESS
54 select ARCH_INLINE_READ_LOCK if !PREEMPTION
55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
80 select ARCH_KEEP_MEMBLOCK
81 select ARCH_USE_CMPXCHG_LOCKREF
82 select ARCH_USE_GNU_PROPERTY
83 select ARCH_USE_MEMTEST
84 select ARCH_USE_QUEUED_RWLOCKS
85 select ARCH_USE_QUEUED_SPINLOCKS
86 select ARCH_USE_SYM_ANNOTATIONS
87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC
88 select ARCH_SUPPORTS_HUGETLBFS
89 select ARCH_SUPPORTS_MEMORY_FAILURE
90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
92 select ARCH_SUPPORTS_LTO_CLANG_THIN
93 select ARCH_SUPPORTS_CFI_CLANG
94 select ARCH_SUPPORTS_ATOMIC_RMW
95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
96 select ARCH_SUPPORTS_NUMA_BALANCING
97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK
98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
99 select ARCH_WANT_DEFAULT_BPF_JIT
100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
101 select ARCH_WANT_FRAME_POINTERS
102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
103 select ARCH_WANT_LD_ORPHAN_WARN
104 select ARCH_WANTS_NO_INSTR
105 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
106 select ARCH_HAS_UBSAN_SANITIZE_ALL
108 select ARM_ARCH_TIMER
110 select AUDIT_ARCH_COMPAT_GENERIC
111 select ARM_GIC_V2M if PCI
113 select ARM_GIC_V3_ITS if PCI
115 select BUILDTIME_TABLE_SORT
116 select CLONE_BACKWARDS
118 select CPU_PM if (SUSPEND || CPU_IDLE)
120 select DCACHE_WORD_ACCESS
121 select DYNAMIC_FTRACE if FUNCTION_TRACER
122 select DMA_DIRECT_REMAP
125 select FUNCTION_ALIGNMENT_4B
126 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
127 select GENERIC_ALLOCATOR
128 select GENERIC_ARCH_TOPOLOGY
129 select GENERIC_CLOCKEVENTS_BROADCAST
130 select GENERIC_CPU_AUTOPROBE
131 select GENERIC_CPU_VULNERABILITIES
132 select GENERIC_EARLY_IOREMAP
133 select GENERIC_IDLE_POLL_SETUP
134 select GENERIC_IOREMAP
135 select GENERIC_IRQ_IPI
136 select GENERIC_IRQ_PROBE
137 select GENERIC_IRQ_SHOW
138 select GENERIC_IRQ_SHOW_LEVEL
139 select GENERIC_LIB_DEVMEM_IS_ALLOWED
140 select GENERIC_PCI_IOMAP
141 select GENERIC_PTDUMP
142 select GENERIC_SCHED_CLOCK
143 select GENERIC_SMP_IDLE_THREAD
144 select GENERIC_TIME_VSYSCALL
145 select GENERIC_GETTIMEOFDAY
146 select GENERIC_VDSO_TIME_NS
147 select HARDIRQS_SW_RESEND
151 select HAVE_ACPI_APEI if (ACPI && EFI)
152 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
153 select HAVE_ARCH_AUDITSYSCALL
154 select HAVE_ARCH_BITREVERSE
155 select HAVE_ARCH_COMPILER_H
156 select HAVE_ARCH_HUGE_VMALLOC
157 select HAVE_ARCH_HUGE_VMAP
158 select HAVE_ARCH_JUMP_LABEL
159 select HAVE_ARCH_JUMP_LABEL_RELATIVE
160 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
161 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
162 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
163 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
164 # Some instrumentation may be unsound, hence EXPERT
165 select HAVE_ARCH_KCSAN if EXPERT
166 select HAVE_ARCH_KFENCE
167 select HAVE_ARCH_KGDB
168 select HAVE_ARCH_MMAP_RND_BITS
169 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
170 select HAVE_ARCH_PREL32_RELOCATIONS
171 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
172 select HAVE_ARCH_SECCOMP_FILTER
173 select HAVE_ARCH_STACKLEAK
174 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
175 select HAVE_ARCH_TRACEHOOK
176 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
177 select HAVE_ARCH_VMAP_STACK
178 select HAVE_ARM_SMCCC
179 select HAVE_ASM_MODVERSIONS
181 select HAVE_C_RECORDMCOUNT
182 select HAVE_CMPXCHG_DOUBLE
183 select HAVE_CMPXCHG_LOCAL
184 select HAVE_CONTEXT_TRACKING_USER
185 select HAVE_DEBUG_KMEMLEAK
186 select HAVE_DMA_CONTIGUOUS
187 select HAVE_DYNAMIC_FTRACE
188 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
189 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
190 !CC_OPTIMIZE_FOR_SIZE)
191 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
192 if DYNAMIC_FTRACE_WITH_ARGS
193 select HAVE_EFFICIENT_UNALIGNED_ACCESS
195 select HAVE_FTRACE_MCOUNT_RECORD
196 select HAVE_FUNCTION_TRACER
197 select HAVE_FUNCTION_ERROR_INJECTION
198 select HAVE_FUNCTION_GRAPH_TRACER
199 select HAVE_GCC_PLUGINS
200 select HAVE_HW_BREAKPOINT if PERF_EVENTS
201 select HAVE_IOREMAP_PROT
202 select HAVE_IRQ_TIME_ACCOUNTING
205 select HAVE_PERF_EVENTS
206 select HAVE_PERF_REGS
207 select HAVE_PERF_USER_STACK_DUMP
208 select HAVE_PREEMPT_DYNAMIC_KEY
209 select HAVE_REGS_AND_STACK_ACCESS_API
210 select HAVE_POSIX_CPU_TIMERS_TASK_WORK
211 select HAVE_FUNCTION_ARG_ACCESS_API
212 select MMU_GATHER_RCU_TABLE_FREE
214 select HAVE_STACKPROTECTOR
215 select HAVE_SYSCALL_TRACEPOINTS
217 select HAVE_KRETPROBES
218 select HAVE_GENERIC_VDSO
220 select IRQ_FORCED_THREADING
221 select KASAN_VMALLOC if KASAN
222 select MODULES_USE_ELF_RELA
223 select NEED_DMA_MAP_STATE
224 select NEED_SG_DMA_LENGTH
226 select OF_EARLY_FLATTREE
227 select PCI_DOMAINS_GENERIC if PCI
228 select PCI_ECAM if (ACPI && PCI)
229 select PCI_SYSCALL if PCI
234 select SYSCTL_EXCEPTION_TRACE
235 select THREAD_INFO_IN_TASK
236 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
237 select TRACE_IRQFLAGS_SUPPORT
238 select TRACE_IRQFLAGS_NMI_SUPPORT
239 select HAVE_SOFTIRQ_ON_OWN_STACK
241 ARM 64-bit (AArch64) Linux support.
243 config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
245 # https://github.com/ClangBuiltLinux/linux/issues/1507
246 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
247 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
249 config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
251 depends on $(cc-option,-fpatchable-function-entry=2)
252 select HAVE_DYNAMIC_FTRACE_WITH_ARGS
260 config ARM64_PAGE_SHIFT
262 default 16 if ARM64_64K_PAGES
263 default 14 if ARM64_16K_PAGES
266 config ARM64_CONT_PTE_SHIFT
268 default 5 if ARM64_64K_PAGES
269 default 7 if ARM64_16K_PAGES
272 config ARM64_CONT_PMD_SHIFT
274 default 5 if ARM64_64K_PAGES
275 default 5 if ARM64_16K_PAGES
278 config ARCH_MMAP_RND_BITS_MIN
279 default 14 if ARM64_64K_PAGES
280 default 16 if ARM64_16K_PAGES
283 # max bits determined by the following formula:
284 # VA_BITS - PAGE_SHIFT - 3
285 config ARCH_MMAP_RND_BITS_MAX
286 default 19 if ARM64_VA_BITS=36
287 default 24 if ARM64_VA_BITS=39
288 default 27 if ARM64_VA_BITS=42
289 default 30 if ARM64_VA_BITS=47
290 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
291 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
292 default 33 if ARM64_VA_BITS=48
293 default 14 if ARM64_64K_PAGES
294 default 16 if ARM64_16K_PAGES
297 config ARCH_MMAP_RND_COMPAT_BITS_MIN
298 default 7 if ARM64_64K_PAGES
299 default 9 if ARM64_16K_PAGES
302 config ARCH_MMAP_RND_COMPAT_BITS_MAX
308 config STACKTRACE_SUPPORT
311 config ILLEGAL_POINTER_VALUE
313 default 0xdead000000000000
315 config LOCKDEP_SUPPORT
322 config GENERIC_BUG_RELATIVE_POINTERS
324 depends on GENERIC_BUG
326 config GENERIC_HWEIGHT
332 config GENERIC_CALIBRATE_DELAY
335 config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
341 config KERNEL_MODE_NEON
344 config FIX_EARLYCON_MEM
347 config PGTABLE_LEVELS
349 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
350 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
351 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
352 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
353 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
354 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
356 config ARCH_SUPPORTS_UPROBES
359 config ARCH_PROC_KCORE_TEXT
362 config BROKEN_GAS_INST
363 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
365 config KASAN_SHADOW_OFFSET
367 depends on KASAN_GENERIC || KASAN_SW_TAGS
368 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS
369 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS
370 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
371 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
372 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
373 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS
374 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS
375 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
376 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
377 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
378 default 0xffffffffffffffff
383 source "arch/arm64/Kconfig.platforms"
385 menu "Kernel Features"
387 menu "ARM errata workarounds via the alternatives framework"
389 config ARM64_WORKAROUND_CLEAN_CACHE
392 config ARM64_ERRATUM_826319
393 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
395 select ARM64_WORKAROUND_CLEAN_CACHE
397 This option adds an alternative code sequence to work around ARM
398 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
399 AXI master interface and an L2 cache.
401 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
402 and is unable to accept a certain write via this interface, it will
403 not progress on read data presented on the read data channel and the
406 The workaround promotes data cache clean instructions to
407 data cache clean-and-invalidate.
408 Please note that this does not necessarily enable the workaround,
409 as it depends on the alternative framework, which will only patch
410 the kernel if an affected CPU is detected.
414 config ARM64_ERRATUM_827319
415 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
417 select ARM64_WORKAROUND_CLEAN_CACHE
419 This option adds an alternative code sequence to work around ARM
420 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
421 master interface and an L2 cache.
423 Under certain conditions this erratum can cause a clean line eviction
424 to occur at the same time as another transaction to the same address
425 on the AMBA 5 CHI interface, which can cause data corruption if the
426 interconnect reorders the two transactions.
428 The workaround promotes data cache clean instructions to
429 data cache clean-and-invalidate.
430 Please note that this does not necessarily enable the workaround,
431 as it depends on the alternative framework, which will only patch
432 the kernel if an affected CPU is detected.
436 config ARM64_ERRATUM_824069
437 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
439 select ARM64_WORKAROUND_CLEAN_CACHE
441 This option adds an alternative code sequence to work around ARM
442 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
443 to a coherent interconnect.
445 If a Cortex-A53 processor is executing a store or prefetch for
446 write instruction at the same time as a processor in another
447 cluster is executing a cache maintenance operation to the same
448 address, then this erratum might cause a clean cache line to be
449 incorrectly marked as dirty.
451 The workaround promotes data cache clean instructions to
452 data cache clean-and-invalidate.
453 Please note that this option does not necessarily enable the
454 workaround, as it depends on the alternative framework, which will
455 only patch the kernel if an affected CPU is detected.
459 config ARM64_ERRATUM_819472
460 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
462 select ARM64_WORKAROUND_CLEAN_CACHE
464 This option adds an alternative code sequence to work around ARM
465 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
466 present when it is connected to a coherent interconnect.
468 If the processor is executing a load and store exclusive sequence at
469 the same time as a processor in another cluster is executing a cache
470 maintenance operation to the same address, then this erratum might
471 cause data corruption.
473 The workaround promotes data cache clean instructions to
474 data cache clean-and-invalidate.
475 Please note that this does not necessarily enable the workaround,
476 as it depends on the alternative framework, which will only patch
477 the kernel if an affected CPU is detected.
481 config ARM64_ERRATUM_832075
482 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
485 This option adds an alternative code sequence to work around ARM
486 erratum 832075 on Cortex-A57 parts up to r1p2.
488 Affected Cortex-A57 parts might deadlock when exclusive load/store
489 instructions to Write-Back memory are mixed with Device loads.
491 The workaround is to promote device loads to use Load-Acquire
493 Please note that this does not necessarily enable the workaround,
494 as it depends on the alternative framework, which will only patch
495 the kernel if an affected CPU is detected.
499 config ARM64_ERRATUM_834220
500 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
504 This option adds an alternative code sequence to work around ARM
505 erratum 834220 on Cortex-A57 parts up to r1p2.
507 Affected Cortex-A57 parts might report a Stage 2 translation
508 fault as the result of a Stage 1 fault for load crossing a
509 page boundary when there is a permission or device memory
510 alignment fault at Stage 1 and a translation fault at Stage 2.
512 The workaround is to verify that the Stage 1 translation
513 doesn't generate a fault before handling the Stage 2 fault.
514 Please note that this does not necessarily enable the workaround,
515 as it depends on the alternative framework, which will only patch
516 the kernel if an affected CPU is detected.
520 config ARM64_ERRATUM_1742098
521 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
525 This option removes the AES hwcap for aarch32 user-space to
526 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
528 Affected parts may corrupt the AES state if an interrupt is
529 taken between a pair of AES instructions. These instructions
530 are only present if the cryptography extensions are present.
531 All software should have a fallback implementation for CPUs
532 that don't implement the cryptography extensions.
536 config ARM64_ERRATUM_845719
537 bool "Cortex-A53: 845719: a load might read incorrect data"
541 This option adds an alternative code sequence to work around ARM
542 erratum 845719 on Cortex-A53 parts up to r0p4.
544 When running a compat (AArch32) userspace on an affected Cortex-A53
545 part, a load at EL0 from a virtual address that matches the bottom 32
546 bits of the virtual address used by a recent load at (AArch64) EL1
547 might return incorrect data.
549 The workaround is to write the contextidr_el1 register on exception
550 return to a 32-bit task.
551 Please note that this does not necessarily enable the workaround,
552 as it depends on the alternative framework, which will only patch
553 the kernel if an affected CPU is detected.
557 config ARM64_ERRATUM_843419
558 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
560 select ARM64_MODULE_PLTS if MODULES
562 This option links the kernel with '--fix-cortex-a53-843419' and
563 enables PLT support to replace certain ADRP instructions, which can
564 cause subsequent memory accesses to use an incorrect address on
565 Cortex-A53 parts up to r0p4.
569 config ARM64_LD_HAS_FIX_ERRATUM_843419
570 def_bool $(ld-option,--fix-cortex-a53-843419)
572 config ARM64_ERRATUM_1024718
573 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
576 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
578 Affected Cortex-A55 cores (all revisions) could cause incorrect
579 update of the hardware dirty bit when the DBM/AP bits are updated
580 without a break-before-make. The workaround is to disable the usage
581 of hardware DBM locally on the affected cores. CPUs not affected by
582 this erratum will continue to use the feature.
586 config ARM64_ERRATUM_1418040
587 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
591 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
592 errata 1188873 and 1418040.
594 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
595 cause register corruption when accessing the timer registers
596 from AArch32 userspace.
600 config ARM64_WORKAROUND_SPECULATIVE_AT
603 config ARM64_ERRATUM_1165522
604 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
606 select ARM64_WORKAROUND_SPECULATIVE_AT
608 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
610 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
611 corrupted TLBs by speculating an AT instruction during a guest
616 config ARM64_ERRATUM_1319367
617 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
619 select ARM64_WORKAROUND_SPECULATIVE_AT
621 This option adds work arounds for ARM Cortex-A57 erratum 1319537
622 and A72 erratum 1319367
624 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
625 speculating an AT instruction during a guest context switch.
629 config ARM64_ERRATUM_1530923
630 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
632 select ARM64_WORKAROUND_SPECULATIVE_AT
634 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
636 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
637 corrupted TLBs by speculating an AT instruction during a guest
642 config ARM64_WORKAROUND_REPEAT_TLBI
645 config ARM64_ERRATUM_2441007
646 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
648 select ARM64_WORKAROUND_REPEAT_TLBI
650 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
652 Under very rare circumstances, affected Cortex-A55 CPUs
653 may not handle a race between a break-before-make sequence on one
654 CPU, and another CPU accessing the same page. This could allow a
655 store to a page that has been unmapped.
657 Work around this by adding the affected CPUs to the list that needs
658 TLB sequences to be done twice.
662 config ARM64_ERRATUM_1286807
663 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"
665 select ARM64_WORKAROUND_REPEAT_TLBI
667 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
669 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
670 address for a cacheable mapping of a location is being
671 accessed by a core while another core is remapping the virtual
672 address to a new physical page using the recommended
673 break-before-make sequence, then under very rare circumstances
674 TLBI+DSB completes before a read using the translation being
675 invalidated has been observed by other observers. The
676 workaround repeats the TLBI+DSB operation.
678 config ARM64_ERRATUM_1463225
679 bool "Cortex-A76: Software Step might prevent interrupt recognition"
682 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
684 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
685 of a system call instruction (SVC) can prevent recognition of
686 subsequent interrupts when software stepping is disabled in the
687 exception handler of the system call and either kernel debugging
688 is enabled or VHE is in use.
690 Work around the erratum by triggering a dummy step exception
691 when handling a system call from a task that is being stepped
692 in a VHE configuration of the kernel.
696 config ARM64_ERRATUM_1542419
697 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
700 This option adds a workaround for ARM Neoverse-N1 erratum
703 Affected Neoverse-N1 cores could execute a stale instruction when
704 modified by another CPU. The workaround depends on a firmware
707 Workaround the issue by hiding the DIC feature from EL0. This
708 forces user-space to perform cache maintenance.
712 config ARM64_ERRATUM_1508412
713 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
716 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
718 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
719 of a store-exclusive or read of PAR_EL1 and a load with device or
720 non-cacheable memory attributes. The workaround depends on a firmware
723 KVM guests must also have the workaround implemented or they can
726 Work around the issue by inserting DMB SY barriers around PAR_EL1
727 register reads and warning KVM users. The DMB barrier is sufficient
728 to prevent a speculative PAR_EL1 read.
732 config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
735 config ARM64_ERRATUM_2051678
736 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
739 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
740 Affected Cortex-A510 might not respect the ordering rules for
741 hardware update of the page table's dirty bit. The workaround
742 is to not enable the feature on affected CPUs.
746 config ARM64_ERRATUM_2077057
747 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
750 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
751 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
752 expected, but a Pointer Authentication trap is taken instead. The
753 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
754 EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
756 This can only happen when EL2 is stepping EL1.
758 When these conditions occur, the SPSR_EL2 value is unchanged from the
759 previous guest entry, and can be restored from the in-memory copy.
763 config ARM64_ERRATUM_2658417
764 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
767 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
768 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
769 BFMMLA or VMMLA instructions in rare circumstances when a pair of
770 A510 CPUs are using shared neon hardware. As the sharing is not
771 discoverable by the kernel, hide the BF16 HWCAP to indicate that
772 user-space should not be using these instructions.
776 config ARM64_ERRATUM_2119858
777 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
779 depends on CORESIGHT_TRBE
780 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
782 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
784 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
785 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
786 the event of a WRAP event.
788 Work around the issue by always making sure we move the TRBPTR_EL1 by
789 256 bytes before enabling the buffer and filling the first 256 bytes of
790 the buffer with ETM ignore packets upon disabling.
794 config ARM64_ERRATUM_2139208
795 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
797 depends on CORESIGHT_TRBE
798 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
800 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
802 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
803 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
804 the event of a WRAP event.
806 Work around the issue by always making sure we move the TRBPTR_EL1 by
807 256 bytes before enabling the buffer and filling the first 256 bytes of
808 the buffer with ETM ignore packets upon disabling.
812 config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
815 config ARM64_ERRATUM_2054223
816 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
818 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
820 Enable workaround for ARM Cortex-A710 erratum 2054223
822 Affected cores may fail to flush the trace data on a TSB instruction, when
823 the PE is in trace prohibited state. This will cause losing a few bytes
826 Workaround is to issue two TSB consecutively on affected cores.
830 config ARM64_ERRATUM_2067961
831 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
833 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
835 Enable workaround for ARM Neoverse-N2 erratum 2067961
837 Affected cores may fail to flush the trace data on a TSB instruction, when
838 the PE is in trace prohibited state. This will cause losing a few bytes
841 Workaround is to issue two TSB consecutively on affected cores.
845 config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
848 config ARM64_ERRATUM_2253138
849 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
850 depends on CORESIGHT_TRBE
852 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
854 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
856 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
857 for TRBE. Under some conditions, the TRBE might generate a write to the next
858 virtually addressed page following the last page of the TRBE address space
859 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
861 Work around this in the driver by always making sure that there is a
862 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
866 config ARM64_ERRATUM_2224489
867 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
868 depends on CORESIGHT_TRBE
870 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
872 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
874 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
875 for TRBE. Under some conditions, the TRBE might generate a write to the next
876 virtually addressed page following the last page of the TRBE address space
877 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
879 Work around this in the driver by always making sure that there is a
880 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
884 config ARM64_ERRATUM_2441009
885 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"
887 select ARM64_WORKAROUND_REPEAT_TLBI
889 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
891 Under very rare circumstances, affected Cortex-A510 CPUs
892 may not handle a race between a break-before-make sequence on one
893 CPU, and another CPU accessing the same page. This could allow a
894 store to a page that has been unmapped.
896 Work around this by adding the affected CPUs to the list that needs
897 TLB sequences to be done twice.
901 config ARM64_ERRATUM_2064142
902 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
903 depends on CORESIGHT_TRBE
906 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
908 Affected Cortex-A510 core might fail to write into system registers after the
909 TRBE has been disabled. Under some conditions after the TRBE has been disabled
910 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
911 and TRBTRG_EL1 will be ignored and will not be effected.
913 Work around this in the driver by executing TSB CSYNC and DSB after collection
914 is stopped and before performing a system register write to one of the affected
919 config ARM64_ERRATUM_2038923
920 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
921 depends on CORESIGHT_TRBE
924 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
926 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
927 prohibited within the CPU. As a result, the trace buffer or trace buffer state
928 might be corrupted. This happens after TRBE buffer has been enabled by setting
929 TRBLIMITR_EL1.E, followed by just a single context synchronization event before
930 execution changes from a context, in which trace is prohibited to one where it
931 isn't, or vice versa. In these mentioned conditions, the view of whether trace
932 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
933 the trace buffer state might be corrupted.
935 Work around this in the driver by preventing an inconsistent view of whether the
936 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
937 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
938 two ISB instructions if no ERET is to take place.
942 config ARM64_ERRATUM_1902691
943 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
944 depends on CORESIGHT_TRBE
947 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
949 Affected Cortex-A510 core might cause trace data corruption, when being written
950 into the memory. Effectively TRBE is broken and hence cannot be used to capture
953 Work around this problem in the driver by just preventing TRBE initialization on
954 affected cpus. The firmware must have disabled the access to TRBE for the kernel
955 on such implementations. This will cover the kernel for any firmware that doesn't
960 config ARM64_ERRATUM_2457168
961 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
962 depends on ARM64_AMU_EXTN
965 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
967 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
968 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
969 incorrectly giving a significantly higher output value.
971 Work around this problem by returning 0 when reading the affected counter in
972 key locations that results in disabling all users of this counter. This effect
973 is the same to firmware disabling affected counters.
977 config ARM64_ERRATUM_2645198
978 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
981 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
983 If a Cortex-A715 cpu sees a page mapping permissions change from executable
984 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
985 next instruction abort caused by permission fault.
987 Only user-space does executable to non-executable permission transition via
988 mprotect() system call. Workaround the problem by doing a break-before-make
989 TLB invalidation, for all changes to executable user space mappings.
993 config CAVIUM_ERRATUM_22375
994 bool "Cavium erratum 22375, 24313"
997 Enable workaround for errata 22375 and 24313.
999 This implements two gicv3-its errata workarounds for ThunderX. Both
1000 with a small impact affecting only ITS table allocation.
1002 erratum 22375: only alloc 8MB table size
1003 erratum 24313: ignore memory access type
1005 The fixes are in ITS initialization and basically ignore memory access
1006 type and table size provided by the TYPER and BASER registers.
1010 config CAVIUM_ERRATUM_23144
1011 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1015 ITS SYNC command hang for cross node io and collections/cpu mapping.
1019 config CAVIUM_ERRATUM_23154
1020 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1023 The ThunderX GICv3 implementation requires a modified version for
1024 reading the IAR status to ensure data synchronization
1025 (access to icc_iar1_el1 is not sync'ed before and after).
1027 It also suffers from erratum 38545 (also present on Marvell's
1028 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1029 spuriously presented to the CPU interface.
1033 config CAVIUM_ERRATUM_27456
1034 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1037 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1038 instructions may cause the icache to become corrupted if it
1039 contains data for a non-current ASID. The fix is to
1040 invalidate the icache when changing the mm context.
1044 config CAVIUM_ERRATUM_30115
1045 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1048 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1049 1.2, and T83 Pass 1.0, KVM guest execution may disable
1050 interrupts in host. Trapping both GICv3 group-0 and group-1
1051 accesses sidesteps the issue.
1055 config CAVIUM_TX2_ERRATUM_219
1056 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1059 On Cavium ThunderX2, a load, store or prefetch instruction between a
1060 TTBR update and the corresponding context synchronizing operation can
1061 cause a spurious Data Abort to be delivered to any hardware thread in
1064 Work around the issue by avoiding the problematic code sequence and
1065 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1066 trap handler performs the corresponding register access, skips the
1067 instruction and ensures context synchronization by virtue of the
1072 config FUJITSU_ERRATUM_010001
1073 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1076 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1077 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1078 accesses may cause undefined fault (Data abort, DFSC=0b111111).
1079 This fault occurs under a specific hardware condition when a
1080 load/store instruction performs an address translation using:
1081 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1082 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1083 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1084 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1086 The workaround is to ensure these bits are clear in TCR_ELx.
1087 The workaround only affects the Fujitsu-A64FX.
1091 config HISILICON_ERRATUM_161600802
1092 bool "Hip07 161600802: Erroneous redistributor VLPI base"
1095 The HiSilicon Hip07 SoC uses the wrong redistributor base
1096 when issued ITS commands such as VMOVP and VMAPP, and requires
1097 a 128kB offset to be applied to the target address in this commands.
1101 config QCOM_FALKOR_ERRATUM_1003
1102 bool "Falkor E1003: Incorrect translation due to ASID change"
1105 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1106 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1107 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1108 then only for entries in the walk cache, since the leaf translation
1109 is unchanged. Work around the erratum by invalidating the walk cache
1110 entries for the trampoline before entering the kernel proper.
1112 config QCOM_FALKOR_ERRATUM_1009
1113 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1115 select ARM64_WORKAROUND_REPEAT_TLBI
1117 On Falkor v1, the CPU may prematurely complete a DSB following a
1118 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1119 one more time to fix the issue.
1123 config QCOM_QDF2400_ERRATUM_0065
1124 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1127 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1128 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1129 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1133 config QCOM_FALKOR_ERRATUM_E1041
1134 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1137 Falkor CPU may speculatively fetch instructions from an improper
1138 memory location when MMU translation is changed from SCTLR_ELn[M]=1
1139 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1143 config NVIDIA_CARMEL_CNP_ERRATUM
1144 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1147 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1148 invalidate shared TLB entries installed by a different core, as it would
1149 on standard ARM cores.
1153 config SOCIONEXT_SYNQUACER_PREITS
1154 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1157 Socionext Synquacer SoCs implement a separate h/w block to generate
1158 MSI doorbell writes with non-zero values for the device ID.
1162 endmenu # "ARM errata workarounds via the alternatives framework"
1166 default ARM64_4K_PAGES
1168 Page size (translation granule) configuration.
1170 config ARM64_4K_PAGES
1173 This feature enables 4KB pages support.
1175 config ARM64_16K_PAGES
1178 The system will use 16KB pages support. AArch32 emulation
1179 requires applications compiled with 16K (or a multiple of 16K)
1182 config ARM64_64K_PAGES
1185 This feature enables 64KB pages support (4KB by default)
1186 allowing only two levels of page tables and faster TLB
1187 look-up. AArch32 emulation requires applications compiled
1188 with 64K aligned segments.
1193 prompt "Virtual address space size"
1194 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
1195 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
1196 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
1198 Allows choosing one of multiple possible virtual address
1199 space sizes. The level of translation table is determined by
1200 a combination of page size and virtual address space size.
1202 config ARM64_VA_BITS_36
1203 bool "36-bit" if EXPERT
1204 depends on ARM64_16K_PAGES
1206 config ARM64_VA_BITS_39
1208 depends on ARM64_4K_PAGES
1210 config ARM64_VA_BITS_42
1212 depends on ARM64_64K_PAGES
1214 config ARM64_VA_BITS_47
1216 depends on ARM64_16K_PAGES
1218 config ARM64_VA_BITS_48
1221 config ARM64_VA_BITS_52
1223 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN)
1225 Enable 52-bit virtual addressing for userspace when explicitly
1226 requested via a hint to mmap(). The kernel will also use 52-bit
1227 virtual addresses for its own mappings (provided HW support for
1228 this feature is available, otherwise it reverts to 48-bit).
1230 NOTE: Enabling 52-bit virtual addressing in conjunction with
1231 ARMv8.3 Pointer Authentication will result in the PAC being
1232 reduced from 7 bits to 3 bits, which may have a significant
1233 impact on its susceptibility to brute-force attacks.
1235 If unsure, select 48-bit virtual addressing instead.
1239 config ARM64_FORCE_52BIT
1240 bool "Force 52-bit virtual addresses for userspace"
1241 depends on ARM64_VA_BITS_52 && EXPERT
1243 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1244 to maintain compatibility with older software by providing 48-bit VAs
1245 unless a hint is supplied to mmap.
1247 This configuration option disables the 48-bit compatibility logic, and
1248 forces all userspace addresses to be 52-bit on HW that supports it. One
1249 should only enable this configuration option for stress testing userspace
1250 memory management code. If unsure say N here.
1252 config ARM64_VA_BITS
1254 default 36 if ARM64_VA_BITS_36
1255 default 39 if ARM64_VA_BITS_39
1256 default 42 if ARM64_VA_BITS_42
1257 default 47 if ARM64_VA_BITS_47
1258 default 48 if ARM64_VA_BITS_48
1259 default 52 if ARM64_VA_BITS_52
1262 prompt "Physical address space size"
1263 default ARM64_PA_BITS_48
1265 Choose the maximum physical address range that the kernel will
1268 config ARM64_PA_BITS_48
1271 config ARM64_PA_BITS_52
1272 bool "52-bit (ARMv8.2)"
1273 depends on ARM64_64K_PAGES
1274 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1276 Enable support for a 52-bit physical address space, introduced as
1277 part of the ARMv8.2-LPA extension.
1279 With this enabled, the kernel will also continue to work on CPUs that
1280 do not support ARMv8.2-LPA, but with some added memory overhead (and
1281 minor performance overhead).
1285 config ARM64_PA_BITS
1287 default 48 if ARM64_PA_BITS_48
1288 default 52 if ARM64_PA_BITS_52
1292 default CPU_LITTLE_ENDIAN
1294 Select the endianness of data accesses performed by the CPU. Userspace
1295 applications will need to be compiled and linked for the endianness
1296 that is selected here.
1298 config CPU_BIG_ENDIAN
1299 bool "Build big-endian kernel"
1300 depends on !LD_IS_LLD || LLD_VERSION >= 130000
1302 Say Y if you plan on running a kernel with a big-endian userspace.
1304 config CPU_LITTLE_ENDIAN
1305 bool "Build little-endian kernel"
1307 Say Y if you plan on running a kernel with a little-endian userspace.
1308 This is usually the case for distributions targeting arm64.
1313 bool "Multi-core scheduler support"
1315 Multi-core scheduler support improves the CPU scheduler's decision
1316 making when dealing with multi-core CPU chips at a cost of slightly
1317 increased overhead in some places. If unsure say N here.
1319 config SCHED_CLUSTER
1320 bool "Cluster scheduler support"
1322 Cluster scheduler support improves the CPU scheduler's decision
1323 making when dealing with machines that have clusters of CPUs.
1324 Cluster usually means a couple of CPUs which are placed closely
1325 by sharing mid-level caches, last-level cache tags or internal
1329 bool "SMT scheduler support"
1331 Improves the CPU scheduler's decision making when dealing with
1332 MultiThreading at a cost of slightly increased overhead in some
1333 places. If unsure say N here.
1336 int "Maximum number of CPUs (2-4096)"
1341 bool "Support for hot-pluggable CPUs"
1342 select GENERIC_IRQ_MIGRATION
1344 Say Y here to experiment with turning CPUs off and on. CPUs
1345 can be controlled through /sys/devices/system/cpu.
1347 # Common NUMA Features
1349 bool "NUMA Memory Allocation and Scheduler Support"
1350 select GENERIC_ARCH_NUMA
1351 select ACPI_NUMA if ACPI
1353 select HAVE_SETUP_PER_CPU_AREA
1354 select NEED_PER_CPU_EMBED_FIRST_CHUNK
1355 select NEED_PER_CPU_PAGE_FIRST_CHUNK
1356 select USE_PERCPU_NUMA_NODE_ID
1358 Enable NUMA (Non-Uniform Memory Access) support.
1360 The kernel will try to allocate memory used by a CPU on the
1361 local memory of the CPU and add some more
1362 NUMA awareness to the kernel.
1365 int "Maximum NUMA Nodes (as a power of 2)"
1370 Specify the maximum number of NUMA Nodes available on the target
1371 system. Increases memory reserved to accommodate various tables.
1373 source "kernel/Kconfig.hz"
1375 config ARCH_SPARSEMEM_ENABLE
1377 select SPARSEMEM_VMEMMAP_ENABLE
1378 select SPARSEMEM_VMEMMAP
1380 config HW_PERF_EVENTS
1384 # Supported by clang >= 7.0 or GCC >= 12.0.0
1385 config CC_HAVE_SHADOW_CALL_STACK
1386 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1389 bool "Enable paravirtualization code"
1391 This changes the kernel so it can modify itself when it is run
1392 under a hypervisor, potentially improving performance significantly
1393 over full virtualization.
1395 config PARAVIRT_TIME_ACCOUNTING
1396 bool "Paravirtual steal time accounting"
1399 Select this option to enable fine granularity task steal time
1400 accounting. Time spent executing other tasks in parallel with
1401 the current vCPU is discounted from the vCPU power. To account for
1402 that, there can be a small performance impact.
1404 If in doubt, say N here.
1407 depends on PM_SLEEP_SMP
1409 bool "kexec system call"
1411 kexec is a system call that implements the ability to shutdown your
1412 current kernel, and to start another kernel. It is like a reboot
1413 but it is independent of the system firmware. And like a reboot
1414 you can start any kernel with it, not just Linux.
1417 bool "kexec file based system call"
1419 select HAVE_IMA_KEXEC if IMA
1421 This is new version of kexec system call. This system call is
1422 file based and takes file descriptors as system call argument
1423 for kernel and initramfs as opposed to list of segments as
1424 accepted by previous system call.
1427 bool "Verify kernel signature during kexec_file_load() syscall"
1428 depends on KEXEC_FILE
1430 Select this option to verify a signature with loaded kernel
1431 image. If configured, any attempt of loading a image without
1432 valid signature will fail.
1434 In addition to that option, you need to enable signature
1435 verification for the corresponding kernel image type being
1436 loaded in order for this to work.
1438 config KEXEC_IMAGE_VERIFY_SIG
1439 bool "Enable Image signature verification support"
1441 depends on KEXEC_SIG
1442 depends on EFI && SIGNED_PE_FILE_VERIFICATION
1444 Enable Image signature verification support.
1446 comment "Support for PE file signature verification disabled"
1447 depends on KEXEC_SIG
1448 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION
1451 bool "Build kdump crash kernel"
1453 Generate crash dump after being started by kexec. This should
1454 be normally only set in special crash dump kernels which are
1455 loaded in the main kernel with kexec-tools into a specially
1456 reserved region and then later executed after a crash by
1459 For more details see Documentation/admin-guide/kdump/kdump.rst
1463 depends on HIBERNATION || KEXEC_CORE
1470 bool "Xen guest support on ARM64"
1471 depends on ARM64 && OF
1475 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1477 # include/linux/mmzone.h requires the following to be true:
1479 # MAX_ORDER - 1 + PAGE_SHIFT <= SECTION_SIZE_BITS
1481 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS + 1 - PAGE_SHIFT:
1483 # | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER |
1484 # ----+-------------------+--------------+-----------------+--------------------+
1485 # 4K | 27 | 12 | 16 | 11 |
1486 # 16K | 27 | 14 | 14 | 12 |
1487 # 64K | 29 | 16 | 14 | 14 |
1488 config ARCH_FORCE_MAX_ORDER
1489 int "Maximum zone order" if ARM64_4K_PAGES || ARM64_16K_PAGES
1490 default "14" if ARM64_64K_PAGES
1491 range 12 14 if ARM64_16K_PAGES
1492 default "12" if ARM64_16K_PAGES
1493 range 11 16 if ARM64_4K_PAGES
1496 The kernel memory allocator divides physically contiguous memory
1497 blocks into "zones", where each zone is a power of two number of
1498 pages. This option selects the largest power of two that the kernel
1499 keeps in the memory allocator. If you need to allocate very large
1500 blocks of physically contiguous memory, then you may need to
1501 increase this value.
1503 This config option is actually maximum order plus one. For example,
1504 a value of 11 means that the largest free memory block is 2^10 pages.
1506 We make sure that we can allocate up to a HugePage size for each configuration.
1508 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
1510 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
1511 4M allocations matching the default size used by generic code.
1513 config UNMAP_KERNEL_AT_EL0
1514 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1517 Speculation attacks against some high-performance processors can
1518 be used to bypass MMU permission checks and leak kernel data to
1519 userspace. This can be defended against by unmapping the kernel
1520 when running in userspace, mapping it back in on exception entry
1521 via a trampoline page in the vector table.
1525 config MITIGATE_SPECTRE_BRANCH_HISTORY
1526 bool "Mitigate Spectre style attacks against branch history" if EXPERT
1529 Speculation attacks against some high-performance processors can
1530 make use of branch history to influence future speculation.
1531 When taking an exception from user-space, a sequence of branches
1532 or a firmware call overwrites the branch history.
1534 config RODATA_FULL_DEFAULT_ENABLED
1535 bool "Apply r/o permissions of VM areas also to their linear aliases"
1538 Apply read-only attributes of VM areas to the linear alias of
1539 the backing pages as well. This prevents code or read-only data
1540 from being modified (inadvertently or intentionally) via another
1541 mapping of the same memory page. This additional enhancement can
1542 be turned off at runtime by passing rodata=[off|on] (and turned on
1543 with rodata=full if this option is set to 'n')
1545 This requires the linear region to be mapped down to pages,
1546 which may adversely affect performance in some cases.
1548 config ARM64_SW_TTBR0_PAN
1549 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1551 Enabling this option prevents the kernel from accessing
1552 user-space memory directly by pointing TTBR0_EL1 to a reserved
1553 zeroed area and reserved ASID. The user access routines
1554 restore the valid TTBR0_EL1 temporarily.
1556 config ARM64_TAGGED_ADDR_ABI
1557 bool "Enable the tagged user addresses syscall ABI"
1560 When this option is enabled, user applications can opt in to a
1561 relaxed ABI via prctl() allowing tagged addresses to be passed
1562 to system calls as pointer arguments. For details, see
1563 Documentation/arm64/tagged-address-abi.rst.
1566 bool "Kernel support for 32-bit EL0"
1567 depends on ARM64_4K_PAGES || EXPERT
1569 select OLD_SIGSUSPEND3
1570 select COMPAT_OLD_SIGACTION
1572 This option enables support for a 32-bit EL0 running under a 64-bit
1573 kernel at EL1. AArch32-specific components such as system calls,
1574 the user helper functions, VFP support and the ptrace interface are
1575 handled appropriately by the kernel.
1577 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1578 that you will only be able to execute AArch32 binaries that were compiled
1579 with page size aligned segments.
1581 If you want to execute 32-bit userspace applications, say Y.
1585 config KUSER_HELPERS
1586 bool "Enable kuser helpers page for 32-bit applications"
1589 Warning: disabling this option may break 32-bit user programs.
1591 Provide kuser helpers to compat tasks. The kernel provides
1592 helper code to userspace in read only form at a fixed location
1593 to allow userspace to be independent of the CPU type fitted to
1594 the system. This permits binaries to be run on ARMv4 through
1595 to ARMv8 without modification.
1597 See Documentation/arm/kernel_user_helpers.rst for details.
1599 However, the fixed address nature of these helpers can be used
1600 by ROP (return orientated programming) authors when creating
1603 If all of the binaries and libraries which run on your platform
1604 are built specifically for your platform, and make no use of
1605 these helpers, then you can turn this option off to hinder
1606 such exploits. However, in that case, if a binary or library
1607 relying on those helpers is run, it will not function correctly.
1609 Say N here only if you are absolutely certain that you do not
1610 need these helpers; otherwise, the safe option is to say Y.
1613 bool "Enable vDSO for 32-bit applications"
1614 depends on !CPU_BIG_ENDIAN
1615 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1616 select GENERIC_COMPAT_VDSO
1619 Place in the process address space of 32-bit applications an
1620 ELF shared object providing fast implementations of gettimeofday
1623 You must have a 32-bit build of glibc 2.22 or later for programs
1624 to seamlessly take advantage of this.
1626 config THUMB2_COMPAT_VDSO
1627 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1628 depends on COMPAT_VDSO
1631 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1632 otherwise with '-marm'.
1634 config COMPAT_ALIGNMENT_FIXUPS
1635 bool "Fix up misaligned multi-word loads and stores in user space"
1637 menuconfig ARMV8_DEPRECATED
1638 bool "Emulate deprecated/obsolete ARMv8 instructions"
1641 Legacy software support may require certain instructions
1642 that have been deprecated or obsoleted in the architecture.
1644 Enable this config to enable selective emulation of these
1651 config SWP_EMULATION
1652 bool "Emulate SWP/SWPB instructions"
1654 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1655 they are always undefined. Say Y here to enable software
1656 emulation of these instructions for userspace using LDXR/STXR.
1657 This feature can be controlled at runtime with the abi.swp
1658 sysctl which is disabled by default.
1660 In some older versions of glibc [<=2.8] SWP is used during futex
1661 trylock() operations with the assumption that the code will not
1662 be preempted. This invalid assumption may be more likely to fail
1663 with SWP emulation enabled, leading to deadlock of the user
1666 NOTE: when accessing uncached shared regions, LDXR/STXR rely
1667 on an external transaction monitoring block called a global
1668 monitor to maintain update atomicity. If your system does not
1669 implement a global monitor, this option can cause programs that
1670 perform SWP operations to uncached memory to deadlock.
1674 config CP15_BARRIER_EMULATION
1675 bool "Emulate CP15 Barrier instructions"
1677 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1678 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1679 strongly recommended to use the ISB, DSB, and DMB
1680 instructions instead.
1682 Say Y here to enable software emulation of these
1683 instructions for AArch32 userspace code. When this option is
1684 enabled, CP15 barrier usage is traced which can help
1685 identify software that needs updating. This feature can be
1686 controlled at runtime with the abi.cp15_barrier sysctl.
1690 config SETEND_EMULATION
1691 bool "Emulate SETEND instruction"
1693 The SETEND instruction alters the data-endianness of the
1694 AArch32 EL0, and is deprecated in ARMv8.
1696 Say Y here to enable software emulation of the instruction
1697 for AArch32 userspace code. This feature can be controlled
1698 at runtime with the abi.setend sysctl.
1700 Note: All the cpus on the system must have mixed endian support at EL0
1701 for this feature to be enabled. If a new CPU - which doesn't support mixed
1702 endian - is hotplugged in after this feature has been enabled, there could
1703 be unexpected results in the applications.
1706 endif # ARMV8_DEPRECATED
1710 menu "ARMv8.1 architectural features"
1712 config ARM64_HW_AFDBM
1713 bool "Support for hardware updates of the Access and Dirty page flags"
1716 The ARMv8.1 architecture extensions introduce support for
1717 hardware updates of the access and dirty information in page
1718 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1719 capable processors, accesses to pages with PTE_AF cleared will
1720 set this bit instead of raising an access flag fault.
1721 Similarly, writes to read-only pages with the DBM bit set will
1722 clear the read-only bit (AP[2]) instead of raising a
1725 Kernels built with this configuration option enabled continue
1726 to work on pre-ARMv8.1 hardware and the performance impact is
1727 minimal. If unsure, say Y.
1730 bool "Enable support for Privileged Access Never (PAN)"
1733 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1734 prevents the kernel or hypervisor from accessing user-space (EL0)
1737 Choosing this option will cause any unprotected (not using
1738 copy_to_user et al) memory access to fail with a permission fault.
1740 The feature is detected at runtime, and will remain as a 'nop'
1741 instruction if the cpu does not implement the feature.
1744 def_bool $(as-instr,.arch_extension rcpc)
1746 config AS_HAS_LSE_ATOMICS
1747 def_bool $(as-instr,.arch_extension lse)
1749 config ARM64_LSE_ATOMICS
1751 default ARM64_USE_LSE_ATOMICS
1752 depends on AS_HAS_LSE_ATOMICS
1754 config ARM64_USE_LSE_ATOMICS
1755 bool "Atomic instructions"
1758 As part of the Large System Extensions, ARMv8.1 introduces new
1759 atomic instructions that are designed specifically to scale in
1762 Say Y here to make use of these instructions for the in-kernel
1763 atomic routines. This incurs a small overhead on CPUs that do
1764 not support these instructions and requires the kernel to be
1765 built with binutils >= 2.25 in order for the new instructions
1768 endmenu # "ARMv8.1 architectural features"
1770 menu "ARMv8.2 architectural features"
1772 config AS_HAS_ARMV8_2
1773 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1776 def_bool $(as-instr,.arch armv8.2-a+sha3)
1779 bool "Enable support for persistent memory"
1780 select ARCH_HAS_PMEM_API
1781 select ARCH_HAS_UACCESS_FLUSHCACHE
1783 Say Y to enable support for the persistent memory API based on the
1784 ARMv8.2 DCPoP feature.
1786 The feature is detected at runtime, and the kernel will use DC CVAC
1787 operations if DC CVAP is not supported (following the behaviour of
1788 DC CVAP itself if the system does not define a point of persistence).
1790 config ARM64_RAS_EXTN
1791 bool "Enable support for RAS CPU Extensions"
1794 CPUs that support the Reliability, Availability and Serviceability
1795 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1796 errors, classify them and report them to software.
1798 On CPUs with these extensions system software can use additional
1799 barriers to determine if faults are pending and read the
1800 classification from a new set of registers.
1802 Selecting this feature will allow the kernel to use these barriers
1803 and access the new registers if the system supports the extension.
1804 Platform RAS features may additionally depend on firmware support.
1807 bool "Enable support for Common Not Private (CNP) translations"
1809 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1811 Common Not Private (CNP) allows translation table entries to
1812 be shared between different PEs in the same inner shareable
1813 domain, so the hardware can use this fact to optimise the
1814 caching of such entries in the TLB.
1816 Selecting this option allows the CNP feature to be detected
1817 at runtime, and does not affect PEs that do not implement
1820 endmenu # "ARMv8.2 architectural features"
1822 menu "ARMv8.3 architectural features"
1824 config ARM64_PTR_AUTH
1825 bool "Enable support for pointer authentication"
1828 Pointer authentication (part of the ARMv8.3 Extensions) provides
1829 instructions for signing and authenticating pointers against secret
1830 keys, which can be used to mitigate Return Oriented Programming (ROP)
1833 This option enables these instructions at EL0 (i.e. for userspace).
1834 Choosing this option will cause the kernel to initialise secret keys
1835 for each process at exec() time, with these keys being
1836 context-switched along with the process.
1838 The feature is detected at runtime. If the feature is not present in
1839 hardware it will not be advertised to userspace/KVM guest nor will it
1842 If the feature is present on the boot CPU but not on a late CPU, then
1843 the late CPU will be parked. Also, if the boot CPU does not have
1844 address auth and the late CPU has then the late CPU will still boot
1845 but with the feature disabled. On such a system, this option should
1848 config ARM64_PTR_AUTH_KERNEL
1849 bool "Use pointer authentication for kernel"
1851 depends on ARM64_PTR_AUTH
1852 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1853 # Modern compilers insert a .note.gnu.property section note for PAC
1854 # which is only understood by binutils starting with version 2.33.1.
1855 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1856 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1857 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1859 If the compiler supports the -mbranch-protection or
1860 -msign-return-address flag (e.g. GCC 7 or later), then this option
1861 will cause the kernel itself to be compiled with return address
1862 protection. In this case, and if the target hardware is known to
1863 support pointer authentication, then CONFIG_STACKPROTECTOR can be
1864 disabled with minimal loss of protection.
1866 This feature works with FUNCTION_GRAPH_TRACER option only if
1867 DYNAMIC_FTRACE_WITH_ARGS is enabled.
1869 config CC_HAS_BRANCH_PROT_PAC_RET
1870 # GCC 9 or later, clang 8 or later
1871 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1873 config CC_HAS_SIGN_RETURN_ADDRESS
1875 def_bool $(cc-option,-msign-return-address=all)
1877 config AS_HAS_ARMV8_3
1878 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1880 config AS_HAS_CFI_NEGATE_RA_STATE
1881 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1883 endmenu # "ARMv8.3 architectural features"
1885 menu "ARMv8.4 architectural features"
1887 config ARM64_AMU_EXTN
1888 bool "Enable support for the Activity Monitors Unit CPU extension"
1891 The activity monitors extension is an optional extension introduced
1892 by the ARMv8.4 CPU architecture. This enables support for version 1
1893 of the activity monitors architecture, AMUv1.
1895 To enable the use of this extension on CPUs that implement it, say Y.
1897 Note that for architectural reasons, firmware _must_ implement AMU
1898 support when running on CPUs that present the activity monitors
1899 extension. The required support is present in:
1900 * Version 1.5 and later of the ARM Trusted Firmware
1902 For kernels that have this configuration enabled but boot with broken
1903 firmware, you may need to say N here until the firmware is fixed.
1904 Otherwise you may experience firmware panics or lockups when
1905 accessing the counter registers. Even if you are not observing these
1906 symptoms, the values returned by the register reads might not
1907 correctly reflect reality. Most commonly, the value read will be 0,
1908 indicating that the counter is not enabled.
1910 config AS_HAS_ARMV8_4
1911 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1913 config ARM64_TLB_RANGE
1914 bool "Enable support for tlbi range feature"
1916 depends on AS_HAS_ARMV8_4
1918 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1919 range of input addresses.
1921 The feature introduces new assembly instructions, and they were
1922 support when binutils >= 2.30.
1924 endmenu # "ARMv8.4 architectural features"
1926 menu "ARMv8.5 architectural features"
1928 config AS_HAS_ARMV8_5
1929 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1932 bool "Branch Target Identification support"
1935 Branch Target Identification (part of the ARMv8.5 Extensions)
1936 provides a mechanism to limit the set of locations to which computed
1937 branch instructions such as BR or BLR can jump.
1939 To make use of BTI on CPUs that support it, say Y.
1941 BTI is intended to provide complementary protection to other control
1942 flow integrity protection mechanisms, such as the Pointer
1943 authentication mechanism provided as part of the ARMv8.3 Extensions.
1944 For this reason, it does not make sense to enable this option without
1945 also enabling support for pointer authentication. Thus, when
1946 enabling this option you should also select ARM64_PTR_AUTH=y.
1948 Userspace binaries must also be specifically compiled to make use of
1949 this mechanism. If you say N here or the hardware does not support
1950 BTI, such binaries can still run, but you get no additional
1951 enforcement of branch destinations.
1953 config ARM64_BTI_KERNEL
1954 bool "Use Branch Target Identification for kernel"
1956 depends on ARM64_BTI
1957 depends on ARM64_PTR_AUTH_KERNEL
1958 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
1959 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
1960 depends on !CC_IS_GCC || GCC_VERSION >= 100100
1961 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
1962 depends on !CC_IS_GCC
1963 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
1964 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
1965 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1967 Build the kernel with Branch Target Identification annotations
1968 and enable enforcement of this for kernel code. When this option
1969 is enabled and the system supports BTI all kernel code including
1970 modular code must have BTI enabled.
1972 config CC_HAS_BRANCH_PROT_PAC_RET_BTI
1973 # GCC 9 or later, clang 8 or later
1974 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
1977 bool "Enable support for E0PD"
1980 E0PD (part of the ARMv8.5 extensions) allows us to ensure
1981 that EL0 accesses made via TTBR1 always fault in constant time,
1982 providing similar benefits to KASLR as those provided by KPTI, but
1983 with lower overhead and without disrupting legitimate access to
1984 kernel memory such as SPE.
1986 This option enables E0PD for TTBR1 where available.
1988 config ARM64_AS_HAS_MTE
1989 # Initial support for MTE went in binutils 2.32.0, checked with
1990 # ".arch armv8.5-a+memtag" below. However, this was incomplete
1991 # as a late addition to the final architecture spec (LDGM/STGM)
1992 # is only supported in the newer 2.32.x and 2.33 binutils
1993 # versions, hence the extra "stgm" instruction check below.
1994 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
1997 bool "Memory Tagging Extension support"
1999 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2000 depends on AS_HAS_ARMV8_5
2001 depends on AS_HAS_LSE_ATOMICS
2002 # Required for tag checking in the uaccess routines
2003 depends on ARM64_PAN
2004 select ARCH_HAS_SUBPAGE_FAULTS
2005 select ARCH_USES_HIGH_VMA_FLAGS
2006 select ARCH_USES_PG_ARCH_X
2008 Memory Tagging (part of the ARMv8.5 Extensions) provides
2009 architectural support for run-time, always-on detection of
2010 various classes of memory error to aid with software debugging
2011 to eliminate vulnerabilities arising from memory-unsafe
2014 This option enables the support for the Memory Tagging
2015 Extension at EL0 (i.e. for userspace).
2017 Selecting this option allows the feature to be detected at
2018 runtime. Any secondary CPU not implementing this feature will
2019 not be allowed a late bring-up.
2021 Userspace binaries that want to use this feature must
2022 explicitly opt in. The mechanism for the userspace is
2025 Documentation/arm64/memory-tagging-extension.rst.
2027 endmenu # "ARMv8.5 architectural features"
2029 menu "ARMv8.7 architectural features"
2032 bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2034 depends on ARM64_PAN
2036 Enhanced Privileged Access Never (EPAN) allows Privileged
2037 Access Never to be used with Execute-only mappings.
2039 The feature is detected at runtime, and will remain disabled
2040 if the cpu does not implement the feature.
2041 endmenu # "ARMv8.7 architectural features"
2044 bool "ARM Scalable Vector Extension support"
2047 The Scalable Vector Extension (SVE) is an extension to the AArch64
2048 execution state which complements and extends the SIMD functionality
2049 of the base architecture to support much larger vectors and to enable
2050 additional vectorisation opportunities.
2052 To enable use of this extension on CPUs that implement it, say Y.
2054 On CPUs that support the SVE2 extensions, this option will enable
2057 Note that for architectural reasons, firmware _must_ implement SVE
2058 support when running on SVE capable hardware. The required support
2061 * version 1.5 and later of the ARM Trusted Firmware
2062 * the AArch64 boot wrapper since commit 5e1261e08abf
2063 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2065 For other firmware implementations, consult the firmware documentation
2068 If you need the kernel to boot on SVE-capable hardware with broken
2069 firmware, you may need to say N here until you get your firmware
2070 fixed. Otherwise, you may experience firmware panics or lockups when
2071 booting the kernel. If unsure and you are not observing these
2072 symptoms, you should assume that it is safe to say Y.
2075 bool "ARM Scalable Matrix Extension support"
2077 depends on ARM64_SVE
2079 The Scalable Matrix Extension (SME) is an extension to the AArch64
2080 execution state which utilises a substantial subset of the SVE
2081 instruction set, together with the addition of new architectural
2082 register state capable of holding two dimensional matrix tiles to
2083 enable various matrix operations.
2085 config ARM64_MODULE_PLTS
2086 bool "Use PLTs to allow module memory to spill over into vmalloc area"
2088 select HAVE_MOD_ARCH_SPECIFIC
2090 Allocate PLTs when loading modules so that jumps and calls whose
2091 targets are too far away for their relative offsets to be encoded
2092 in the instructions themselves can be bounced via veneers in the
2093 module's PLT. This allows modules to be allocated in the generic
2094 vmalloc area after the dedicated module memory area has been
2097 When running with address space randomization (KASLR), the module
2098 region itself may be too far away for ordinary relative jumps and
2099 calls, and so in that case, module PLTs are required and cannot be
2102 Specific errata workaround(s) might also force module PLTs to be
2103 enabled (ARM64_ERRATUM_843419).
2105 config ARM64_PSEUDO_NMI
2106 bool "Support for NMI-like interrupts"
2109 Adds support for mimicking Non-Maskable Interrupts through the use of
2110 GIC interrupt priority. This support requires version 3 or later of
2113 This high priority configuration for interrupts needs to be
2114 explicitly enabled by setting the kernel parameter
2115 "irqchip.gicv3_pseudo_nmi" to 1.
2120 config ARM64_DEBUG_PRIORITY_MASKING
2121 bool "Debug interrupt priority masking"
2123 This adds runtime checks to functions enabling/disabling
2124 interrupts when using priority masking. The additional checks verify
2125 the validity of ICC_PMR_EL1 when calling concerned functions.
2128 endif # ARM64_PSEUDO_NMI
2131 bool "Build a relocatable kernel image" if EXPERT
2132 select ARCH_HAS_RELR
2135 This builds the kernel as a Position Independent Executable (PIE),
2136 which retains all relocation metadata required to relocate the
2137 kernel binary at runtime to a different virtual address than the
2138 address it was linked at.
2139 Since AArch64 uses the RELA relocation format, this requires a
2140 relocation pass at runtime even if the kernel is loaded at the
2141 same address it was linked at.
2143 config RANDOMIZE_BASE
2144 bool "Randomize the address of the kernel image"
2145 select ARM64_MODULE_PLTS if MODULES
2148 Randomizes the virtual address at which the kernel image is
2149 loaded, as a security feature that deters exploit attempts
2150 relying on knowledge of the location of kernel internals.
2152 It is the bootloader's job to provide entropy, by passing a
2153 random u64 value in /chosen/kaslr-seed at kernel entry.
2155 When booting via the UEFI stub, it will invoke the firmware's
2156 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2157 to the kernel proper. In addition, it will randomise the physical
2158 location of the kernel Image as well.
2162 config RANDOMIZE_MODULE_REGION_FULL
2163 bool "Randomize the module region over a 2 GB range"
2164 depends on RANDOMIZE_BASE
2167 Randomizes the location of the module region inside a 2 GB window
2168 covering the core kernel. This way, it is less likely for modules
2169 to leak information about the location of core kernel data structures
2170 but it does imply that function calls between modules and the core
2171 kernel will need to be resolved via veneers in the module PLT.
2173 When this option is not set, the module region will be randomized over
2174 a limited range that contains the [_stext, _etext] interval of the
2175 core kernel, so branch relocations are almost always in range unless
2176 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this
2177 particular case of region exhaustion, modules might be able to fall
2178 back to a larger 2GB area.
2180 config CC_HAVE_STACKPROTECTOR_SYSREG
2181 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2183 config STACKPROTECTOR_PER_TASK
2185 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2187 config UNWIND_PATCH_PAC_INTO_SCS
2188 bool "Enable shadow call stack dynamically using code patching"
2189 # needs Clang with https://reviews.llvm.org/D111780 incorporated
2190 depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2191 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2192 depends on SHADOW_CALL_STACK
2193 select UNWIND_TABLES
2196 endmenu # "Kernel Features"
2200 config ARM64_ACPI_PARKING_PROTOCOL
2201 bool "Enable support for the ARM64 ACPI parking protocol"
2204 Enable support for the ARM64 ACPI parking protocol. If disabled
2205 the kernel will not allow booting through the ARM64 ACPI parking
2206 protocol even if the corresponding data is present in the ACPI
2210 string "Default kernel command string"
2213 Provide a set of default command-line options at build time by
2214 entering them here. As a minimum, you should specify the the
2215 root device (e.g. root=/dev/nfs).
2218 prompt "Kernel command line type" if CMDLINE != ""
2219 default CMDLINE_FROM_BOOTLOADER
2221 Choose how the kernel will handle the provided default kernel
2222 command line string.
2224 config CMDLINE_FROM_BOOTLOADER
2225 bool "Use bootloader kernel arguments if available"
2227 Uses the command-line options passed by the boot loader. If
2228 the boot loader doesn't provide any, the default kernel command
2229 string provided in CMDLINE will be used.
2231 config CMDLINE_FORCE
2232 bool "Always use the default kernel command string"
2234 Always use the default kernel command string, even if the boot
2235 loader passes other arguments to the kernel.
2236 This is useful if you cannot or don't want to change the
2237 command-line options your boot loader passes to the kernel.
2245 bool "UEFI runtime support"
2246 depends on OF && !CPU_BIG_ENDIAN
2247 depends on KERNEL_MODE_NEON
2248 select ARCH_SUPPORTS_ACPI
2251 select EFI_PARAMS_FROM_FDT
2252 select EFI_RUNTIME_WRAPPERS
2254 select EFI_GENERIC_STUB
2255 imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2258 This option provides support for runtime services provided
2259 by UEFI firmware (such as non-volatile variables, realtime
2260 clock, and platform reset). A UEFI stub is also provided to
2261 allow the kernel to be booted as an EFI application. This
2262 is only useful on systems that have UEFI firmware.
2265 bool "Enable support for SMBIOS (DMI) tables"
2269 This enables SMBIOS/DMI feature for systems.
2271 This option is only useful on systems that have UEFI firmware.
2272 However, even with this option, the resultant kernel should
2273 continue to boot on existing non-UEFI platforms.
2275 endmenu # "Boot options"
2277 menu "Power management options"
2279 source "kernel/power/Kconfig"
2281 config ARCH_HIBERNATION_POSSIBLE
2285 config ARCH_HIBERNATION_HEADER
2287 depends on HIBERNATION
2289 config ARCH_SUSPEND_POSSIBLE
2292 endmenu # "Power management options"
2294 menu "CPU Power Management"
2296 source "drivers/cpuidle/Kconfig"
2298 source "drivers/cpufreq/Kconfig"
2300 endmenu # "CPU Power Management"
2302 source "drivers/acpi/Kconfig"
2304 source "arch/arm64/kvm/Kconfig"