1 /* arch/arm/plat-samsung/include/plat/regs-fb-v4.h
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
8 * S3C64XX - new-style framebuffer register definitions
10 * This is the register set for the new style framebuffer interface
11 * found from the S3C2443 onwards and specifically the S3C64XX series
12 * S3C6400 and S3C6410.
14 * The file contains the cpu specific items which change between whichever
15 * architecture is selected. See <plat/regs-fb.h> for the core definitions
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
23 /* include the core definitions here, in case we really do need to
24 * override them at a later date.
27 #include <plat/regs-fb.h>
29 #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
30 #define VIDCON1_FSTATUS_EVEN (1 << 15)
32 /* Video timing controls */
33 #define VIDTCON0 (0x10)
34 #define VIDTCON1 (0x14)
35 #define VIDTCON2 (0x18)
37 /* Window position controls */
39 #define WINCON(_win) (0x20 + ((_win) * 4))
41 /* OSD1 and OSD4 do not have register D */
43 #define VIDOSD_A(_win) (0x40 + ((_win) * 16))
44 #define VIDOSD_B(_win) (0x44 + ((_win) * 16))
45 #define VIDOSD_C(_win) (0x48 + ((_win) * 16))
46 #define VIDOSD_D(_win) (0x4C + ((_win) * 16))
49 #define VIDINTCON0 (0x130)
51 #define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4))
55 #define WINCONx_CSCWIDTH_MASK (0x3 << 26)
56 #define WINCONx_CSCWIDTH_SHIFT (26)
57 #define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
58 #define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
60 #define WINCONx_ENLOCAL (1 << 22)
61 #define WINCONx_BUFSTATUS (1 << 21)
62 #define WINCONx_BUFSEL (1 << 20)
63 #define WINCONx_BUFAUTOEN (1 << 19)
64 #define WINCONx_YCbCr (1 << 13)
66 #define WINCON1_LOCALSEL_CAMIF (1 << 23)
68 #define WINCON2_LOCALSEL_CAMIF (1 << 23)
69 #define WINCON2_BLD_PIX (1 << 6)
71 #define WINCON2_ALPHA_SEL (1 << 1)
72 #define WINCON2_BPPMODE_MASK (0xf << 2)
73 #define WINCON2_BPPMODE_SHIFT (2)
74 #define WINCON2_BPPMODE_1BPP (0x0 << 2)
75 #define WINCON2_BPPMODE_2BPP (0x1 << 2)
76 #define WINCON2_BPPMODE_4BPP (0x2 << 2)
77 #define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
78 #define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
79 #define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
80 #define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
81 #define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
82 #define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
83 #define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
84 #define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
85 #define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
86 #define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
87 #define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
89 #define WINCON3_BLD_PIX (1 << 6)
91 #define WINCON3_ALPHA_SEL (1 << 1)
92 #define WINCON3_BPPMODE_MASK (0xf << 2)
93 #define WINCON3_BPPMODE_SHIFT (2)
94 #define WINCON3_BPPMODE_1BPP (0x0 << 2)
95 #define WINCON3_BPPMODE_2BPP (0x1 << 2)
96 #define WINCON3_BPPMODE_4BPP (0x2 << 2)
97 #define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
98 #define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
99 #define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
100 #define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
101 #define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
102 #define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
103 #define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
104 #define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
105 #define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
106 #define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
108 #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
109 #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
110 #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
112 #define DITHMODE (0x170)
113 #define WINxMAP(_win) (0x180 + ((_win) * 4))
116 #define DITHMODE_R_POS_MASK (0x3 << 5)
117 #define DITHMODE_R_POS_SHIFT (5)
118 #define DITHMODE_R_POS_8BIT (0x0 << 5)
119 #define DITHMODE_R_POS_6BIT (0x1 << 5)
120 #define DITHMODE_R_POS_5BIT (0x2 << 5)
122 #define DITHMODE_G_POS_MASK (0x3 << 3)
123 #define DITHMODE_G_POS_SHIFT (3)
124 #define DITHMODE_G_POS_8BIT (0x0 << 3)
125 #define DITHMODE_G_POS_6BIT (0x1 << 3)
126 #define DITHMODE_G_POS_5BIT (0x2 << 3)
128 #define DITHMODE_B_POS_MASK (0x3 << 1)
129 #define DITHMODE_B_POS_SHIFT (1)
130 #define DITHMODE_B_POS_8BIT (0x0 << 1)
131 #define DITHMODE_B_POS_6BIT (0x1 << 1)
132 #define DITHMODE_B_POS_5BIT (0x2 << 1)
134 #define DITHMODE_DITH_EN (1 << 0)
136 #define WPALCON (0x1A0)
138 /* Palette control */
139 /* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
140 * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
141 #define WPALCON_W4PAL_16BPP_A555 (1 << 8)
142 #define WPALCON_W3PAL_16BPP_A555 (1 << 7)
143 #define WPALCON_W2PAL_16BPP_A555 (1 << 6)
146 /* system specific implementation code for palette sizes, and other
147 * information that changes depending on which architecture is being
151 struct s3c_fb_palette {
152 struct fb_bitfield r;
153 struct fb_bitfield g;
154 struct fb_bitfield b;
155 struct fb_bitfield a;
158 static inline void s3c_fb_init_palette(unsigned int window,
159 struct s3c_fb_palette *palette)
162 /* Windows 0/1 are 8/8/8 or A/8/8/8 */
163 palette->r.offset = 16;
164 palette->r.length = 8;
165 palette->g.offset = 8;
166 palette->g.length = 8;
167 palette->b.offset = 0;
168 palette->b.length = 8;
170 /* currently we assume RGB 5/6/5 */
171 palette->r.offset = 11;
172 palette->r.length = 5;
173 palette->g.offset = 5;
174 palette->g.length = 6;
175 palette->b.offset = 0;
176 palette->b.length = 5;
180 /* Notes on per-window bpp settings
182 * Value Win0 Win1 Win2 Win3 Win 4
183 * 0000 1(P) 1(P) 1(P) 1(P) 1(P)
184 * 0001 2(P) 2(P) 2(P) 2(P) 2(P)
185 * 0010 4(P) 4(P) 4(P) 4(P) -none-
186 * 0011 8(P) 8(P) -none- -none- -none-
187 * 0100 -none- 8(A232) 8(A232) -none- -none-
188 * 0101 16(565) 16(565) 16(565) 16(565) 16(565)
189 * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
190 * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
191 * 1000 18(666) 18(666) 18(666) 18(666) 18(666)
192 * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
193 * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
194 * 1011 24(888) 24(888) 24(888) 24(888) 24(888)
195 * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
196 * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
197 * 1110 -none- -none- -none- -none- -none-
198 * 1111 -none- -none- -none- -none- -none-