1 /* arch/arm/mach-s3c2410/include/mach/regs-adc.h
3 * Copyright (c) 2004 Shannon Holland <holland@loser.net>
5 * This program is free software; yosu can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * S3C2410 ADC registers
12 #ifndef __ASM_ARCH_REGS_ADC_H
13 #define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
15 #define S3C2410_ADCREG(x) (x)
17 #define S3C2410_ADCCON S3C2410_ADCREG(0x00)
18 #define S3C2410_ADCTSC S3C2410_ADCREG(0x04)
19 #define S3C2410_ADCDLY S3C2410_ADCREG(0x08)
20 #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C)
21 #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22 #define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
23 #define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
24 #define S5PV210_ADCMUX S3C2410_ADCREG(0x1C)
25 #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
28 /* ADCCON Register Bits */
29 #define S3C64XX_ADCCON_TSSEL (1<<17)
30 #define S3C64XX_ADCCON_RESSEL (1<<16)
31 #define S3C2410_ADCCON_ECFLG (1<<15)
32 #define S3C2410_ADCCON_PRSCEN (1<<14)
33 #define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
34 #define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
35 #define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
36 #define S5PV210_ADCCON_SELMUX(x) (((x)&0xF)<<0)
37 #define S3C2410_ADCCON_MUXMASK (0x7<<3)
38 #define S3C2410_ADCCON_STDBM (1<<2)
39 #define S3C2410_ADCCON_READ_START (1<<1)
40 #define S3C2410_ADCCON_ENABLE_START (1<<0)
41 #define S3C2410_ADCCON_STARTMASK (0x3<<0)
44 /* ADCTSC Register Bits */
45 #define S3C2410_ADCTSC_YM_SEN (1<<7)
46 #define S3C2410_ADCTSC_YP_SEN (1<<6)
47 #define S3C2410_ADCTSC_XM_SEN (1<<5)
48 #define S3C2410_ADCTSC_XP_SEN (1<<4)
49 #define S3C2410_ADCTSC_PULL_UP_DISABLE (1<<3)
50 #define S3C2410_ADCTSC_AUTO_PST (1<<2)
51 #define S3C2410_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
54 #define S3C2410_ADCDAT0_UPDOWN (1<<15)
55 #define S3C2410_ADCDAT0_AUTO_PST (1<<14)
56 #define S3C2410_ADCDAT0_XY_PST (0x3<<12)
57 #define S3C2410_ADCDAT0_XPDATA_MASK (0x03FF)
60 #define S3C2410_ADCDAT1_UPDOWN (1<<15)
61 #define S3C2410_ADCDAT1_AUTO_PST (1<<14)
62 #define S3C2410_ADCDAT1_XY_PST (0x3<<12)
63 #define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
65 /*--------------------------- Common definitions for S3C --------------------
66 The following definitions will be applied to S3C24XX,S3C64XX,S5PC1XX,S5PC2XX.
67 *---------------------------------------------------------------------------*/
68 #define S3C_ADCREG(x) (x)
70 #define S3C_ADCCON S3C_ADCREG(0x00)
71 #define S3C_ADCTSC S3C_ADCREG(0x04)
72 #define S3C_ADCDLY S3C_ADCREG(0x08)
73 #define S3C_ADCDAT0 S3C_ADCREG(0x0C)
74 #define S3C_ADCDAT1 S3C_ADCREG(0x10)
75 #define S3C_ADCUPDN S3C_ADCREG(0x14)
76 #define S3C_ADCCLRINT S3C_ADCREG(0x18)
77 #define S3C_ADCMUX S3C_ADCREG(0x1C)
78 #define S3C_ADCCLRWK S3C_ADCREG(0x20)
81 /* ADCCON Register Bits */
82 #define S3C_ADCCON_RESSEL_10BIT (0x0<<16)
83 #define S3C_ADCCON_RESSEL_12BIT (0x1<<16)
84 #define S3C_ADCCON_ECFLG (1<<15)
85 #define S3C_ADCCON_PRSCEN (1<<14)
86 #define S3C_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
87 #define S3C_ADCCON_PRSCVLMASK (0xFF<<6)
88 #define S3C_ADCCON_SELMUX(x) (((x)&0x7)<<3)
89 #define S3C_ADCCON_SELMUX_1(x) (((x)&0xF)<<0)
90 #define S3C_ADCCON_MUXMASK (0x7<<3)
91 #define S3C_ADCCON_RESSEL_10BIT_1 (0x0<<3)
92 #define S3C_ADCCON_RESSEL_12BIT_1 (0x1<<3)
93 #define S3C_ADCCON_STDBM (1<<2)
94 #define S3C_ADCCON_READ_START (1<<1)
95 #define S3C_ADCCON_ENABLE_START (1<<0)
96 #define S3C_ADCCON_STARTMASK (0x3<<0)
99 /* ADCTSC Register Bits */
100 #define S3C_ADCTSC_UD_SEN (1<<8)
101 #define S3C_ADCTSC_YM_SEN (1<<7)
102 #define S3C_ADCTSC_YP_SEN (1<<6)
103 #define S3C_ADCTSC_XM_SEN (1<<5)
104 #define S3C_ADCTSC_XP_SEN (1<<4)
105 #define S3C_ADCTSC_PULL_UP_DISABLE (1<<3)
106 #define S3C_ADCTSC_AUTO_PST (1<<2)
107 #define S3C_ADCTSC_XY_PST(x) (((x)&0x3)<<0)
110 #define S3C_ADCDAT0_UPDOWN (1<<15)
111 #define S3C_ADCDAT0_AUTO_PST (1<<14)
112 #define S3C_ADCDAT0_XY_PST (0x3<<12)
113 #define S3C_ADCDAT0_XPDATA_MASK (0x03FF)
114 #define S3C_ADCDAT0_XPDATA_MASK_12BIT (0x0FFF)
117 #define S3C_ADCDAT1_UPDOWN (1<<15)
118 #define S3C_ADCDAT1_AUTO_PST (1<<14)
119 #define S3C_ADCDAT1_XY_PST (0x3<<12)
120 #define S3C_ADCDAT1_YPDATA_MASK (0x03FF)
121 #define S3C_ADCDAT1_YPDATA_MASK_12BIT (0x0FFF)
123 #endif /* __ASM_ARCH_REGS_ADC_H */