1 /* linux/arch/arm/plat-s5p/irq-gpioint.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * Author: Kyungmin Park <kyungmin.park@samsung.com>
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <linux/gpio.h>
22 #include <plat/gpio-core.h>
23 #include <plat/gpio-cfg.h>
25 #define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u)
27 #define CON_OFFSET 0x700
28 #define MASK_OFFSET 0x900
29 #define PEND_OFFSET 0xA00
30 #define REG_OFFSET(x) ((x) << 2)
32 static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
34 static int s5p_gpioint_get_offset(struct irq_data *data)
36 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
37 return data->irq - chip->irq_base;
40 static void s5p_gpioint_ack(struct irq_data *data)
42 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
43 int group, offset, pend_offset;
47 offset = s5p_gpioint_get_offset(data);
48 pend_offset = REG_OFFSET(group);
50 value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
52 __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
55 static void s5p_gpioint_mask(struct irq_data *data)
57 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
58 int group, offset, mask_offset;
62 offset = s5p_gpioint_get_offset(data);
63 mask_offset = REG_OFFSET(group);
65 value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
67 __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
70 static void s5p_gpioint_unmask(struct irq_data *data)
72 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
73 int group, offset, mask_offset;
77 offset = s5p_gpioint_get_offset(data);
78 mask_offset = REG_OFFSET(group);
80 value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
81 value &= ~BIT(offset);
82 __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
85 static void s5p_gpioint_mask_ack(struct irq_data *data)
87 s5p_gpioint_mask(data);
88 s5p_gpioint_ack(data);
91 static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
93 struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
94 int group, offset, con_offset;
98 offset = s5p_gpioint_get_offset(data);
99 con_offset = REG_OFFSET(group);
102 case IRQ_TYPE_EDGE_RISING:
103 type = S5P_IRQ_TYPE_EDGE_RISING;
105 case IRQ_TYPE_EDGE_FALLING:
106 type = S5P_IRQ_TYPE_EDGE_FALLING;
108 case IRQ_TYPE_EDGE_BOTH:
109 type = S5P_IRQ_TYPE_EDGE_BOTH;
111 case IRQ_TYPE_LEVEL_HIGH:
112 type = S5P_IRQ_TYPE_LEVEL_HIGH;
114 case IRQ_TYPE_LEVEL_LOW:
115 type = S5P_IRQ_TYPE_LEVEL_LOW;
119 printk(KERN_WARNING "No irq type\n");
123 value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
124 value &= ~(0x7 << (offset * 0x4));
125 value |= (type << (offset * 0x4));
126 __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
131 static struct irq_chip s5p_gpioint = {
132 .name = "s5p_gpioint",
133 .irq_ack = s5p_gpioint_ack,
134 .irq_mask = s5p_gpioint_mask,
135 .irq_mask_ack = s5p_gpioint_mask_ack,
136 .irq_unmask = s5p_gpioint_unmask,
137 .irq_set_type = s5p_gpioint_set_type,
140 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
142 int group, pend_offset, mask_offset;
143 unsigned int pend, mask;
145 for (group = 0; group < S5P_GPIOINT_GROUP_MAXNR; group++) {
146 struct s3c_gpio_chip *chip = irq_chips[group];
150 pend_offset = REG_OFFSET(group);
151 pend = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
155 mask_offset = REG_OFFSET(group);
156 mask = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
160 int offset = fls(pend) - 1;
161 int real_irq = chip->irq_base + offset;
162 generic_handle_irq(real_irq);
163 pend &= ~BIT(offset);
168 static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
170 static int used_gpioint_groups = 0;
171 static bool handler_registered = 0;
172 int irq, group = chip->group;
175 if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
178 chip->irq_base = S5P_GPIOINT_BASE +
179 used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
180 used_gpioint_groups++;
182 if (!handler_registered) {
183 set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
184 handler_registered = 1;
187 irq_chips[group] = chip;
188 for (i = 0; i < chip->chip.ngpio; i++) {
189 irq = chip->irq_base + i;
190 set_irq_chip(irq, &s5p_gpioint);
191 set_irq_data(irq, chip);
192 set_irq_handler(irq, handle_level_irq);
193 set_irq_flags(irq, IRQF_VALID);
198 int __init s5p_register_gpio_interrupt(int pin)
200 struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin);
207 offset = pin - my_chip->chip.base;
208 group = my_chip->group;
210 /* check if the group has been already registered */
211 if (my_chip->irq_base)
212 return my_chip->irq_base + offset;
214 /* register gpio group */
215 ret = s5p_gpioint_add(my_chip);
217 my_chip->chip.to_irq = samsung_gpiolib_to_irq;
218 printk(KERN_INFO "Registered interrupt support for gpio group %d.\n",
220 return my_chip->irq_base + offset;