arch/arm/plat-s3c64xx/clock.c

   1 /* linux/arch/arm/plat-s3c64xx/clock.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX Base clock support
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/ioport.h>
  19 #include <linux/io.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/map.h>
  23
  24 #include <plat/regs-sys.h>
  25 #include <plat/regs-clock.h>
  26 #include <plat/cpu.h>
  27 #include <plat/devs.h>
  28 #include <plat/clock.h>
  29
  30 struct clk clk_27m = {
  31         .name           = "clk_27m",
  32         .id             = -1,
  33         .rate           = 27000000,
  34 };
  35
  36 static int clk_48m_ctrl(struct clk *clk, int enable)
  37 {
  38         unsigned long flags;
  39         u32 val;
  40
  41         /* can't rely on clock lock, this register has other usages */
  42         local_irq_save(flags);
  43
  44         val = __raw_readl(S3C64XX_OTHERS);
  45         if (enable)
  46                 val |= S3C64XX_OTHERS_USBMASK;
  47         else
  48                 val &= ~S3C64XX_OTHERS_USBMASK;
  49
  50         __raw_writel(val, S3C64XX_OTHERS);
  51         local_irq_restore(flags);
  52
  53         return 0;
  54 }
  55
  56 struct clk clk_48m = {
  57         .name           = "clk_48m",
  58         .id             = -1,
  59         .rate           = 48000000,
  60         .enable         = clk_48m_ctrl,
  61 };
  62
  63 static int inline s3c64xx_gate(void __iomem *reg,
  64                                 struct clk *clk,
  65                                 int enable)
  66 {
  67         unsigned int ctrlbit = clk->ctrlbit;
  68         u32 con;
  69
  70         con = __raw_readl(reg);
  71
  72         if (enable)
  73                 con |= ctrlbit;
  74         else
  75                 con &= ~ctrlbit;
  76
  77         __raw_writel(con, reg);
  78         return 0;
  79 }
  80
  81 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
  82 {
  83         return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
  84 }
  85
  86 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
  87 {
  88         return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
  89 }
  90
  91 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
  92 {
  93         return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
  94 }
  95
  96 static struct clk init_clocks_disable[] = {
  97         {
  98                 .name           = "nand",
  99                 .id             = -1,
 100                 .parent         = &clk_h,
 101         }, {
 102                 .name           = "adc",
 103                 .id             = -1,
 104                 .parent         = &clk_p,
 105                 .enable         = s3c64xx_pclk_ctrl,
 106                 .ctrlbit        = S3C_CLKCON_PCLK_TSADC,
 107         }, {
 108                 .name           = "i2c",
 109                 .id             = -1,
 110                 .parent         = &clk_p,
 111                 .enable         = s3c64xx_pclk_ctrl,
 112                 .ctrlbit        = S3C_CLKCON_PCLK_IIC,
 113         }, {
 114                 .name           = "iis",
 115                 .id             = 0,
 116                 .parent         = &clk_p,
 117                 .enable         = s3c64xx_pclk_ctrl,
 118                 .ctrlbit        = S3C_CLKCON_PCLK_IIS0,
 119         }, {
 120                 .name           = "iis",
 121                 .id             = 1,
 122                 .parent         = &clk_p,
 123                 .enable         = s3c64xx_pclk_ctrl,
 124                 .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
 125         }, {
 126                 .name           = "spi",
 127                 .id             = 0,
 128                 .parent         = &clk_p,
 129                 .enable         = s3c64xx_pclk_ctrl,
 130                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
 131         }, {
 132                 .name           = "spi",
 133                 .id             = 1,
 134                 .parent         = &clk_p,
 135                 .enable         = s3c64xx_pclk_ctrl,
 136                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
 137         }, {
 138                 .name           = "48m",
 139                 .id             = 0,
 140                 .parent         = &clk_48m,
 141                 .enable         = s3c64xx_sclk_ctrl,
 142                 .ctrlbit        = S3C_CLKCON_SCLK_MMC0_48,
 143         }, {
 144                 .name           = "48m",
 145                 .id             = 1,
 146                 .parent         = &clk_48m,
 147                 .enable         = s3c64xx_sclk_ctrl,
 148                 .ctrlbit        = S3C_CLKCON_SCLK_MMC1_48,
 149         }, {
 150                 .name           = "48m",
 151                 .id             = 2,
 152                 .parent         = &clk_48m,
 153                 .enable         = s3c64xx_sclk_ctrl,
 154                 .ctrlbit        = S3C_CLKCON_SCLK_MMC2_48,
 155         },
 156 };
 157
 158 static struct clk init_clocks[] = {
 159         {
 160                 .name           = "lcd",
 161                 .id             = -1,
 162                 .parent         = &clk_h,
 163                 .enable         = s3c64xx_hclk_ctrl,
 164                 .ctrlbit        = S3C_CLKCON_HCLK_LCD,
 165         }, {
 166                 .name           = "gpio",
 167                 .id             = -1,
 168                 .parent         = &clk_p,
 169                 .enable         = s3c64xx_pclk_ctrl,
 170                 .ctrlbit        = S3C_CLKCON_PCLK_GPIO,
 171         }, {
 172                 .name           = "usb-host",
 173                 .id             = -1,
 174                 .parent         = &clk_h,
 175                 .enable         = s3c64xx_hclk_ctrl,
 176                 .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
 177         }, {
 178                 .name           = "hsmmc",
 179                 .id             = 0,
 180                 .parent         = &clk_h,
 181                 .enable         = s3c64xx_hclk_ctrl,
 182                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
 183         }, {
 184                 .name           = "hsmmc",
 185                 .id             = 1,
 186                 .parent         = &clk_h,
 187                 .enable         = s3c64xx_hclk_ctrl,
 188                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
 189         }, {
 190                 .name           = "hsmmc",
 191                 .id             = 2,
 192                 .parent         = &clk_h,
 193                 .enable         = s3c64xx_hclk_ctrl,
 194                 .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
 195         }, {
 196                 .name           = "timers",
 197                 .id             = -1,
 198                 .parent         = &clk_p,
 199                 .enable         = s3c64xx_pclk_ctrl,
 200                 .ctrlbit        = S3C_CLKCON_PCLK_PWM,
 201         }, {
 202                 .name           = "uart",
 203                 .id             = 0,
 204                 .parent         = &clk_p,
 205                 .enable         = s3c64xx_pclk_ctrl,
 206                 .ctrlbit        = S3C_CLKCON_PCLK_UART0,
 207         }, {
 208                 .name           = "uart",
 209                 .id             = 1,
 210                 .parent         = &clk_p,
 211                 .enable         = s3c64xx_pclk_ctrl,
 212                 .ctrlbit        = S3C_CLKCON_PCLK_UART1,
 213         }, {
 214                 .name           = "uart",
 215                 .id             = 2,
 216                 .parent         = &clk_p,
 217                 .enable         = s3c64xx_pclk_ctrl,
 218                 .ctrlbit        = S3C_CLKCON_PCLK_UART2,
 219         }, {
 220                 .name           = "uart",
 221                 .id             = 3,
 222                 .parent         = &clk_p,
 223                 .enable         = s3c64xx_pclk_ctrl,
 224                 .ctrlbit        = S3C_CLKCON_PCLK_UART3,
 225         }, {
 226                 .name           = "rtc",
 227                 .id             = -1,
 228                 .parent         = &clk_p,
 229                 .enable         = s3c64xx_pclk_ctrl,
 230                 .ctrlbit        = S3C_CLKCON_PCLK_RTC,
 231         }, {
 232                 .name           = "watchdog",
 233                 .id             = -1,
 234                 .parent         = &clk_p,
 235                 .ctrlbit        = S3C_CLKCON_PCLK_WDT,
 236         }, {
 237                 .name           = "ac97",
 238                 .id             = -1,
 239                 .parent         = &clk_p,
 240                 .ctrlbit        = S3C_CLKCON_PCLK_AC97,
 241         }
 242 };
 243
 244 static struct clk *clks[] __initdata = {
 245         &clk_ext,
 246         &clk_epll,
 247         &clk_27m,
 248         &clk_48m,
 249 };
 250
 251 void __init s3c64xx_register_clocks(void)
 252 {
 253         struct clk *clkp;
 254         int ret;
 255         int ptr;
 256
 257         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 258
 259         clkp = init_clocks;
 260         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
 261                 ret = s3c24xx_register_clock(clkp);
 262                 if (ret < 0) {
 263                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 264                                clkp->name, ret);
 265                 }
 266         }
 267
 268         clkp = init_clocks_disable;
 269         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 270
 271                 ret = s3c24xx_register_clock(clkp);
 272                 if (ret < 0) {
 273                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 274                                clkp->name, ret);
 275                 }
 276
 277                 (clkp->enable)(clkp, 0);
 278         }
 279
 280         s3c_pwmclk_init();
 281 }