2 * linux/arch/arm/plat-omap/sram.c
4 * OMAP SRAM detection and management
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
23 #include <asm/fncpy.h>
25 #include <asm/cacheflush.h>
27 #include <asm/mach/map.h>
29 #include "../mach-omap1/soc.h"
30 #include "../mach-omap1/sram.h"
31 #include "../mach-omap2/soc.h"
32 #include "../mach-omap2/sram.h"
34 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
35 #include "../mach-omap2/iomap.h"
36 #include "../mach-omap2/prm2xxx_3xxx.h"
37 #include "../mach-omap2/sdrc.h"
39 #define OMAP1_SRAM_PA 0x20000000
40 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
41 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
42 #ifdef CONFIG_OMAP4_ERRATA_I688
43 #define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
45 #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
47 #define OMAP5_SRAM_PA 0x40300000
49 #if defined(CONFIG_ARCH_OMAP2PLUS)
50 #define SRAM_BOOTLOADER_SZ 0x00
52 #define SRAM_BOOTLOADER_SZ 0x80
55 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
56 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
57 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
59 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
60 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
61 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
62 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
63 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
65 #define GP_DEVICE 0x300
67 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
69 static unsigned long omap_sram_start;
70 static void __iomem *omap_sram_base;
71 static unsigned long omap_sram_skip;
72 static unsigned long omap_sram_size;
73 static void __iomem *omap_sram_ceil;
76 * Depending on the target RAMFS firewall setup, the public usable amount of
77 * SRAM varies. The default accessible size for all device types is 2k. A GP
78 * device allows ARM11 but not other initiators for full size. This
79 * functionality seems ok until some nice security API happens.
81 static int is_sram_locked(void)
83 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
84 /* RAMFW: R/W access to all initiators for all qualifier sets */
85 if (cpu_is_omap242x()) {
86 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
87 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
88 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
90 if (cpu_is_omap34xx()) {
91 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
92 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
93 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
94 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
95 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
99 return 1; /* assume locked with no PPA or security driver */
103 * The amount of SRAM depends on the core type.
104 * Note that we cannot try to test for SRAM here because writes
105 * to secure SRAM will hang the system. Also the SRAM is not
106 * yet mapped at this point.
108 static void __init omap_detect_sram(void)
110 omap_sram_skip = SRAM_BOOTLOADER_SZ;
111 if (cpu_class_is_omap2()) {
112 if (is_sram_locked()) {
113 if (cpu_is_omap34xx()) {
114 omap_sram_start = OMAP3_SRAM_PUB_PA;
115 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
116 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
117 omap_sram_size = 0x7000; /* 28K */
118 omap_sram_skip += SZ_16K;
120 omap_sram_size = 0x8000; /* 32K */
122 } else if (cpu_is_omap44xx()) {
123 omap_sram_start = OMAP4_SRAM_PUB_PA;
124 omap_sram_size = 0xa000; /* 40K */
125 } else if (soc_is_omap54xx()) {
126 omap_sram_start = OMAP5_SRAM_PA;
127 omap_sram_size = SZ_128K; /* 128KB */
129 omap_sram_start = OMAP2_SRAM_PUB_PA;
130 omap_sram_size = 0x800; /* 2K */
133 if (soc_is_am33xx()) {
134 omap_sram_start = AM33XX_SRAM_PA;
135 omap_sram_size = 0x10000; /* 64K */
136 } else if (cpu_is_omap34xx()) {
137 omap_sram_start = OMAP3_SRAM_PA;
138 omap_sram_size = 0x10000; /* 64K */
139 } else if (cpu_is_omap44xx()) {
140 omap_sram_start = OMAP4_SRAM_PA;
141 omap_sram_size = 0xe000; /* 56K */
142 } else if (soc_is_omap54xx()) {
143 omap_sram_start = OMAP5_SRAM_PA;
144 omap_sram_size = SZ_128K; /* 128KB */
146 omap_sram_start = OMAP2_SRAM_PA;
147 if (cpu_is_omap242x())
148 omap_sram_size = 0xa0000; /* 640K */
149 else if (cpu_is_omap243x())
150 omap_sram_size = 0x10000; /* 64K */
154 omap_sram_start = OMAP1_SRAM_PA;
156 if (cpu_is_omap7xx())
157 omap_sram_size = 0x32000; /* 200K */
158 else if (cpu_is_omap15xx())
159 omap_sram_size = 0x30000; /* 192K */
160 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
161 cpu_is_omap1621() || cpu_is_omap1710())
162 omap_sram_size = 0x4000; /* 16K */
164 pr_err("Could not detect SRAM size\n");
165 omap_sram_size = 0x4000;
171 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
173 static void __init omap_fix_and_map_sram(void)
177 #ifdef CONFIG_OMAP4_ERRATA_I688
178 if (cpu_is_omap44xx()) {
179 omap_sram_start += PAGE_SIZE;
180 omap_sram_size -= SZ_16K;
183 if (cpu_is_omap34xx()) {
185 * SRAM must be marked as non-cached on OMAP3 since the
186 * CORE DPLL M2 divider change code (in SRAM) runs with the
187 * SDRAM controller disabled, and if it is marked cached,
188 * the ARM may attempt to write cache lines back to SDRAM
189 * which will cause the system to hang.
194 omap_map_sram(omap_sram_start, omap_sram_size,
195 omap_sram_skip, cached);
199 * Memory allocator for SRAM: calculates the new ceiling address
200 * for pushing a function using the fncpy API.
202 * Note that fncpy requires the returned address to be aligned
203 * to an 8-byte boundary.
205 void *omap_sram_push_address(unsigned long size)
207 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
209 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
211 if (size > available) {
212 pr_err("Not enough space in SRAM\n");
217 new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
218 omap_sram_ceil = IOMEM(new_ceil);
220 return (void *)omap_sram_ceil;
224 * The SRAM context is lost during off-idle and stack
227 void omap_sram_reset(void)
229 omap_sram_ceil = omap_sram_base + omap_sram_size;
233 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
235 void __init omap_map_sram(unsigned long start, unsigned long size,
236 unsigned long skip, int cached)
241 start = ROUND_DOWN(start, PAGE_SIZE);
242 omap_sram_size = size;
243 omap_sram_skip = skip;
244 omap_sram_base = __arm_ioremap_exec(start, size, cached);
245 if (!omap_sram_base) {
246 pr_err("SRAM: Could not map\n");
253 * Looks like we need to preserve some bootloader code at the
254 * beginning of SRAM for jumping to flash for reboot to work...
256 memset_io(omap_sram_base + omap_sram_skip, 0,
257 omap_sram_size - omap_sram_skip);
260 #ifdef CONFIG_ARCH_OMAP1
262 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
264 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
266 BUG_ON(!_omap_sram_reprogram_clock);
267 /* On 730, bit 13 must always be 1 */
268 if (cpu_is_omap7xx())
270 _omap_sram_reprogram_clock(dpllctl, ckctl);
273 static int __init omap1_sram_init(void)
275 _omap_sram_reprogram_clock =
276 omap_sram_push(omap1_sram_reprogram_clock,
277 omap1_sram_reprogram_clock_sz);
283 #define omap1_sram_init() do {} while (0)
286 #if defined(CONFIG_ARCH_OMAP2)
288 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
289 u32 base_cs, u32 force_unlock);
291 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
292 u32 base_cs, u32 force_unlock)
294 BUG_ON(!_omap2_sram_ddr_init);
295 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
296 base_cs, force_unlock);
299 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
302 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
304 BUG_ON(!_omap2_sram_reprogram_sdrc);
305 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
308 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
310 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
312 BUG_ON(!_omap2_set_prcm);
313 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
317 #ifdef CONFIG_SOC_OMAP2420
318 static int __init omap242x_sram_init(void)
320 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
321 omap242x_sram_ddr_init_sz);
323 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
324 omap242x_sram_reprogram_sdrc_sz);
326 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
327 omap242x_sram_set_prcm_sz);
332 static inline int omap242x_sram_init(void)
338 #ifdef CONFIG_SOC_OMAP2430
339 static int __init omap243x_sram_init(void)
341 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
342 omap243x_sram_ddr_init_sz);
344 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
345 omap243x_sram_reprogram_sdrc_sz);
347 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
348 omap243x_sram_set_prcm_sz);
353 static inline int omap243x_sram_init(void)
359 #ifdef CONFIG_ARCH_OMAP3
361 static u32 (*_omap3_sram_configure_core_dpll)(
362 u32 m2, u32 unlock_dll, u32 f, u32 inc,
363 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
364 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
365 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
366 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
368 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
369 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
370 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
371 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
372 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
374 BUG_ON(!_omap3_sram_configure_core_dpll);
375 return _omap3_sram_configure_core_dpll(
376 m2, unlock_dll, f, inc,
377 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
378 sdrc_actim_ctrl_b_0, sdrc_mr_0,
379 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
380 sdrc_actim_ctrl_b_1, sdrc_mr_1);
383 void omap3_sram_restore_context(void)
387 _omap3_sram_configure_core_dpll =
388 omap_sram_push(omap3_sram_configure_core_dpll,
389 omap3_sram_configure_core_dpll_sz);
390 omap_push_sram_idle();
393 static inline int omap34xx_sram_init(void)
395 omap3_sram_restore_context();
399 static inline int omap34xx_sram_init(void)
403 #endif /* CONFIG_ARCH_OMAP3 */
405 static inline int am33xx_sram_init(void)
410 int __init omap_sram_init(void)
413 omap_fix_and_map_sram();
415 if (!(cpu_class_is_omap2()))
417 else if (cpu_is_omap242x())
418 omap242x_sram_init();
419 else if (cpu_is_omap2430())
420 omap243x_sram_init();
421 else if (soc_is_am33xx())
423 else if (cpu_is_omap34xx())
424 omap34xx_sram_init();