2 * linux/arch/arm/plat-omap/sram.c
4 * OMAP SRAM detection and management
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
23 #include <asm/fncpy.h>
25 #include <asm/cacheflush.h>
27 #include <asm/mach/map.h>
29 #include "../mach-omap2/soc.h"
30 #include "../mach-omap2/sram.h"
32 /* XXX These "sideways" includes will disappear when sram.c becomes a driver */
33 #include "../mach-omap2/iomap.h"
34 #include "../mach-omap2/prm2xxx_3xxx.h"
35 #include "../mach-omap2/sdrc.h"
37 #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
38 #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
39 #ifdef CONFIG_OMAP4_ERRATA_I688
40 #define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
42 #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
44 #define OMAP5_SRAM_PA 0x40300000
46 #if defined(CONFIG_ARCH_OMAP2PLUS)
47 #define SRAM_BOOTLOADER_SZ 0x00
49 #define SRAM_BOOTLOADER_SZ 0x80
52 #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
53 #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
54 #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
56 #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
57 #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
58 #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
59 #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
60 #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
62 #define GP_DEVICE 0x300
64 #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
66 static unsigned long omap_sram_start;
67 static void __iomem *omap_sram_base;
68 static unsigned long omap_sram_skip;
69 static unsigned long omap_sram_size;
70 static void __iomem *omap_sram_ceil;
73 * Depending on the target RAMFS firewall setup, the public usable amount of
74 * SRAM varies. The default accessible size for all device types is 2k. A GP
75 * device allows ARM11 but not other initiators for full size. This
76 * functionality seems ok until some nice security API happens.
78 static int is_sram_locked(void)
80 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
81 /* RAMFW: R/W access to all initiators for all qualifier sets */
82 if (cpu_is_omap242x()) {
83 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
84 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
85 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
87 if (cpu_is_omap34xx()) {
88 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
89 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
90 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
91 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
92 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
96 return 1; /* assume locked with no PPA or security driver */
100 * The amount of SRAM depends on the core type.
101 * Note that we cannot try to test for SRAM here because writes
102 * to secure SRAM will hang the system. Also the SRAM is not
103 * yet mapped at this point.
105 static void __init omap_detect_sram(void)
107 omap_sram_skip = SRAM_BOOTLOADER_SZ;
108 if (cpu_class_is_omap2()) {
109 if (is_sram_locked()) {
110 if (cpu_is_omap34xx()) {
111 omap_sram_start = OMAP3_SRAM_PUB_PA;
112 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
113 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
114 omap_sram_size = 0x7000; /* 28K */
115 omap_sram_skip += SZ_16K;
117 omap_sram_size = 0x8000; /* 32K */
119 } else if (cpu_is_omap44xx()) {
120 omap_sram_start = OMAP4_SRAM_PUB_PA;
121 omap_sram_size = 0xa000; /* 40K */
122 } else if (soc_is_omap54xx()) {
123 omap_sram_start = OMAP5_SRAM_PA;
124 omap_sram_size = SZ_128K; /* 128KB */
126 omap_sram_start = OMAP2_SRAM_PUB_PA;
127 omap_sram_size = 0x800; /* 2K */
130 if (soc_is_am33xx()) {
131 omap_sram_start = AM33XX_SRAM_PA;
132 omap_sram_size = 0x10000; /* 64K */
133 } else if (cpu_is_omap34xx()) {
134 omap_sram_start = OMAP3_SRAM_PA;
135 omap_sram_size = 0x10000; /* 64K */
136 } else if (cpu_is_omap44xx()) {
137 omap_sram_start = OMAP4_SRAM_PA;
138 omap_sram_size = 0xe000; /* 56K */
139 } else if (soc_is_omap54xx()) {
140 omap_sram_start = OMAP5_SRAM_PA;
141 omap_sram_size = SZ_128K; /* 128KB */
143 omap_sram_start = OMAP2_SRAM_PA;
144 if (cpu_is_omap242x())
145 omap_sram_size = 0xa0000; /* 640K */
146 else if (cpu_is_omap243x())
147 omap_sram_size = 0x10000; /* 64K */
154 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
156 static void __init omap_fix_and_map_sram(void)
160 #ifdef CONFIG_OMAP4_ERRATA_I688
161 if (cpu_is_omap44xx()) {
162 omap_sram_start += PAGE_SIZE;
163 omap_sram_size -= SZ_16K;
166 if (cpu_is_omap34xx()) {
168 * SRAM must be marked as non-cached on OMAP3 since the
169 * CORE DPLL M2 divider change code (in SRAM) runs with the
170 * SDRAM controller disabled, and if it is marked cached,
171 * the ARM may attempt to write cache lines back to SDRAM
172 * which will cause the system to hang.
177 omap_map_sram(omap_sram_start, omap_sram_size,
178 omap_sram_skip, cached);
182 * Memory allocator for SRAM: calculates the new ceiling address
183 * for pushing a function using the fncpy API.
185 * Note that fncpy requires the returned address to be aligned
186 * to an 8-byte boundary.
188 void *omap_sram_push_address(unsigned long size)
190 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
192 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
194 if (size > available) {
195 pr_err("Not enough space in SRAM\n");
200 new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
201 omap_sram_ceil = IOMEM(new_ceil);
203 return (void *)omap_sram_ceil;
207 * The SRAM context is lost during off-idle and stack
210 void omap_sram_reset(void)
212 omap_sram_ceil = omap_sram_base + omap_sram_size;
216 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
218 void __init omap_map_sram(unsigned long start, unsigned long size,
219 unsigned long skip, int cached)
224 start = ROUND_DOWN(start, PAGE_SIZE);
225 omap_sram_size = size;
226 omap_sram_skip = skip;
227 omap_sram_base = __arm_ioremap_exec(start, size, cached);
228 if (!omap_sram_base) {
229 pr_err("SRAM: Could not map\n");
236 * Looks like we need to preserve some bootloader code at the
237 * beginning of SRAM for jumping to flash for reboot to work...
239 memset_io(omap_sram_base + omap_sram_skip, 0,
240 omap_sram_size - omap_sram_skip);
243 #if defined(CONFIG_ARCH_OMAP2)
245 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
246 u32 base_cs, u32 force_unlock);
248 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
249 u32 base_cs, u32 force_unlock)
251 BUG_ON(!_omap2_sram_ddr_init);
252 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
253 base_cs, force_unlock);
256 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
259 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
261 BUG_ON(!_omap2_sram_reprogram_sdrc);
262 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
265 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
267 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
269 BUG_ON(!_omap2_set_prcm);
270 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
274 #ifdef CONFIG_SOC_OMAP2420
275 static int __init omap242x_sram_init(void)
277 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
278 omap242x_sram_ddr_init_sz);
280 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
281 omap242x_sram_reprogram_sdrc_sz);
283 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
284 omap242x_sram_set_prcm_sz);
289 static inline int omap242x_sram_init(void)
295 #ifdef CONFIG_SOC_OMAP2430
296 static int __init omap243x_sram_init(void)
298 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
299 omap243x_sram_ddr_init_sz);
301 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
302 omap243x_sram_reprogram_sdrc_sz);
304 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
305 omap243x_sram_set_prcm_sz);
310 static inline int omap243x_sram_init(void)
316 #ifdef CONFIG_ARCH_OMAP3
318 static u32 (*_omap3_sram_configure_core_dpll)(
319 u32 m2, u32 unlock_dll, u32 f, u32 inc,
320 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
321 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
322 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
323 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
325 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
326 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
327 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
328 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
329 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
331 BUG_ON(!_omap3_sram_configure_core_dpll);
332 return _omap3_sram_configure_core_dpll(
333 m2, unlock_dll, f, inc,
334 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
335 sdrc_actim_ctrl_b_0, sdrc_mr_0,
336 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
337 sdrc_actim_ctrl_b_1, sdrc_mr_1);
340 void omap3_sram_restore_context(void)
344 _omap3_sram_configure_core_dpll =
345 omap_sram_push(omap3_sram_configure_core_dpll,
346 omap3_sram_configure_core_dpll_sz);
347 omap_push_sram_idle();
350 static inline int omap34xx_sram_init(void)
352 omap3_sram_restore_context();
356 static inline int omap34xx_sram_init(void)
360 #endif /* CONFIG_ARCH_OMAP3 */
362 static inline int am33xx_sram_init(void)
367 #ifdef CONFIG_ARCH_OMAP2PLUS
368 int __init omap_sram_init(void)
371 omap_fix_and_map_sram();
373 if (cpu_is_omap242x())
374 omap242x_sram_init();
375 else if (cpu_is_omap2430())
376 omap243x_sram_init();
377 else if (soc_is_am33xx())
379 else if (cpu_is_omap34xx())
380 omap34xx_sram_init();