arch/arm/plat-omap/dmtimer.c

   1 /*
   2  * linux/arch/arm/plat-omap/dmtimer.c
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * dmtimer adaptation to platform_driver.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * OMAP2 support by Juha Yrjola
  14  * API improvements and OMAP2 clock framework support by Timo Teras
  15  *
  16  * Copyright (C) 2009 Texas Instruments
  17  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  18  *
  19  * This program is free software; you can redistribute it and/or modify it
  20  * under the terms of the GNU General Public License as published by the
  21  * Free Software Foundation; either version 2 of the License, or (at your
  22  * option) any later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  27  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the  GNU General Public License along
  34  * with this program; if not, write  to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/clk.h>
  39 #include <linux/module.h>
  40 #include <linux/io.h>
  41 #include <linux/device.h>
  42 #include <linux/err.h>
  43 #include <linux/pm_runtime.h>
  44 #include <linux/of.h>
  45 #include <linux/of_device.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/platform_data/dmtimer-omap.h>
  48
  49 #include <plat/dmtimer.h>
  50
  51 static u32 omap_reserved_systimers;
  52 static LIST_HEAD(omap_timer_list);
  53 static DEFINE_SPINLOCK(dm_timer_lock);
  54
  55 enum {
  56         REQUEST_ANY = 0,
  57         REQUEST_BY_ID,
  58         REQUEST_BY_CAP,
  59         REQUEST_BY_NODE,
  60 };
  61
  62 /**
  63  * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode
  64  * @timer:      timer pointer over which read operation to perform
  65  * @reg:        lowest byte holds the register offset
  66  *
  67  * The posted mode bit is encoded in reg. Note that in posted mode write
  68  * pending bit must be checked. Otherwise a read of a non completed write
  69  * will produce an error.
  70  */
  71 static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
  72 {
  73         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  74         return __omap_dm_timer_read(timer, reg, timer->posted);
  75 }
  76
  77 /**
  78  * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode
  79  * @timer:      timer pointer over which write operation is to perform
  80  * @reg:        lowest byte holds the register offset
  81  * @value:      data to write into the register
  82  *
  83  * The posted mode bit is encoded in reg. Note that in posted mode the write
  84  * pending bit must be checked. Otherwise a write on a register which has a
  85  * pending write will be lost.
  86  */
  87 static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
  88                                                 u32 value)
  89 {
  90         WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET);
  91         __omap_dm_timer_write(timer, reg, value, timer->posted);
  92 }
  93
  94 static void omap_timer_restore_context(struct omap_dm_timer *timer)
  95 {
  96         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
  97                                 timer->context.twer);
  98         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
  99                                 timer->context.tcrr);
 100         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG,
 101                                 timer->context.tldr);
 102         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG,
 103                                 timer->context.tmar);
 104         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
 105                                 timer->context.tsicr);
 106         __raw_writel(timer->context.tier, timer->irq_ena);
 107         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
 108                                 timer->context.tclr);
 109 }
 110
 111 static int omap_dm_timer_reset(struct omap_dm_timer *timer)
 112 {
 113         u32 l, timeout = 100000;
 114
 115         if (timer->revision != 1)
 116                 return -EINVAL;
 117
 118         omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
 119
 120         do {
 121                 l = __omap_dm_timer_read(timer,
 122                                          OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
 123         } while (!l && timeout--);
 124
 125         if (!timeout) {
 126                 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
 127                 return -ETIMEDOUT;
 128         }
 129
 130         /* Configure timer for smart-idle mode */
 131         l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
 132         l |= 0x2 << 0x3;
 133         __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
 134
 135         timer->posted = 0;
 136
 137         return 0;
 138 }
 139
 140 static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 141 {
 142         int rc;
 143
 144         /*
 145          * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
 146          * do not call clk_get() for these devices.
 147          */
 148         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
 149                 timer->fclk = clk_get(&timer->pdev->dev, "fck");
 150                 if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
 151                         timer->fclk = NULL;
 152                         dev_err(&timer->pdev->dev, ": No fclk handle.\n");
 153                         return -EINVAL;
 154                 }
 155         }
 156
 157         omap_dm_timer_enable(timer);
 158
 159         if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
 160                 rc = omap_dm_timer_reset(timer);
 161                 if (rc) {
 162                         omap_dm_timer_disable(timer);
 163                         return rc;
 164                 }
 165         }
 166
 167         __omap_dm_timer_enable_posted(timer);
 168         omap_dm_timer_disable(timer);
 169
 170         return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
 171 }
 172
 173 static inline u32 omap_dm_timer_reserved_systimer(int id)
 174 {
 175         return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
 176 }
 177
 178 int omap_dm_timer_reserve_systimer(int id)
 179 {
 180         if (omap_dm_timer_reserved_systimer(id))
 181                 return -ENODEV;
 182
 183         omap_reserved_systimers |= (1 << (id - 1));
 184
 185         return 0;
 186 }
 187
 188 static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
 189 {
 190         struct omap_dm_timer *timer = NULL, *t;
 191         struct device_node *np = NULL;
 192         unsigned long flags;
 193         u32 cap = 0;
 194         int id = 0;
 195
 196         switch (req_type) {
 197         case REQUEST_BY_ID:
 198                 id = *(int *)data;
 199                 break;
 200         case REQUEST_BY_CAP:
 201                 cap = *(u32 *)data;
 202                 break;
 203         case REQUEST_BY_NODE:
 204                 np = (struct device_node *)data;
 205                 break;
 206         default:
 207                 /* REQUEST_ANY */
 208                 break;
 209         }
 210
 211         spin_lock_irqsave(&dm_timer_lock, flags);
 212         list_for_each_entry(t, &omap_timer_list, node) {
 213                 if (t->reserved)
 214                         continue;
 215
 216                 switch (req_type) {
 217                 case REQUEST_BY_ID:
 218                         if (id == t->pdev->id) {
 219                                 timer = t;
 220                                 timer->reserved = 1;
 221                                 goto found;
 222                         }
 223                         break;
 224                 case REQUEST_BY_CAP:
 225                         if (cap == (t->capability & cap)) {
 226                                 /*
 227                                  * If timer is not NULL, we have already found
 228                                  * one timer but it was not an exact match
 229                                  * because it had more capabilites that what
 230                                  * was required. Therefore, unreserve the last
 231                                  * timer found and see if this one is a better
 232                                  * match.
 233                                  */
 234                                 if (timer)
 235                                         timer->reserved = 0;
 236                                 timer = t;
 237                                 timer->reserved = 1;
 238
 239                                 /* Exit loop early if we find an exact match */
 240                                 if (t->capability == cap)
 241                                         goto found;
 242                         }
 243                         break;
 244                 case REQUEST_BY_NODE:
 245                         if (np == t->pdev->dev.of_node) {
 246                                 timer = t;
 247                                 timer->reserved = 1;
 248                                 goto found;
 249                         }
 250                         break;
 251                 default:
 252                         /* REQUEST_ANY */
 253                         timer = t;
 254                         timer->reserved = 1;
 255                         goto found;
 256                 }
 257         }
 258 found:
 259         spin_unlock_irqrestore(&dm_timer_lock, flags);
 260
 261         if (timer && omap_dm_timer_prepare(timer)) {
 262                 timer->reserved = 0;
 263                 timer = NULL;
 264         }
 265
 266         if (!timer)
 267                 pr_debug("%s: timer request failed!\n", __func__);
 268
 269         return timer;
 270 }
 271
 272 struct omap_dm_timer *omap_dm_timer_request(void)
 273 {
 274         return _omap_dm_timer_request(REQUEST_ANY, NULL);
 275 }
 276 EXPORT_SYMBOL_GPL(omap_dm_timer_request);
 277
 278 struct omap_dm_timer *omap_dm_timer_request_specific(int id)
 279 {
 280         /* Requesting timer by ID is not supported when device tree is used */
 281         if (of_have_populated_dt()) {
 282                 pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n",
 283                         __func__);
 284                 return NULL;
 285         }
 286
 287         return _omap_dm_timer_request(REQUEST_BY_ID, &id);
 288 }
 289 EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
 290
 291 /**
 292  * omap_dm_timer_request_by_cap - Request a timer by capability
 293  * @cap:        Bit mask of capabilities to match
 294  *
 295  * Find a timer based upon capabilities bit mask. Callers of this function
 296  * should use the definitions found in the plat/dmtimer.h file under the
 297  * comment "timer capabilities used in hwmod database". Returns pointer to
 298  * timer handle on success and a NULL pointer on failure.
 299  */
 300 struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
 301 {
 302         return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
 303 }
 304 EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
 305
 306 /**
 307  * omap_dm_timer_request_by_node - Request a timer by device-tree node
 308  * @np:         Pointer to device-tree timer node
 309  *
 310  * Request a timer based upon a device node pointer. Returns pointer to
 311  * timer handle on success and a NULL pointer on failure.
 312  */
 313 struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
 314 {
 315         if (!np)
 316                 return NULL;
 317
 318         return _omap_dm_timer_request(REQUEST_BY_NODE, np);
 319 }
 320 EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_node);
 321
 322 int omap_dm_timer_free(struct omap_dm_timer *timer)
 323 {
 324         if (unlikely(!timer))
 325                 return -EINVAL;
 326
 327         clk_put(timer->fclk);
 328
 329         WARN_ON(!timer->reserved);
 330         timer->reserved = 0;
 331         return 0;
 332 }
 333 EXPORT_SYMBOL_GPL(omap_dm_timer_free);
 334
 335 void omap_dm_timer_enable(struct omap_dm_timer *timer)
 336 {
 337         int c;
 338
 339         pm_runtime_get_sync(&timer->pdev->dev);
 340
 341         if (!(timer->capability & OMAP_TIMER_ALWON)) {
 342                 if (timer->get_context_loss_count) {
 343                         c = timer->get_context_loss_count(&timer->pdev->dev);
 344                         if (c != timer->ctx_loss_count) {
 345                                 omap_timer_restore_context(timer);
 346                                 timer->ctx_loss_count = c;
 347                         }
 348                 } else {
 349                         omap_timer_restore_context(timer);
 350                 }
 351         }
 352 }
 353 EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 354
 355 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 356 {
 357         pm_runtime_put_sync(&timer->pdev->dev);
 358 }
 359 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 360
 361 int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
 362 {
 363         if (timer)
 364                 return timer->irq;
 365         return -EINVAL;
 366 }
 367 EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
 368
 369 #if defined(CONFIG_ARCH_OMAP1)
 370 #include <mach/hardware.h>
 371 /**
 372  * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
 373  * @inputmask: current value of idlect mask
 374  */
 375 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 376 {
 377         int i = 0;
 378         struct omap_dm_timer *timer = NULL;
 379         unsigned long flags;
 380
 381         /* If ARMXOR cannot be idled this function call is unnecessary */
 382         if (!(inputmask & (1 << 1)))
 383                 return inputmask;
 384
 385         /* If any active timer is using ARMXOR return modified mask */
 386         spin_lock_irqsave(&dm_timer_lock, flags);
 387         list_for_each_entry(timer, &omap_timer_list, node) {
 388                 u32 l;
 389
 390                 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 391                 if (l & OMAP_TIMER_CTRL_ST) {
 392                         if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0)
 393                                 inputmask &= ~(1 << 1);
 394                         else
 395                                 inputmask &= ~(1 << 2);
 396                 }
 397                 i++;
 398         }
 399         spin_unlock_irqrestore(&dm_timer_lock, flags);
 400
 401         return inputmask;
 402 }
 403 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 404
 405 #else
 406
 407 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
 408 {
 409         if (timer)
 410                 return timer->fclk;
 411         return NULL;
 412 }
 413 EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
 414
 415 __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
 416 {
 417         BUG();
 418
 419         return 0;
 420 }
 421 EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
 422
 423 #endif
 424
 425 int omap_dm_timer_trigger(struct omap_dm_timer *timer)
 426 {
 427         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 428                 pr_err("%s: timer not available or enabled.\n", __func__);
 429                 return -EINVAL;
 430         }
 431
 432         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 433         return 0;
 434 }
 435 EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
 436
 437 int omap_dm_timer_start(struct omap_dm_timer *timer)
 438 {
 439         u32 l;
 440
 441         if (unlikely(!timer))
 442                 return -EINVAL;
 443
 444         omap_dm_timer_enable(timer);
 445
 446         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 447         if (!(l & OMAP_TIMER_CTRL_ST)) {
 448                 l |= OMAP_TIMER_CTRL_ST;
 449                 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 450         }
 451
 452         /* Save the context */
 453         timer->context.tclr = l;
 454         return 0;
 455 }
 456 EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 457
 458 int omap_dm_timer_stop(struct omap_dm_timer *timer)
 459 {
 460         unsigned long rate = 0;
 461
 462         if (unlikely(!timer))
 463                 return -EINVAL;
 464
 465         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
 466                 rate = clk_get_rate(timer->fclk);
 467
 468         __omap_dm_timer_stop(timer, timer->posted, rate);
 469
 470         /*
 471          * Since the register values are computed and written within
 472          * __omap_dm_timer_stop, we need to use read to retrieve the
 473          * context.
 474          */
 475         timer->context.tclr =
 476                         omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 477         omap_dm_timer_disable(timer);
 478         return 0;
 479 }
 480 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 481
 482 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 483 {
 484         int ret;
 485         char *parent_name = NULL;
 486         struct clk *parent;
 487         struct dmtimer_platform_data *pdata;
 488
 489         if (unlikely(!timer))
 490                 return -EINVAL;
 491
 492         pdata = timer->pdev->dev.platform_data;
 493
 494         if (source < 0 || source >= 3)
 495                 return -EINVAL;
 496
 497         /*
 498          * FIXME: Used for OMAP1 devices only because they do not currently
 499          * use the clock framework to set the parent clock. To be removed
 500          * once OMAP1 migrated to using clock framework for dmtimers
 501          */
 502         if (pdata && pdata->set_timer_src)
 503                 return pdata->set_timer_src(timer->pdev, source);
 504
 505         if (!timer->fclk)
 506                 return -EINVAL;
 507
 508         switch (source) {
 509         case OMAP_TIMER_SRC_SYS_CLK:
 510                 parent_name = "timer_sys_ck";
 511                 break;
 512
 513         case OMAP_TIMER_SRC_32_KHZ:
 514                 parent_name = "timer_32k_ck";
 515                 break;
 516
 517         case OMAP_TIMER_SRC_EXT_CLK:
 518                 parent_name = "timer_ext_ck";
 519                 break;
 520         }
 521
 522         parent = clk_get(&timer->pdev->dev, parent_name);
 523         if (IS_ERR_OR_NULL(parent)) {
 524                 pr_err("%s: %s not found\n", __func__, parent_name);
 525                 return -EINVAL;
 526         }
 527
 528         ret = clk_set_parent(timer->fclk, parent);
 529         if (IS_ERR_VALUE(ret))
 530                 pr_err("%s: failed to set %s as parent\n", __func__,
 531                         parent_name);
 532
 533         clk_put(parent);
 534
 535         return ret;
 536 }
 537 EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
 538
 539 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
 540                             unsigned int load)
 541 {
 542         u32 l;
 543
 544         if (unlikely(!timer))
 545                 return -EINVAL;
 546
 547         omap_dm_timer_enable(timer);
 548         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 549         if (autoreload)
 550                 l |= OMAP_TIMER_CTRL_AR;
 551         else
 552                 l &= ~OMAP_TIMER_CTRL_AR;
 553         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 554         omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 555
 556         omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
 557         /* Save the context */
 558         timer->context.tclr = l;
 559         timer->context.tldr = load;
 560         omap_dm_timer_disable(timer);
 561         return 0;
 562 }
 563 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
 564
 565 /* Optimized set_load which removes costly spin wait in timer_start */
 566 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
 567                             unsigned int load)
 568 {
 569         u32 l;
 570
 571         if (unlikely(!timer))
 572                 return -EINVAL;
 573
 574         omap_dm_timer_enable(timer);
 575
 576         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 577         if (autoreload) {
 578                 l |= OMAP_TIMER_CTRL_AR;
 579                 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
 580         } else {
 581                 l &= ~OMAP_TIMER_CTRL_AR;
 582         }
 583         l |= OMAP_TIMER_CTRL_ST;
 584
 585         __omap_dm_timer_load_start(timer, l, load, timer->posted);
 586
 587         /* Save the context */
 588         timer->context.tclr = l;
 589         timer->context.tldr = load;
 590         timer->context.tcrr = load;
 591         return 0;
 592 }
 593 EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
 594
 595 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
 596                              unsigned int match)
 597 {
 598         u32 l;
 599
 600         if (unlikely(!timer))
 601                 return -EINVAL;
 602
 603         omap_dm_timer_enable(timer);
 604         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 605         if (enable)
 606                 l |= OMAP_TIMER_CTRL_CE;
 607         else
 608                 l &= ~OMAP_TIMER_CTRL_CE;
 609         omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
 610         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 611
 612         /* Save the context */
 613         timer->context.tclr = l;
 614         timer->context.tmar = match;
 615         omap_dm_timer_disable(timer);
 616         return 0;
 617 }
 618 EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
 619
 620 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
 621                            int toggle, int trigger)
 622 {
 623         u32 l;
 624
 625         if (unlikely(!timer))
 626                 return -EINVAL;
 627
 628         omap_dm_timer_enable(timer);
 629         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 630         l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM |
 631                OMAP_TIMER_CTRL_PT | (0x03 << 10));
 632         if (def_on)
 633                 l |= OMAP_TIMER_CTRL_SCPWM;
 634         if (toggle)
 635                 l |= OMAP_TIMER_CTRL_PT;
 636         l |= trigger << 10;
 637         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 638
 639         /* Save the context */
 640         timer->context.tclr = l;
 641         omap_dm_timer_disable(timer);
 642         return 0;
 643 }
 644 EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
 645
 646 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
 647 {
 648         u32 l;
 649
 650         if (unlikely(!timer))
 651                 return -EINVAL;
 652
 653         omap_dm_timer_enable(timer);
 654         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
 655         l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2));
 656         if (prescaler >= 0x00 && prescaler <= 0x07) {
 657                 l |= OMAP_TIMER_CTRL_PRE;
 658                 l |= prescaler << 2;
 659         }
 660         omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
 661
 662         /* Save the context */
 663         timer->context.tclr = l;
 664         omap_dm_timer_disable(timer);
 665         return 0;
 666 }
 667 EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
 668
 669 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
 670                                   unsigned int value)
 671 {
 672         if (unlikely(!timer))
 673                 return -EINVAL;
 674
 675         omap_dm_timer_enable(timer);
 676         __omap_dm_timer_int_enable(timer, value);
 677
 678         /* Save the context */
 679         timer->context.tier = value;
 680         timer->context.twer = value;
 681         omap_dm_timer_disable(timer);
 682         return 0;
 683 }
 684 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
 685
 686 /**
 687  * omap_dm_timer_set_int_disable - disable timer interrupts
 688  * @timer:      pointer to timer handle
 689  * @mask:       bit mask of interrupts to be disabled
 690  *
 691  * Disables the specified timer interrupts for a timer.
 692  */
 693 int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
 694 {
 695         u32 l = mask;
 696
 697         if (unlikely(!timer))
 698                 return -EINVAL;
 699
 700         omap_dm_timer_enable(timer);
 701
 702         if (timer->revision == 1)
 703                 l = __raw_readl(timer->irq_ena) & ~mask;
 704
 705         __raw_writel(l, timer->irq_dis);
 706         l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
 707         omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
 708
 709         /* Save the context */
 710         timer->context.tier &= ~mask;
 711         timer->context.twer &= ~mask;
 712         omap_dm_timer_disable(timer);
 713         return 0;
 714 }
 715 EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
 716
 717 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
 718 {
 719         unsigned int l;
 720
 721         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 722                 pr_err("%s: timer not available or enabled.\n", __func__);
 723                 return 0;
 724         }
 725
 726         l = __raw_readl(timer->irq_stat);
 727
 728         return l;
 729 }
 730 EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
 731
 732 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
 733 {
 734         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
 735                 return -EINVAL;
 736
 737         __omap_dm_timer_write_status(timer, value);
 738
 739         return 0;
 740 }
 741 EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
 742
 743 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
 744 {
 745         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 746                 pr_err("%s: timer not iavailable or enabled.\n", __func__);
 747                 return 0;
 748         }
 749
 750         return __omap_dm_timer_read_counter(timer, timer->posted);
 751 }
 752 EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
 753
 754 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
 755 {
 756         if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
 757                 pr_err("%s: timer not available or enabled.\n", __func__);
 758                 return -EINVAL;
 759         }
 760
 761         omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
 762
 763         /* Save the context */
 764         timer->context.tcrr = value;
 765         return 0;
 766 }
 767 EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
 768
 769 int omap_dm_timers_active(void)
 770 {
 771         struct omap_dm_timer *timer;
 772
 773         list_for_each_entry(timer, &omap_timer_list, node) {
 774                 if (!timer->reserved)
 775                         continue;
 776
 777                 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
 778                     OMAP_TIMER_CTRL_ST) {
 779                         return 1;
 780                 }
 781         }
 782         return 0;
 783 }
 784 EXPORT_SYMBOL_GPL(omap_dm_timers_active);
 785
 786 /**
 787  * omap_dm_timer_probe - probe function called for every registered device
 788  * @pdev:       pointer to current timer platform device
 789  *
 790  * Called by driver framework at the end of device registration for all
 791  * timer devices.
 792  */
 793 static int omap_dm_timer_probe(struct platform_device *pdev)
 794 {
 795         unsigned long flags;
 796         struct omap_dm_timer *timer;
 797         struct resource *mem, *irq;
 798         struct device *dev = &pdev->dev;
 799         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 800
 801         if (!pdata && !dev->of_node) {
 802                 dev_err(dev, "%s: no platform data.\n", __func__);
 803                 return -ENODEV;
 804         }
 805
 806         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 807         if (unlikely(!irq)) {
 808                 dev_err(dev, "%s: no IRQ resource.\n", __func__);
 809                 return -ENODEV;
 810         }
 811
 812         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 813         if (unlikely(!mem)) {
 814                 dev_err(dev, "%s: no memory resource.\n", __func__);
 815                 return -ENODEV;
 816         }
 817
 818         timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
 819         if (!timer) {
 820                 dev_err(dev, "%s: memory alloc failed!\n", __func__);
 821                 return  -ENOMEM;
 822         }
 823
 824         timer->io_base = devm_ioremap_resource(dev, mem);
 825         if (IS_ERR(timer->io_base))
 826                 return PTR_ERR(timer->io_base);
 827
 828         if (dev->of_node) {
 829                 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
 830                         timer->capability |= OMAP_TIMER_ALWON;
 831                 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
 832                         timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
 833                 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
 834                         timer->capability |= OMAP_TIMER_HAS_PWM;
 835                 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
 836                         timer->capability |= OMAP_TIMER_SECURE;
 837         } else {
 838                 timer->id = pdev->id;
 839                 timer->errata = pdata->timer_errata;
 840                 timer->capability = pdata->timer_capability;
 841                 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
 842                 timer->get_context_loss_count = pdata->get_context_loss_count;
 843         }
 844
 845         timer->irq = irq->start;
 846         timer->pdev = pdev;
 847
 848         /* Skip pm_runtime_enable for OMAP1 */
 849         if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
 850                 pm_runtime_enable(dev);
 851                 pm_runtime_irq_safe(dev);
 852         }
 853
 854         if (!timer->reserved) {
 855                 pm_runtime_get_sync(dev);
 856                 __omap_dm_timer_init_regs(timer);
 857                 pm_runtime_put(dev);
 858         }
 859
 860         /* add the timer element to the list */
 861         spin_lock_irqsave(&dm_timer_lock, flags);
 862         list_add_tail(&timer->node, &omap_timer_list);
 863         spin_unlock_irqrestore(&dm_timer_lock, flags);
 864
 865         dev_dbg(dev, "Device Probed.\n");
 866
 867         return 0;
 868 }
 869
 870 /**
 871  * omap_dm_timer_remove - cleanup a registered timer device
 872  * @pdev:       pointer to current timer platform device
 873  *
 874  * Called by driver framework whenever a timer device is unregistered.
 875  * In addition to freeing platform resources it also deletes the timer
 876  * entry from the local list.
 877  */
 878 static int omap_dm_timer_remove(struct platform_device *pdev)
 879 {
 880         struct omap_dm_timer *timer;
 881         unsigned long flags;
 882         int ret = -EINVAL;
 883
 884         spin_lock_irqsave(&dm_timer_lock, flags);
 885         list_for_each_entry(timer, &omap_timer_list, node)
 886                 if (!strcmp(dev_name(&timer->pdev->dev),
 887                             dev_name(&pdev->dev))) {
 888                         list_del(&timer->node);
 889                         ret = 0;
 890                         break;
 891                 }
 892         spin_unlock_irqrestore(&dm_timer_lock, flags);
 893
 894         return ret;
 895 }
 896
 897 static const struct of_device_id omap_timer_match[] = {
 898         { .compatible = "ti,omap2420-timer", },
 899         { .compatible = "ti,omap3430-timer", },
 900         { .compatible = "ti,omap4430-timer", },
 901         { .compatible = "ti,omap5430-timer", },
 902         { .compatible = "ti,am335x-timer", },
 903         { .compatible = "ti,am335x-timer-1ms", },
 904         {},
 905 };
 906 MODULE_DEVICE_TABLE(of, omap_timer_match);
 907
 908 static struct platform_driver omap_dm_timer_driver = {
 909         .probe  = omap_dm_timer_probe,
 910         .remove = omap_dm_timer_remove,
 911         .driver = {
 912                 .name   = "omap_timer",
 913                 .of_match_table = of_match_ptr(omap_timer_match),
 914         },
 915 };
 916
 917 early_platform_init("earlytimer", &omap_dm_timer_driver);
 918 module_platform_driver(omap_dm_timer_driver);
 919
 920 MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver");
 921 MODULE_LICENSE("GPL");
 922 MODULE_ALIAS("platform:" DRIVER_NAME);
 923 MODULE_AUTHOR("Texas Instruments Inc");