arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/hwcap.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/memory.h>
  20
  21 #include "proc-macros.S"
  22
  23 #ifdef CONFIG_ARM_LPAE
  24 #include "proc-v7-3level.S"
  25 #else
  26 #include "proc-v7-2level.S"
  27 #endif
  28
  29 ENTRY(cpu_v7_proc_init)
  30         ret     lr
  31 ENDPROC(cpu_v7_proc_init)
  32
  33 ENTRY(cpu_v7_proc_fin)
  34         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  35         bic     r0, r0, #0x1000                 @ ...i............
  36         bic     r0, r0, #0x0006                 @ .............ca.
  37         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  38         ret     lr
  39 ENDPROC(cpu_v7_proc_fin)
  40
  41 /*
  42  *      cpu_v7_reset(loc, hyp)
  43  *
  44  *      Perform a soft reset of the system.  Put the CPU into the
  45  *      same state as it would be if it had been reset, and branch
  46  *      to what would be the reset vector.
  47  *
  48  *      - loc   - location to jump to for soft reset
  49  *      - hyp   - indicate if restart occurs in HYP mode
  50  *
  51  *      This code must be executed using a flat identity mapping with
  52  *      caches disabled.
  53  */
  54         .align  5
  55         .pushsection    .idmap.text, "ax"
  56 ENTRY(cpu_v7_reset)
  57         mrc     p15, 0, r2, c1, c0, 0           @ ctrl register
  58         bic     r2, r2, #0x1                    @ ...............m
  59  THUMB( bic     r2, r2, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
  60         mcr     p15, 0, r2, c1, c0, 0           @ disable MMU
  61         isb
  62 #ifdef CONFIG_ARM_VIRT_EXT
  63         teq     r1, #0
  64         bne     __hyp_soft_restart
  65 #endif
  66         bx      r0
  67 ENDPROC(cpu_v7_reset)
  68         .popsection
  69
  70 /*
  71  *      cpu_v7_do_idle()
  72  *
  73  *      Idle the processor (eg, wait for interrupt).
  74  *
  75  *      IRQs are already disabled.
  76  */
  77 ENTRY(cpu_v7_do_idle)
  78         dsb                                     @ WFI may enter a low-power mode
  79         wfi
  80         ret     lr
  81 ENDPROC(cpu_v7_do_idle)
  82
  83 ENTRY(cpu_v7_dcache_clean_area)
  84         ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
  85         ALT_UP_B(1f)
  86         ret     lr
  87 1:      dcache_line_size r2, r3
  88 2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  89         add     r0, r0, r2
  90         subs    r1, r1, r2
  91         bhi     2b
  92         dsb     ishst
  93         ret     lr
  94 ENDPROC(cpu_v7_dcache_clean_area)
  95
  96 ENTRY(cpu_v7_iciallu_switch_mm)
  97         mov     r3, #0
  98         mcr     p15, 0, r3, c7, c5, 0           @ ICIALLU
  99         b       cpu_v7_switch_mm
 100 ENDPROC(cpu_v7_iciallu_switch_mm)
 101 ENTRY(cpu_v7_bpiall_switch_mm)
 102         mov     r3, #0
 103         mcr     p15, 0, r3, c7, c5, 6           @ flush BTAC/BTB
 104         b       cpu_v7_switch_mm
 105 ENDPROC(cpu_v7_bpiall_switch_mm)
 106
 107         string  cpu_v7_name, "ARMv7 Processor"
 108         .align
 109
 110 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 111 .globl  cpu_v7_suspend_size
 112 .equ    cpu_v7_suspend_size, 4 * 9
 113 #ifdef CONFIG_ARM_CPU_SUSPEND
 114 ENTRY(cpu_v7_do_suspend)
 115         stmfd   sp!, {r4 - r11, lr}
 116         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 117         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 118         stmia   r0!, {r4 - r5}
 119 #ifdef CONFIG_MMU
 120         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 121 #ifdef CONFIG_ARM_LPAE
 122         mrrc    p15, 1, r5, r7, c2      @ TTB 1
 123 #else
 124         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
 125 #endif
 126         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
 127 #endif
 128         mrc     p15, 0, r8, c1, c0, 0   @ Control register
 129         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
 130         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 131         stmia   r0, {r5 - r11}
 132         ldmfd   sp!, {r4 - r11, pc}
 133 ENDPROC(cpu_v7_do_suspend)
 134
 135 ENTRY(cpu_v7_do_resume)
 136         mov     ip, #0
 137         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 138         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 139         ldmia   r0!, {r4 - r5}
 140         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 141         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 142         ldmia   r0, {r5 - r11}
 143 #ifdef CONFIG_MMU
 144         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
 145         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 146 #ifdef CONFIG_ARM_LPAE
 147         mcrr    p15, 0, r1, ip, c2      @ TTB 0
 148         mcrr    p15, 1, r5, r7, c2      @ TTB 1
 149 #else
 150         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 151         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 152         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
 153         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
 154 #endif
 155         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
 156         ldr     r4, =PRRR               @ PRRR
 157         ldr     r5, =NMRR               @ NMRR
 158         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
 159         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
 160 #endif  /* CONFIG_MMU */
 161         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
 162         teq     r4, r9                  @ Is it already set?
 163         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
 164         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 165         isb
 166         dsb
 167         mov     r0, r8                  @ control register
 168         b       cpu_resume_mmu
 169 ENDPROC(cpu_v7_do_resume)
 170 #endif
 171
 172 .globl  cpu_ca9mp_suspend_size
 173 .equ    cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
 174 #ifdef CONFIG_ARM_CPU_SUSPEND
 175 ENTRY(cpu_ca9mp_do_suspend)
 176         stmfd   sp!, {r4 - r5}
 177         mrc     p15, 0, r4, c15, c0, 1          @ Diagnostic register
 178         mrc     p15, 0, r5, c15, c0, 0          @ Power register
 179         stmia   r0!, {r4 - r5}
 180         ldmfd   sp!, {r4 - r5}
 181         b       cpu_v7_do_suspend
 182 ENDPROC(cpu_ca9mp_do_suspend)
 183
 184 ENTRY(cpu_ca9mp_do_resume)
 185         ldmia   r0!, {r4 - r5}
 186         mrc     p15, 0, r10, c15, c0, 1         @ Read Diagnostic register
 187         teq     r4, r10                         @ Already restored?
 188         mcrne   p15, 0, r4, c15, c0, 1          @ No, so restore it
 189         mrc     p15, 0, r10, c15, c0, 0         @ Read Power register
 190         teq     r5, r10                         @ Already restored?
 191         mcrne   p15, 0, r5, c15, c0, 0          @ No, so restore it
 192         b       cpu_v7_do_resume
 193 ENDPROC(cpu_ca9mp_do_resume)
 194 #endif
 195
 196 #ifdef CONFIG_CPU_PJ4B
 197         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
 198         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
 199         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
 200         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
 201         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
 202 #ifdef CONFIG_PJ4B_ERRATA_4742
 203 ENTRY(cpu_pj4b_do_idle)
 204         dsb                                     @ WFI may enter a low-power mode
 205         wfi
 206         dsb                                     @barrier
 207         ret     lr
 208 ENDPROC(cpu_pj4b_do_idle)
 209 #else
 210         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 211 #endif
 212         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
 213 #ifdef CONFIG_ARM_CPU_SUSPEND
 214 ENTRY(cpu_pj4b_do_suspend)
 215         stmfd   sp!, {r6 - r10}
 216         mrc     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
 217         mrc     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
 218         mrc     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
 219         mrc     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
 220         mrc     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
 221         stmia   r0!, {r6 - r10}
 222         ldmfd   sp!, {r6 - r10}
 223         b cpu_v7_do_suspend
 224 ENDPROC(cpu_pj4b_do_suspend)
 225
 226 ENTRY(cpu_pj4b_do_resume)
 227         ldmia   r0!, {r6 - r10}
 228         mcr     p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
 229         mcr     p15, 1, r7, c15, c2, 0  @ restore CP15 - Aux Func Modes Ctrl 0
 230         mcr     p15, 1, r8, c15, c1, 2  @ restore CP15 - Aux Debug Modes Ctrl 2
 231         mcr     p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
 232         mcr     p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
 233         b cpu_v7_do_resume
 234 ENDPROC(cpu_pj4b_do_resume)
 235 #endif
 236 .globl  cpu_pj4b_suspend_size
 237 .equ    cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
 238
 239 #endif
 240
 241 /*
 242  *      __v7_setup
 243  *
 244  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 245  *      on.  Return in r0 the new CP15 C1 control register setting.
 246  *
 247  *      r1, r2, r4, r5, r9, r13 must be preserved - r13 is not a stack
 248  *      r4: TTBR0 (low word)
 249  *      r5: TTBR0 (high word if LPAE)
 250  *      r8: TTBR1
 251  *      r9: Main ID register
 252  *
 253  *      This should be able to cover all ARMv7 cores.
 254  *
 255  *      It is assumed that:
 256  *      - cache type register is implemented
 257  */
 258 __v7_ca5mp_setup:
 259 __v7_ca9mp_setup:
 260 __v7_cr7mp_setup:
 261         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
 262         b       1f
 263 __v7_ca7mp_setup:
 264 __v7_ca12mp_setup:
 265 __v7_ca15mp_setup:
 266 __v7_b15mp_setup:
 267 __v7_ca17mp_setup:
 268         mov     r10, #0
 269 1:      adr     r0, __v7_setup_stack_ptr
 270         ldr     r12, [r0]
 271         add     r12, r12, r0                    @ the local stack
 272         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
 273         bl      v7_invalidate_l1
 274         ldmia   r12, {r1-r6, lr}
 275 #ifdef CONFIG_SMP
 276         orr     r10, r10, #(1 << 6)             @ Enable SMP/nAMP mode
 277         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
 278         ALT_UP(mov      r0, r10)                @ fake it for UP
 279         orr     r10, r10, r0                    @ Set required bits
 280         teq     r10, r0                         @ Were they already set?
 281         mcrne   p15, 0, r10, c1, c0, 1          @ No, update register
 282 #endif
 283         b       __v7_setup_cont
 284
 285 /*
 286  * Errata:
 287  *  r0, r10 available for use
 288  *  r1, r2, r4, r5, r9, r13: must be preserved
 289  *  r3: contains MIDR rX number in bits 23-20
 290  *  r6: contains MIDR rXpY as 8-bit XY number
 291  *  r9: MIDR
 292  */
 293 __ca8_errata:
 294 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 295         teq     r3, #0x00100000                 @ only present in r1p*
 296         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
 297         orreq   r0, r0, #(1 << 6)               @ set IBE to 1
 298         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
 299 #endif
 300 #ifdef CONFIG_ARM_ERRATA_458693
 301         teq     r6, #0x20                       @ only present in r2p0
 302         mrceq   p15, 0, r0, c1, c0, 1           @ read aux control register
 303         orreq   r0, r0, #(1 << 5)               @ set L1NEON to 1
 304         orreq   r0, r0, #(1 << 9)               @ set PLDNOP to 1
 305         mcreq   p15, 0, r0, c1, c0, 1           @ write aux control register
 306 #endif
 307 #ifdef CONFIG_ARM_ERRATA_460075
 308         teq     r6, #0x20                       @ only present in r2p0
 309         mrceq   p15, 1, r0, c9, c0, 2           @ read L2 cache aux ctrl register
 310         tsteq   r0, #1 << 22
 311         orreq   r0, r0, #(1 << 22)              @ set the Write Allocate disable bit
 312         mcreq   p15, 1, r0, c9, c0, 2           @ write the L2 cache aux ctrl register
 313 #endif
 314         b       __errata_finish
 315
 316 __ca9_errata:
 317 #ifdef CONFIG_ARM_ERRATA_742230
 318         cmp     r6, #0x22                       @ only present up to r2p2
 319         mrcle   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 320         orrle   r0, r0, #1 << 4                 @ set bit #4
 321         mcrle   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 322 #endif
 323 #ifdef CONFIG_ARM_ERRATA_742231
 324         teq     r6, #0x20                       @ present in r2p0
 325         teqne   r6, #0x21                       @ present in r2p1
 326         teqne   r6, #0x22                       @ present in r2p2
 327         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 328         orreq   r0, r0, #1 << 12                @ set bit #12
 329         orreq   r0, r0, #1 << 22                @ set bit #22
 330         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 331 #endif
 332 #ifdef CONFIG_ARM_ERRATA_743622
 333         teq     r3, #0x00200000                 @ only present in r2p*
 334         mrceq   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 335         orreq   r0, r0, #1 << 6                 @ set bit #6
 336         mcreq   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 337 #endif
 338 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 339         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
 340         ALT_UP_B(1f)
 341         mrclt   p15, 0, r0, c15, c0, 1          @ read diagnostic register
 342         orrlt   r0, r0, #1 << 11                @ set bit #11
 343         mcrlt   p15, 0, r0, c15, c0, 1          @ write diagnostic register
 344 1:
 345 #endif
 346         b       __errata_finish
 347
 348 __ca15_errata:
 349 #ifdef CONFIG_ARM_ERRATA_773022
 350         cmp     r6, #0x4                        @ only present up to r0p4
 351         mrcle   p15, 0, r0, c1, c0, 1           @ read aux control register
 352         orrle   r0, r0, #1 << 1                 @ disable loop buffer
 353         mcrle   p15, 0, r0, c1, c0, 1           @ write aux control register
 354 #endif
 355         b       __errata_finish
 356
 357 __ca12_errata:
 358 #ifdef CONFIG_ARM_ERRATA_818325_852422
 359         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
 360         orr     r10, r10, #1 << 12              @ set bit #12
 361         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 362 #endif
 363 #ifdef CONFIG_ARM_ERRATA_821420
 364         mrc     p15, 0, r10, c15, c0, 2         @ read internal feature reg
 365         orr     r10, r10, #1 << 1               @ set bit #1
 366         mcr     p15, 0, r10, c15, c0, 2         @ write internal feature reg
 367 #endif
 368 #ifdef CONFIG_ARM_ERRATA_825619
 369         mrc     p15, 0, r10, c15, c0, 1         @ read diagnostic register
 370         orr     r10, r10, #1 << 24              @ set bit #24
 371         mcr     p15, 0, r10, c15, c0, 1         @ write diagnostic register
 372 #endif
 373         b       __errata_finish
 374
 375 __ca17_errata:
 376 #ifdef CONFIG_ARM_ERRATA_852421
 377         cmp     r6, #0x12                       @ only present up to r1p2
 378         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 379         orrle   r10, r10, #1 << 24              @ set bit #24
 380         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 381 #endif
 382 #ifdef CONFIG_ARM_ERRATA_852423
 383         cmp     r6, #0x12                       @ only present up to r1p2
 384         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 385         orrle   r10, r10, #1 << 12              @ set bit #12
 386         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 387 #endif
 388         b       __errata_finish
 389
 390 __v7_pj4b_setup:
 391 #ifdef CONFIG_CPU_PJ4B
 392
 393 /* Auxiliary Debug Modes Control 1 Register */
 394 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 395 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
 396 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 397
 398 /* Auxiliary Debug Modes Control 2 Register */
 399 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
 400 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
 401 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
 402 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
 403 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
 404 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
 405                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
 406
 407 /* Auxiliary Functional Modes Control Register 0 */
 408 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
 409 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
 410 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
 411
 412 /* Auxiliary Debug Modes Control 0 Register */
 413 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
 414
 415         /* Auxiliary Debug Modes Control 1 Register */
 416         mrc     p15, 1, r0, c15, c1, 1
 417         orr     r0, r0, #PJ4B_CLEAN_LINE
 418         orr     r0, r0, #PJ4B_INTER_PARITY
 419         bic     r0, r0, #PJ4B_STATIC_BP
 420         mcr     p15, 1, r0, c15, c1, 1
 421
 422         /* Auxiliary Debug Modes Control 2 Register */
 423         mrc     p15, 1, r0, c15, c1, 2
 424         bic     r0, r0, #PJ4B_FAST_LDR
 425         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
 426         mcr     p15, 1, r0, c15, c1, 2
 427
 428         /* Auxiliary Functional Modes Control Register 0 */
 429         mrc     p15, 1, r0, c15, c2, 0
 430 #ifdef CONFIG_SMP
 431         orr     r0, r0, #PJ4B_SMP_CFB
 432 #endif
 433         orr     r0, r0, #PJ4B_L1_PAR_CHK
 434         orr     r0, r0, #PJ4B_BROADCAST_CACHE
 435         mcr     p15, 1, r0, c15, c2, 0
 436
 437         /* Auxiliary Debug Modes Control 0 Register */
 438         mrc     p15, 1, r0, c15, c1, 0
 439         orr     r0, r0, #PJ4B_WFI_WFE
 440         mcr     p15, 1, r0, c15, c1, 0
 441
 442 #endif /* CONFIG_CPU_PJ4B */
 443
 444 __v7_setup:
 445         adr     r0, __v7_setup_stack_ptr
 446         ldr     r12, [r0]
 447         add     r12, r12, r0                    @ the local stack
 448         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
 449         bl      v7_invalidate_l1
 450         ldmia   r12, {r1-r6, lr}
 451
 452 __v7_setup_cont:
 453         and     r0, r9, #0xff000000             @ ARM?
 454         teq     r0, #0x41000000
 455         bne     __errata_finish
 456         and     r3, r9, #0x00f00000             @ variant
 457         and     r6, r9, #0x0000000f             @ revision
 458         orr     r6, r6, r3, lsr #20-4           @ combine variant and revision
 459         ubfx    r0, r9, #4, #12                 @ primary part number
 460
 461         /* Cortex-A8 Errata */
 462         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
 463         teq     r0, r10
 464         beq     __ca8_errata
 465
 466         /* Cortex-A9 Errata */
 467         ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
 468         teq     r0, r10
 469         beq     __ca9_errata
 470
 471         /* Cortex-A12 Errata */
 472         ldr     r10, =0x00000c0d                @ Cortex-A12 primary part number
 473         teq     r0, r10
 474         beq     __ca12_errata
 475
 476         /* Cortex-A17 Errata */
 477         ldr     r10, =0x00000c0e                @ Cortex-A17 primary part number
 478         teq     r0, r10
 479         beq     __ca17_errata
 480
 481         /* Cortex-A15 Errata */
 482         ldr     r10, =0x00000c0f                @ Cortex-A15 primary part number
 483         teq     r0, r10
 484         beq     __ca15_errata
 485
 486 __errata_finish:
 487         mov     r10, #0
 488         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 489 #ifdef CONFIG_MMU
 490         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 491         v7_ttb_setup r10, r4, r5, r8, r3        @ TTBCR, TTBRx setup
 492         ldr     r3, =PRRR                       @ PRRR
 493         ldr     r6, =NMRR                       @ NMRR
 494         mcr     p15, 0, r3, c10, c2, 0          @ write PRRR
 495         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 496 #endif
 497         dsb                                     @ Complete invalidations
 498 #ifndef CONFIG_ARM_THUMBEE
 499         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
 500         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
 501         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
 502         bne     1f
 503         mov     r3, #0
 504         mcr     p14, 6, r3, c1, c0, 0           @ Initialize TEEHBR to 0
 505         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
 506         orr     r0, r0, #1                      @ set the 1st bit in order to
 507         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
 508 1:
 509 #endif
 510         adr     r3, v7_crval
 511         ldmia   r3, {r3, r6}
 512  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
 513 #ifdef CONFIG_SWP_EMULATE
 514         orr     r3, r3, #(1 << 10)              @ set SW bit in "clear"
 515         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
 516 #endif
 517         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 518         bic     r0, r0, r3                      @ clear bits them
 519         orr     r0, r0, r6                      @ set them
 520  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
 521         ret     lr                              @ return to head.S:__ret
 522
 523         .align  2
 524 __v7_setup_stack_ptr:
 525         .word   PHYS_RELATIVE(__v7_setup_stack, .)
 526 ENDPROC(__v7_setup)
 527
 528         .bss
 529         .align  2
 530 __v7_setup_stack:
 531         .space  4 * 7                           @ 7 registers
 532
 533         __INITDATA
 534
 535         .weak cpu_v7_bugs_init
 536
 537         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 538         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 539
 540 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 541         @ generic v7 bpiall on context switch
 542         globl_equ       cpu_v7_bpiall_proc_init,        cpu_v7_proc_init
 543         globl_equ       cpu_v7_bpiall_proc_fin,         cpu_v7_proc_fin
 544         globl_equ       cpu_v7_bpiall_reset,            cpu_v7_reset
 545         globl_equ       cpu_v7_bpiall_do_idle,          cpu_v7_do_idle
 546         globl_equ       cpu_v7_bpiall_dcache_clean_area, cpu_v7_dcache_clean_area
 547         globl_equ       cpu_v7_bpiall_set_pte_ext,      cpu_v7_set_pte_ext
 548         globl_equ       cpu_v7_bpiall_suspend_size,     cpu_v7_suspend_size
 549 #ifdef CONFIG_ARM_CPU_SUSPEND
 550         globl_equ       cpu_v7_bpiall_do_suspend,       cpu_v7_do_suspend
 551         globl_equ       cpu_v7_bpiall_do_resume,        cpu_v7_do_resume
 552 #endif
 553         define_processor_functions v7_bpiall, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 554
 555 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_bpiall_processor_functions
 556 #else
 557 #define HARDENED_BPIALL_PROCESSOR_FUNCTIONS v7_processor_functions
 558 #endif
 559
 560 #ifndef CONFIG_ARM_LPAE
 561         @ Cortex-A8 - always needs bpiall switch_mm implementation
 562         globl_equ       cpu_ca8_proc_init,      cpu_v7_proc_init
 563         globl_equ       cpu_ca8_proc_fin,       cpu_v7_proc_fin
 564         globl_equ       cpu_ca8_reset,          cpu_v7_reset
 565         globl_equ       cpu_ca8_do_idle,        cpu_v7_do_idle
 566         globl_equ       cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
 567         globl_equ       cpu_ca8_set_pte_ext,    cpu_v7_set_pte_ext
 568         globl_equ       cpu_ca8_switch_mm,      cpu_v7_bpiall_switch_mm
 569         globl_equ       cpu_ca8_suspend_size,   cpu_v7_suspend_size
 570 #ifdef CONFIG_ARM_CPU_SUSPEND
 571         globl_equ       cpu_ca8_do_suspend,     cpu_v7_do_suspend
 572         globl_equ       cpu_ca8_do_resume,      cpu_v7_do_resume
 573 #endif
 574         define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca8_ibe
 575
 576         @ Cortex-A9 - needs more registers preserved across suspend/resume
 577         @ and bpiall switch_mm for hardening
 578         globl_equ       cpu_ca9mp_proc_init,    cpu_v7_proc_init
 579         globl_equ       cpu_ca9mp_proc_fin,     cpu_v7_proc_fin
 580         globl_equ       cpu_ca9mp_reset,        cpu_v7_reset
 581         globl_equ       cpu_ca9mp_do_idle,      cpu_v7_do_idle
 582         globl_equ       cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
 583 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 584         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_bpiall_switch_mm
 585 #else
 586         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_switch_mm
 587 #endif
 588         globl_equ       cpu_ca9mp_set_pte_ext,  cpu_v7_set_pte_ext
 589         define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_bugs_init
 590 #endif
 591
 592         @ Cortex-A15 - needs iciallu switch_mm for hardening
 593         globl_equ       cpu_ca15_proc_init,     cpu_v7_proc_init
 594         globl_equ       cpu_ca15_proc_fin,      cpu_v7_proc_fin
 595         globl_equ       cpu_ca15_reset,         cpu_v7_reset
 596         globl_equ       cpu_ca15_do_idle,       cpu_v7_do_idle
 597         globl_equ       cpu_ca15_dcache_clean_area, cpu_v7_dcache_clean_area
 598 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
 599         globl_equ       cpu_ca15_switch_mm,     cpu_v7_iciallu_switch_mm
 600 #else
 601         globl_equ       cpu_ca15_switch_mm,     cpu_v7_switch_mm
 602 #endif
 603         globl_equ       cpu_ca15_set_pte_ext,   cpu_v7_set_pte_ext
 604         globl_equ       cpu_ca15_suspend_size,  cpu_v7_suspend_size
 605         globl_equ       cpu_ca15_do_suspend,    cpu_v7_do_suspend
 606         globl_equ       cpu_ca15_do_resume,     cpu_v7_do_resume
 607         define_processor_functions ca15, dabort=v7_early_abort, pabort=v7_pabort, suspend=1, bugs=cpu_v7_ca15_ibe
 608 #ifdef CONFIG_CPU_PJ4B
 609         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 610 #endif
 611
 612         .section ".rodata"
 613
 614         string  cpu_arch_name, "armv7"
 615         string  cpu_elf_name, "v7"
 616         .align
 617
 618         .section ".proc.info.init", #alloc
 619
 620         /*
 621          * Standard v7 proc info content
 622          */
 623 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
 624         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 625                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 626         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 627                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
 628         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
 629                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
 630         initfn  \initfunc, \name
 631         .long   cpu_arch_name
 632         .long   cpu_elf_name
 633         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
 634                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
 635         .long   cpu_v7_name
 636         .long   \proc_fns
 637         .long   v7wbi_tlb_fns
 638         .long   v6_user_fns
 639         .long   \cache_fns
 640 .endm
 641
 642 #ifndef CONFIG_ARM_LPAE
 643         /*
 644          * ARM Ltd. Cortex A5 processor.
 645          */
 646         .type   __v7_ca5mp_proc_info, #object
 647 __v7_ca5mp_proc_info:
 648         .long   0x410fc050
 649         .long   0xff0ffff0
 650         __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
 651         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 652
 653         /*
 654          * ARM Ltd. Cortex A9 processor.
 655          */
 656         .type   __v7_ca9mp_proc_info, #object
 657 __v7_ca9mp_proc_info:
 658         .long   0x410fc090
 659         .long   0xff0ffff0
 660         __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
 661         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 662
 663         /*
 664          * ARM Ltd. Cortex A8 processor.
 665          */
 666         .type   __v7_ca8_proc_info, #object
 667 __v7_ca8_proc_info:
 668         .long   0x410fc080
 669         .long   0xff0ffff0
 670         __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
 671         .size   __v7_ca8_proc_info, . - __v7_ca8_proc_info
 672
 673 #endif  /* CONFIG_ARM_LPAE */
 674
 675         /*
 676          * Marvell PJ4B processor.
 677          */
 678 #ifdef CONFIG_CPU_PJ4B
 679         .type   __v7_pj4b_proc_info, #object
 680 __v7_pj4b_proc_info:
 681         .long   0x560f5800
 682         .long   0xff0fff00
 683         __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
 684         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 685 #endif
 686
 687         /*
 688          * ARM Ltd. Cortex R7 processor.
 689          */
 690         .type   __v7_cr7mp_proc_info, #object
 691 __v7_cr7mp_proc_info:
 692         .long   0x410fc170
 693         .long   0xff0ffff0
 694         __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
 695         .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 696
 697         /*
 698          * ARM Ltd. Cortex A7 processor.
 699          */
 700         .type   __v7_ca7mp_proc_info, #object
 701 __v7_ca7mp_proc_info:
 702         .long   0x410fc070
 703         .long   0xff0ffff0
 704         __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
 705         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 706
 707         /*
 708          * ARM Ltd. Cortex A12 processor.
 709          */
 710         .type   __v7_ca12mp_proc_info, #object
 711 __v7_ca12mp_proc_info:
 712         .long   0x410fc0d0
 713         .long   0xff0ffff0
 714         __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 715         .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
 716
 717         /*
 718          * ARM Ltd. Cortex A15 processor.
 719          */
 720         .type   __v7_ca15mp_proc_info, #object
 721 __v7_ca15mp_proc_info:
 722         .long   0x410fc0f0
 723         .long   0xff0ffff0
 724         __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = ca15_processor_functions
 725         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 726
 727         /*
 728          * Broadcom Corporation Brahma-B15 processor.
 729          */
 730         .type   __v7_b15mp_proc_info, #object
 731 __v7_b15mp_proc_info:
 732         .long   0x420f00f0
 733         .long   0xff0ffff0
 734         __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup, proc_fns = ca15_processor_functions, cache_fns = b15_cache_fns
 735         .size   __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
 736
 737         /*
 738          * ARM Ltd. Cortex A17 processor.
 739          */
 740         .type   __v7_ca17mp_proc_info, #object
 741 __v7_ca17mp_proc_info:
 742         .long   0x410fc0e0
 743         .long   0xff0ffff0
 744         __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 745         .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
 746
 747         /* ARM Ltd. Cortex A73 processor */
 748         .type   __v7_ca73_proc_info, #object
 749 __v7_ca73_proc_info:
 750         .long   0x410fd090
 751         .long   0xff0ffff0
 752         __v7_proc __v7_ca73_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 753         .size   __v7_ca73_proc_info, . - __v7_ca73_proc_info
 754
 755         /* ARM Ltd. Cortex A75 processor */
 756         .type   __v7_ca75_proc_info, #object
 757 __v7_ca75_proc_info:
 758         .long   0x410fd0a0
 759         .long   0xff0ffff0
 760         __v7_proc __v7_ca75_proc_info, __v7_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
 761         .size   __v7_ca75_proc_info, . - __v7_ca75_proc_info
 762
 763         /*
 764          * Qualcomm Inc. Krait processors.
 765          */
 766         .type   __krait_proc_info, #object
 767 __krait_proc_info:
 768         .long   0x510f0400              @ Required ID value
 769         .long   0xff0ffc00              @ Mask for ID
 770         /*
 771          * Some Krait processors don't indicate support for SDIV and UDIV
 772          * instructions in the ARM instruction set, even though they actually
 773          * do support them. They also don't indicate support for fused multiply
 774          * instructions even though they actually do support them.
 775          */
 776         __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
 777         .size   __krait_proc_info, . - __krait_proc_info
 778
 779         /*
 780          * Match any ARMv7 processor core.
 781          */
 782         .type   __v7_proc_info, #object
 783 __v7_proc_info:
 784         .long   0x000f0000              @ Required ID value
 785         .long   0x000f0000              @ Mask for ID
 786         __v7_proc __v7_proc_info, __v7_setup
 787         .size   __v7_proc_info, . - __v7_proc_info