1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v6.S
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Modified by Catalin Marinas for noMMU support
8 * This is the "shell" of the ARMv6 processor support.
10 #include <linux/init.h>
11 #include <linux/linkage.h>
12 #include <linux/pgtable.h>
13 #include <asm/assembler.h>
14 #include <asm/asm-offsets.h>
15 #include <asm/hwcap.h>
16 #include <asm/pgtable-hwdef.h>
18 #include "proc-macros.S"
20 #define D_CACHE_LINE_SIZE 32
22 #define TTB_C (1 << 0)
23 #define TTB_S (1 << 1)
24 #define TTB_IMP (1 << 2)
25 #define TTB_RGN_NC (0 << 3)
26 #define TTB_RGN_WBWA (1 << 3)
27 #define TTB_RGN_WT (2 << 3)
28 #define TTB_RGN_WB (3 << 3)
30 #define TTB_FLAGS_UP TTB_RGN_WBWA
31 #define PMD_FLAGS_UP PMD_SECT_WB
32 #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
33 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
37 ENTRY(cpu_v6_proc_init)
40 ENTRY(cpu_v6_proc_fin)
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 bic r0, r0, #0x1000 @ ...i............
43 bic r0, r0, #0x0006 @ .............ca.
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
50 * Perform a soft reset of the system. Put the CPU into the
51 * same state as it would be if it had been reset, and branch
52 * to what would be the reset vector.
54 * - loc - location to jump to for soft reset
57 .pushsection .idmap.text, "ax"
59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
60 bic r1, r1, #0x1 @ ...............m
61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
63 mcr p15, 0, r1, c7, c5, 4 @ ISB
71 * Idle the processor (eg, wait for interrupt).
73 * IRQs are already disabled.
77 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
81 ENTRY(cpu_v6_dcache_clean_area)
82 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
83 add r0, r0, #D_CACHE_LINE_SIZE
84 subs r1, r1, #D_CACHE_LINE_SIZE
89 * cpu_v6_switch_mm(pgd_phys, tsk)
91 * Set the translation table base pointer to be pgd_phys
93 * - pgd_phys - physical address of new TTB
96 * - we are not using split page tables
98 ENTRY(cpu_v6_switch_mm)
101 mmid r1, r1 @ get mm->context.id
102 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
103 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
104 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
105 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
107 #ifdef CONFIG_PID_IN_CONTEXTIDR
108 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
109 bic r2, r2, #0xff @ extract the PID
111 orr r1, r1, r2 @ insert into new context ID
113 mcr p15, 0, r1, c13, c0, 1 @ set context ID
118 * cpu_v6_set_pte_ext(ptep, pte, ext)
120 * Set a level 2 translation table entry.
122 * - ptep - pointer to level 2 translation table entry
123 * (hardware version is stored at -1024 bytes)
124 * - pte - PTE value to store
125 * - ext - value for extended PTE bits
127 armv6_mt_table cpu_v6
129 ENTRY(cpu_v6_set_pte_ext)
131 armv6_set_pte_ext cpu_v6
135 /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
136 .globl cpu_v6_suspend_size
137 .equ cpu_v6_suspend_size, 4 * 6
138 #ifdef CONFIG_ARM_CPU_SUSPEND
139 ENTRY(cpu_v6_do_suspend)
140 stmfd sp!, {r4 - r9, lr}
141 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
143 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
144 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
146 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
147 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
148 mrc p15, 0, r9, c1, c0, 0 @ control register
150 ldmfd sp!, {r4- r9, pc}
151 ENDPROC(cpu_v6_do_suspend)
153 ENTRY(cpu_v6_do_resume)
155 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
156 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
158 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
159 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
161 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
163 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
164 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
165 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
166 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
167 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
168 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
170 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
171 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
172 mcr p15, 0, ip, c7, c5, 4 @ ISB
173 mov r0, r9 @ control register
175 ENDPROC(cpu_v6_do_resume)
178 string cpu_v6_name, "ARMv6-compatible processor"
185 * Initialise TLB, Caches, and MMU state ready to switch the MMU
186 * on. Return in r0 the new CP15 C1 control register setting.
188 * We automatically detect if we have a Harvard cache, and use the
189 * Harvard cache control instructions insead of the unified cache
190 * control instructions.
192 * This should be able to cover all ARMv6 cores.
194 * It is assumed that:
195 * - cache type register is implemented
199 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
202 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
207 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
208 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
209 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
211 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
212 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
213 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
214 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
215 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
216 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
217 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
218 #endif /* CONFIG_MMU */
219 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
220 @ complete invalidations
223 ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
224 mrc p15, 0, r0, c1, c0, 0 @ read control register
225 bic r0, r0, r5 @ clear bits them
226 orr r0, r0, r6 @ set them
227 #ifdef CONFIG_ARM_ERRATA_364296
229 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
230 * corruption with hit-under-miss enabled). The conditional code below
231 * (setting the undocumented bit 31 in the auxiliary control register
232 * and the FI bit in the control register) disables hit-under-miss
233 * without putting the processor into full low interrupt latency mode.
235 ldr r6, =0x4107b362 @ id for ARM1136 r0p2
236 mrc p15, 0, r5, c0, c0, 0 @ get processor id
237 teq r5, r6 @ check for the faulty core
238 mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
239 orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
240 mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
241 orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
243 ret lr @ return to head.S:__ret
247 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
248 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
249 * 0 110 0011 1.00 .111 1101 < we want
251 .type v6_crval, #object
253 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
257 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
258 define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
262 string cpu_arch_name, "armv6"
263 string cpu_elf_name, "v6"
266 .section ".proc.info.init", "a"
269 * Match any ARMv6 processor core.
271 .type __v6_proc_info, #object
277 PMD_SECT_AP_WRITE | \
282 PMD_SECT_AP_WRITE | \
285 .long PMD_TYPE_SECT | \
287 PMD_SECT_AP_WRITE | \
289 initfn __v6_setup, __v6_proc_info
292 /* See also feat_v6_fixup() for HWCAP_TLS */
293 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
295 .long v6_processor_functions
299 .size __v6_proc_info, . - __v6_proc_info