2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
46 * The DMA API is built upon the notion of "buffer ownership". A buffer
47 * is either exclusively owned by the CPU (and therefore may be accessed
48 * by it) or exclusively owned by the DMA device. These helper functions
49 * represent the transitions between these two ownership states.
51 * Note, however, that on later ARMs, this notion does not work due to
52 * speculative prefetches. We model our approach on the assumption that
53 * the CPU does do speculative prefetches, which means we clean caches
54 * before transfers and delay cache invalidation until transfer completion.
57 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
58 size_t, enum dma_data_direction);
59 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
60 size_t, enum dma_data_direction);
63 * arm_dma_map_page - map a portion of a page for streaming DMA
64 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
65 * @page: page that buffer resides in
66 * @offset: offset into page for start of buffer
67 * @size: size of buffer to map
68 * @dir: DMA transfer direction
70 * Ensure that any data held in the cache is appropriately discarded
73 * The device owns this memory once this call has completed. The CPU
74 * can regain ownership by calling dma_unmap_page().
76 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
77 unsigned long offset, size_t size, enum dma_data_direction dir,
78 struct dma_attrs *attrs)
80 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
81 __dma_page_cpu_to_dev(page, offset, size, dir);
82 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
85 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
86 unsigned long offset, size_t size, enum dma_data_direction dir,
87 struct dma_attrs *attrs)
89 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
93 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
94 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
95 * @handle: DMA address of buffer
96 * @size: size of buffer (same as passed to dma_map_page)
97 * @dir: DMA transfer direction (same as passed to dma_map_page)
99 * Unmap a page streaming mode DMA translation. The handle and size
100 * must match what was provided in the previous dma_map_page() call.
101 * All other usages are undefined.
103 * After this call, reads by the CPU to the buffer are guaranteed to see
104 * whatever the device wrote there.
106 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
107 size_t size, enum dma_data_direction dir,
108 struct dma_attrs *attrs)
110 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
111 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
112 handle & ~PAGE_MASK, size, dir);
115 static void arm_dma_sync_single_for_cpu(struct device *dev,
116 dma_addr_t handle, size_t size, enum dma_data_direction dir)
118 unsigned int offset = handle & (PAGE_SIZE - 1);
119 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
120 __dma_page_dev_to_cpu(page, offset, size, dir);
123 static void arm_dma_sync_single_for_device(struct device *dev,
124 dma_addr_t handle, size_t size, enum dma_data_direction dir)
126 unsigned int offset = handle & (PAGE_SIZE - 1);
127 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
128 __dma_page_cpu_to_dev(page, offset, size, dir);
131 struct dma_map_ops arm_dma_ops = {
132 .alloc = arm_dma_alloc,
133 .free = arm_dma_free,
134 .mmap = arm_dma_mmap,
135 .get_sgtable = arm_dma_get_sgtable,
136 .map_page = arm_dma_map_page,
137 .unmap_page = arm_dma_unmap_page,
138 .map_sg = arm_dma_map_sg,
139 .unmap_sg = arm_dma_unmap_sg,
140 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
141 .sync_single_for_device = arm_dma_sync_single_for_device,
142 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
143 .sync_sg_for_device = arm_dma_sync_sg_for_device,
144 .set_dma_mask = arm_dma_set_mask,
146 EXPORT_SYMBOL(arm_dma_ops);
148 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
149 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
150 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
151 dma_addr_t handle, struct dma_attrs *attrs);
152 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
153 void *cpu_addr, dma_addr_t dma_addr, size_t size,
154 struct dma_attrs *attrs);
156 struct dma_map_ops arm_coherent_dma_ops = {
157 .alloc = arm_coherent_dma_alloc,
158 .free = arm_coherent_dma_free,
159 .mmap = arm_coherent_dma_mmap,
160 .get_sgtable = arm_dma_get_sgtable,
161 .map_page = arm_coherent_dma_map_page,
162 .map_sg = arm_dma_map_sg,
163 .set_dma_mask = arm_dma_set_mask,
165 EXPORT_SYMBOL(arm_coherent_dma_ops);
167 static int __dma_supported(struct device *dev, u64 mask, bool warn)
169 unsigned long max_dma_pfn;
172 * If the mask allows for more memory than we can address,
173 * and we actually have that much memory, then we must
174 * indicate that DMA to this device is not supported.
176 if (sizeof(mask) != sizeof(dma_addr_t) &&
177 mask > (dma_addr_t)~0 &&
178 dma_to_pfn(dev, ~0) < max_pfn - 1) {
180 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
182 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
187 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
190 * Translate the device's DMA mask to a PFN limit. This
191 * PFN number includes the page which we can DMA to.
193 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
195 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
197 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
205 static u64 get_coherent_dma_mask(struct device *dev)
207 u64 mask = (u64)DMA_BIT_MASK(32);
210 mask = dev->coherent_dma_mask;
213 * Sanity check the DMA mask - it must be non-zero, and
214 * must be able to be satisfied by a DMA allocation.
217 dev_warn(dev, "coherent DMA mask is unset\n");
221 if (!__dma_supported(dev, mask, true))
228 static void __dma_clear_buffer(struct page *page, size_t size)
231 * Ensure that the allocated pages are zeroed, and that any data
232 * lurking in the kernel direct-mapped region is invalidated.
234 if (PageHighMem(page)) {
235 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
236 phys_addr_t end = base + size;
238 void *ptr = kmap_atomic(page);
239 memset(ptr, 0, PAGE_SIZE);
240 dmac_flush_range(ptr, ptr + PAGE_SIZE);
245 outer_flush_range(base, end);
247 void *ptr = page_address(page);
248 memset(ptr, 0, size);
249 dmac_flush_range(ptr, ptr + size);
250 outer_flush_range(__pa(ptr), __pa(ptr) + size);
255 * Allocate a DMA buffer for 'dev' of size 'size' using the
256 * specified gfp mask. Note that 'size' must be page aligned.
258 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
260 unsigned long order = get_order(size);
261 struct page *page, *p, *e;
263 page = alloc_pages(gfp, order);
268 * Now split the huge page and free the excess pages
270 split_page(page, order);
271 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
274 __dma_clear_buffer(page, size);
280 * Free a DMA buffer. 'size' must be page aligned.
282 static void __dma_free_buffer(struct page *page, size_t size)
284 struct page *e = page + (size >> PAGE_SHIFT);
294 static void *__alloc_from_contiguous(struct device *dev, size_t size,
295 pgprot_t prot, struct page **ret_page,
296 const void *caller, bool want_vaddr);
298 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
299 pgprot_t prot, struct page **ret_page,
300 const void *caller, bool want_vaddr);
303 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
307 * DMA allocation can be mapped to user space, so lets
308 * set VM_USERMAP flags too.
310 return dma_common_contiguous_remap(page, size,
311 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
315 static void __dma_free_remap(void *cpu_addr, size_t size)
317 dma_common_free_remap(cpu_addr, size,
318 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
321 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
322 static struct gen_pool *atomic_pool;
324 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
326 static int __init early_coherent_pool(char *p)
328 atomic_pool_size = memparse(p, &p);
331 early_param("coherent_pool", early_coherent_pool);
333 void __init init_dma_coherent_pool_size(unsigned long size)
336 * Catch any attempt to set the pool size too late.
341 * Set architecture specific coherent pool size only if
342 * it has not been changed by kernel command line parameter.
344 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
345 atomic_pool_size = size;
349 * Initialise the coherent pool for atomic allocations.
351 static int __init atomic_pool_init(void)
353 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
354 gfp_t gfp = GFP_KERNEL | GFP_DMA;
358 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
362 if (dev_get_cma_area(NULL))
363 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
364 &page, atomic_pool_init, true);
366 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
367 &page, atomic_pool_init, true);
371 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
373 atomic_pool_size, -1);
375 goto destroy_genpool;
377 gen_pool_set_algo(atomic_pool,
378 gen_pool_first_fit_order_align,
380 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
381 atomic_pool_size / 1024);
386 gen_pool_destroy(atomic_pool);
389 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
390 atomic_pool_size / 1024);
394 * CMA is activated by core_initcall, so we must be called after it.
396 postcore_initcall(atomic_pool_init);
398 struct dma_contig_early_reserve {
403 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
405 static int dma_mmu_remap_num __initdata;
407 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
409 dma_mmu_remap[dma_mmu_remap_num].base = base;
410 dma_mmu_remap[dma_mmu_remap_num].size = size;
414 void __init dma_contiguous_remap(void)
417 for (i = 0; i < dma_mmu_remap_num; i++) {
418 phys_addr_t start = dma_mmu_remap[i].base;
419 phys_addr_t end = start + dma_mmu_remap[i].size;
423 if (end > arm_lowmem_limit)
424 end = arm_lowmem_limit;
428 map.pfn = __phys_to_pfn(start);
429 map.virtual = __phys_to_virt(start);
430 map.length = end - start;
431 map.type = MT_MEMORY_DMA_READY;
434 * Clear previous low-memory mapping to ensure that the
435 * TLB does not see any conflicting entries, then flush
436 * the TLB of the old entries before creating new mappings.
438 * This ensures that any speculatively loaded TLB entries
439 * (even though they may be rare) can not cause any problems,
440 * and ensures that this code is architecturally compliant.
442 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
444 pmd_clear(pmd_off_k(addr));
446 flush_tlb_kernel_range(__phys_to_virt(start),
447 __phys_to_virt(end));
449 iotable_init(&map, 1);
453 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
456 struct page *page = virt_to_page(addr);
457 pgprot_t prot = *(pgprot_t *)data;
459 set_pte_ext(pte, mk_pte(page, prot), 0);
463 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
465 unsigned long start = (unsigned long) page_address(page);
466 unsigned end = start + size;
468 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
469 flush_tlb_kernel_range(start, end);
472 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
473 pgprot_t prot, struct page **ret_page,
474 const void *caller, bool want_vaddr)
478 page = __dma_alloc_buffer(dev, size, gfp);
484 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
486 __dma_free_buffer(page, size);
495 static void *__alloc_from_pool(size_t size, struct page **ret_page)
501 WARN(1, "coherent pool not initialised!\n");
505 val = gen_pool_alloc(atomic_pool, size);
507 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
509 *ret_page = phys_to_page(phys);
516 static bool __in_atomic_pool(void *start, size_t size)
518 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
521 static int __free_from_pool(void *start, size_t size)
523 if (!__in_atomic_pool(start, size))
526 gen_pool_free(atomic_pool, (unsigned long)start, size);
531 static void *__alloc_from_contiguous(struct device *dev, size_t size,
532 pgprot_t prot, struct page **ret_page,
533 const void *caller, bool want_vaddr)
535 unsigned long order = get_order(size);
536 size_t count = size >> PAGE_SHIFT;
540 page = dma_alloc_from_contiguous(dev, count, order);
544 __dma_clear_buffer(page, size);
549 if (PageHighMem(page)) {
550 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
552 dma_release_from_contiguous(dev, page, count);
556 __dma_remap(page, size, prot);
557 ptr = page_address(page);
565 static void __free_from_contiguous(struct device *dev, struct page *page,
566 void *cpu_addr, size_t size, bool want_vaddr)
569 if (PageHighMem(page))
570 __dma_free_remap(cpu_addr, size);
572 __dma_remap(page, size, PAGE_KERNEL);
574 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
577 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
579 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
580 pgprot_writecombine(prot) :
581 pgprot_dmacoherent(prot);
587 #else /* !CONFIG_MMU */
591 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
592 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
593 #define __alloc_from_pool(size, ret_page) NULL
594 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL
595 #define __free_from_pool(cpu_addr, size) 0
596 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
597 #define __dma_free_remap(cpu_addr, size) do { } while (0)
599 #endif /* CONFIG_MMU */
601 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
602 struct page **ret_page)
605 page = __dma_alloc_buffer(dev, size, gfp);
610 return page_address(page);
615 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
616 gfp_t gfp, pgprot_t prot, bool is_coherent,
617 struct dma_attrs *attrs, const void *caller)
619 u64 mask = get_coherent_dma_mask(dev);
620 struct page *page = NULL;
624 #ifdef CONFIG_DMA_API_DEBUG
625 u64 limit = (mask + 1) & ~mask;
626 if (limit && size >= limit) {
627 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
636 if (mask < 0xffffffffULL)
640 * Following is a work-around (a.k.a. hack) to prevent pages
641 * with __GFP_COMP being passed to split_page() which cannot
642 * handle them. The real problem is that this flag probably
643 * should be 0 on ARM as it is not supported on this
644 * platform; see CONFIG_HUGETLBFS.
646 gfp &= ~(__GFP_COMP);
648 *handle = DMA_ERROR_CODE;
649 size = PAGE_ALIGN(size);
650 want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
653 addr = __alloc_simple_buffer(dev, size, gfp, &page);
654 else if (dev_get_cma_area(dev) && (gfp & __GFP_WAIT))
655 addr = __alloc_from_contiguous(dev, size, prot, &page,
657 else if (is_coherent)
658 addr = __alloc_simple_buffer(dev, size, gfp, &page);
659 else if (!(gfp & __GFP_WAIT))
660 addr = __alloc_from_pool(size, &page);
662 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page,
666 *handle = pfn_to_dma(dev, page_to_pfn(page));
668 return want_vaddr ? addr : page;
672 * Allocate DMA-coherent memory space and return both the kernel remapped
673 * virtual and bus address for that space.
675 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
676 gfp_t gfp, struct dma_attrs *attrs)
678 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
681 if (dma_alloc_from_coherent(dev, size, handle, &memory))
684 return __dma_alloc(dev, size, handle, gfp, prot, false,
685 attrs, __builtin_return_address(0));
688 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
689 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
693 if (dma_alloc_from_coherent(dev, size, handle, &memory))
696 return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true,
697 attrs, __builtin_return_address(0));
700 static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
701 void *cpu_addr, dma_addr_t dma_addr, size_t size,
702 struct dma_attrs *attrs)
706 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
707 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
708 unsigned long pfn = dma_to_pfn(dev, dma_addr);
709 unsigned long off = vma->vm_pgoff;
711 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
714 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
715 ret = remap_pfn_range(vma, vma->vm_start,
717 vma->vm_end - vma->vm_start,
720 #endif /* CONFIG_MMU */
726 * Create userspace mapping for the DMA-coherent memory.
728 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
729 void *cpu_addr, dma_addr_t dma_addr, size_t size,
730 struct dma_attrs *attrs)
732 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
735 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
736 void *cpu_addr, dma_addr_t dma_addr, size_t size,
737 struct dma_attrs *attrs)
740 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
741 #endif /* CONFIG_MMU */
742 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
746 * Free a buffer as defined by the above mapping.
748 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
749 dma_addr_t handle, struct dma_attrs *attrs,
752 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
753 bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
755 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
758 size = PAGE_ALIGN(size);
761 __dma_free_buffer(page, size);
762 } else if (!is_coherent && __free_from_pool(cpu_addr, size)) {
764 } else if (!dev_get_cma_area(dev)) {
765 if (want_vaddr && !is_coherent)
766 __dma_free_remap(cpu_addr, size);
767 __dma_free_buffer(page, size);
770 * Non-atomic allocations cannot be freed with IRQs disabled
772 WARN_ON(irqs_disabled());
773 __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr);
777 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
778 dma_addr_t handle, struct dma_attrs *attrs)
780 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
783 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
784 dma_addr_t handle, struct dma_attrs *attrs)
786 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
789 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
790 void *cpu_addr, dma_addr_t handle, size_t size,
791 struct dma_attrs *attrs)
793 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
796 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
800 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
804 static void dma_cache_maint_page(struct page *page, unsigned long offset,
805 size_t size, enum dma_data_direction dir,
806 void (*op)(const void *, size_t, int))
811 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
815 * A single sg entry may refer to multiple physically contiguous
816 * pages. But we still need to process highmem pages individually.
817 * If highmem is not configured then the bulk of this loop gets
824 page = pfn_to_page(pfn);
826 if (PageHighMem(page)) {
827 if (len + offset > PAGE_SIZE)
828 len = PAGE_SIZE - offset;
830 if (cache_is_vipt_nonaliasing()) {
831 vaddr = kmap_atomic(page);
832 op(vaddr + offset, len, dir);
833 kunmap_atomic(vaddr);
835 vaddr = kmap_high_get(page);
837 op(vaddr + offset, len, dir);
842 vaddr = page_address(page) + offset;
852 * Make an area consistent for devices.
853 * Note: Drivers should NOT use this function directly, as it will break
854 * platforms with CONFIG_DMABOUNCE.
855 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
857 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
858 size_t size, enum dma_data_direction dir)
862 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
864 paddr = page_to_phys(page) + off;
865 if (dir == DMA_FROM_DEVICE) {
866 outer_inv_range(paddr, paddr + size);
868 outer_clean_range(paddr, paddr + size);
870 /* FIXME: non-speculating: flush on bidirectional mappings? */
873 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
874 size_t size, enum dma_data_direction dir)
876 phys_addr_t paddr = page_to_phys(page) + off;
878 /* FIXME: non-speculating: not required */
879 /* in any case, don't bother invalidating if DMA to device */
880 if (dir != DMA_TO_DEVICE) {
881 outer_inv_range(paddr, paddr + size);
883 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
887 * Mark the D-cache clean for these pages to avoid extra flushing.
889 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
893 pfn = page_to_pfn(page) + off / PAGE_SIZE;
897 left -= PAGE_SIZE - off;
899 while (left >= PAGE_SIZE) {
900 page = pfn_to_page(pfn++);
901 set_bit(PG_dcache_clean, &page->flags);
908 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
909 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
910 * @sg: list of buffers
911 * @nents: number of buffers to map
912 * @dir: DMA transfer direction
914 * Map a set of buffers described by scatterlist in streaming mode for DMA.
915 * This is the scatter-gather version of the dma_map_single interface.
916 * Here the scatter gather list elements are each tagged with the
917 * appropriate dma address and length. They are obtained via
918 * sg_dma_{address,length}.
920 * Device ownership issues as mentioned for dma_map_single are the same
923 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
924 enum dma_data_direction dir, struct dma_attrs *attrs)
926 struct dma_map_ops *ops = get_dma_ops(dev);
927 struct scatterlist *s;
930 for_each_sg(sg, s, nents, i) {
931 #ifdef CONFIG_NEED_SG_DMA_LENGTH
932 s->dma_length = s->length;
934 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
935 s->length, dir, attrs);
936 if (dma_mapping_error(dev, s->dma_address))
942 for_each_sg(sg, s, i, j)
943 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
948 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
949 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
950 * @sg: list of buffers
951 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
952 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
954 * Unmap a set of streaming mode DMA translations. Again, CPU access
955 * rules concerning calls here are the same as for dma_unmap_single().
957 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
958 enum dma_data_direction dir, struct dma_attrs *attrs)
960 struct dma_map_ops *ops = get_dma_ops(dev);
961 struct scatterlist *s;
965 for_each_sg(sg, s, nents, i)
966 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
970 * arm_dma_sync_sg_for_cpu
971 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
972 * @sg: list of buffers
973 * @nents: number of buffers to map (returned from dma_map_sg)
974 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
976 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
977 int nents, enum dma_data_direction dir)
979 struct dma_map_ops *ops = get_dma_ops(dev);
980 struct scatterlist *s;
983 for_each_sg(sg, s, nents, i)
984 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
989 * arm_dma_sync_sg_for_device
990 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
991 * @sg: list of buffers
992 * @nents: number of buffers to map (returned from dma_map_sg)
993 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
995 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
996 int nents, enum dma_data_direction dir)
998 struct dma_map_ops *ops = get_dma_ops(dev);
999 struct scatterlist *s;
1002 for_each_sg(sg, s, nents, i)
1003 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1008 * Return whether the given device DMA address mask can be supported
1009 * properly. For example, if your device can only drive the low 24-bits
1010 * during bus mastering, then you would pass 0x00ffffff as the mask
1013 int dma_supported(struct device *dev, u64 mask)
1015 return __dma_supported(dev, mask, false);
1017 EXPORT_SYMBOL(dma_supported);
1019 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1021 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1024 *dev->dma_mask = dma_mask;
1029 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1031 static int __init dma_debug_do_init(void)
1033 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1036 fs_initcall(dma_debug_do_init);
1038 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1042 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1044 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1047 unsigned int order = get_order(size);
1048 unsigned int align = 0;
1049 unsigned int count, start;
1050 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1051 unsigned long flags;
1055 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1056 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1058 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1059 align = (1 << order) - 1;
1061 spin_lock_irqsave(&mapping->lock, flags);
1062 for (i = 0; i < mapping->nr_bitmaps; i++) {
1063 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1064 mapping->bits, 0, count, align);
1066 if (start > mapping->bits)
1069 bitmap_set(mapping->bitmaps[i], start, count);
1074 * No unused range found. Try to extend the existing mapping
1075 * and perform a second attempt to reserve an IO virtual
1076 * address range of size bytes.
1078 if (i == mapping->nr_bitmaps) {
1079 if (extend_iommu_mapping(mapping)) {
1080 spin_unlock_irqrestore(&mapping->lock, flags);
1081 return DMA_ERROR_CODE;
1084 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1085 mapping->bits, 0, count, align);
1087 if (start > mapping->bits) {
1088 spin_unlock_irqrestore(&mapping->lock, flags);
1089 return DMA_ERROR_CODE;
1092 bitmap_set(mapping->bitmaps[i], start, count);
1094 spin_unlock_irqrestore(&mapping->lock, flags);
1096 iova = mapping->base + (mapping_size * i);
1097 iova += start << PAGE_SHIFT;
1102 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1103 dma_addr_t addr, size_t size)
1105 unsigned int start, count;
1106 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1107 unsigned long flags;
1108 dma_addr_t bitmap_base;
1114 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1115 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1117 bitmap_base = mapping->base + mapping_size * bitmap_index;
1119 start = (addr - bitmap_base) >> PAGE_SHIFT;
1121 if (addr + size > bitmap_base + mapping_size) {
1123 * The address range to be freed reaches into the iova
1124 * range of the next bitmap. This should not happen as
1125 * we don't allow this in __alloc_iova (at the
1130 count = size >> PAGE_SHIFT;
1132 spin_lock_irqsave(&mapping->lock, flags);
1133 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1134 spin_unlock_irqrestore(&mapping->lock, flags);
1137 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1138 gfp_t gfp, struct dma_attrs *attrs)
1140 struct page **pages;
1141 int count = size >> PAGE_SHIFT;
1142 int array_size = count * sizeof(struct page *);
1145 if (array_size <= PAGE_SIZE)
1146 pages = kzalloc(array_size, GFP_KERNEL);
1148 pages = vzalloc(array_size);
1152 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1154 unsigned long order = get_order(size);
1157 page = dma_alloc_from_contiguous(dev, count, order);
1161 __dma_clear_buffer(page, size);
1163 for (i = 0; i < count; i++)
1164 pages[i] = page + i;
1170 * IOMMU can map any pages, so himem can also be used here
1172 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1177 for (order = __fls(count); order > 0; --order) {
1179 * We do not want OOM killer to be invoked as long
1180 * as we can fall back to single pages, so we force
1181 * __GFP_NORETRY for orders higher than zero.
1183 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1190 * Fall back to single page allocation.
1191 * Might invoke OOM killer as last resort.
1193 pages[i] = alloc_pages(gfp, 0);
1199 split_page(pages[i], order);
1202 pages[i + j] = pages[i] + j;
1205 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1207 count -= 1 << order;
1214 __free_pages(pages[i], 0);
1215 if (array_size <= PAGE_SIZE)
1222 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1223 size_t size, struct dma_attrs *attrs)
1225 int count = size >> PAGE_SHIFT;
1226 int array_size = count * sizeof(struct page *);
1229 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1230 dma_release_from_contiguous(dev, pages[0], count);
1232 for (i = 0; i < count; i++)
1234 __free_pages(pages[i], 0);
1237 if (array_size <= PAGE_SIZE)
1245 * Create a CPU mapping for a specified pages
1248 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1251 return dma_common_pages_remap(pages, size,
1252 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1256 * Create a mapping in device IO address space for specified pages
1259 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1261 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1262 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1263 dma_addr_t dma_addr, iova;
1264 int i, ret = DMA_ERROR_CODE;
1266 dma_addr = __alloc_iova(mapping, size);
1267 if (dma_addr == DMA_ERROR_CODE)
1271 for (i = 0; i < count; ) {
1272 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1273 phys_addr_t phys = page_to_phys(pages[i]);
1274 unsigned int len, j;
1276 for (j = i + 1; j < count; j++, next_pfn++)
1277 if (page_to_pfn(pages[j]) != next_pfn)
1280 len = (j - i) << PAGE_SHIFT;
1281 ret = iommu_map(mapping->domain, iova, phys, len,
1282 IOMMU_READ|IOMMU_WRITE);
1290 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1291 __free_iova(mapping, dma_addr, size);
1292 return DMA_ERROR_CODE;
1295 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1297 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1300 * add optional in-page offset from iova to size and align
1301 * result to page size
1303 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1306 iommu_unmap(mapping->domain, iova, size);
1307 __free_iova(mapping, iova, size);
1311 static struct page **__atomic_get_pages(void *addr)
1316 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1317 page = phys_to_page(phys);
1319 return (struct page **)page;
1322 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1324 struct vm_struct *area;
1326 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1327 return __atomic_get_pages(cpu_addr);
1329 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1332 area = find_vm_area(cpu_addr);
1333 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1338 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1344 addr = __alloc_from_pool(size, &page);
1348 *handle = __iommu_create_mapping(dev, &page, size);
1349 if (*handle == DMA_ERROR_CODE)
1355 __free_from_pool(addr, size);
1359 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1360 dma_addr_t handle, size_t size)
1362 __iommu_remove_mapping(dev, handle, size);
1363 __free_from_pool(cpu_addr, size);
1366 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1367 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1369 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1370 struct page **pages;
1373 *handle = DMA_ERROR_CODE;
1374 size = PAGE_ALIGN(size);
1376 if (!(gfp & __GFP_WAIT))
1377 return __iommu_alloc_atomic(dev, size, handle);
1380 * Following is a work-around (a.k.a. hack) to prevent pages
1381 * with __GFP_COMP being passed to split_page() which cannot
1382 * handle them. The real problem is that this flag probably
1383 * should be 0 on ARM as it is not supported on this
1384 * platform; see CONFIG_HUGETLBFS.
1386 gfp &= ~(__GFP_COMP);
1388 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1392 *handle = __iommu_create_mapping(dev, pages, size);
1393 if (*handle == DMA_ERROR_CODE)
1396 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1399 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1400 __builtin_return_address(0));
1407 __iommu_remove_mapping(dev, *handle, size);
1409 __iommu_free_buffer(dev, pages, size, attrs);
1413 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1414 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1415 struct dma_attrs *attrs)
1417 unsigned long uaddr = vma->vm_start;
1418 unsigned long usize = vma->vm_end - vma->vm_start;
1419 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1421 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1427 int ret = vm_insert_page(vma, uaddr, *pages++);
1429 pr_err("Remapping memory failed: %d\n", ret);
1434 } while (usize > 0);
1440 * free a page as defined by the above mapping.
1441 * Must not be called with IRQs disabled.
1443 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1444 dma_addr_t handle, struct dma_attrs *attrs)
1446 struct page **pages;
1447 size = PAGE_ALIGN(size);
1449 if (__in_atomic_pool(cpu_addr, size)) {
1450 __iommu_free_atomic(dev, cpu_addr, handle, size);
1454 pages = __iommu_get_pages(cpu_addr, attrs);
1456 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1460 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1461 dma_common_free_remap(cpu_addr, size,
1462 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1465 __iommu_remove_mapping(dev, handle, size);
1466 __iommu_free_buffer(dev, pages, size, attrs);
1469 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1470 void *cpu_addr, dma_addr_t dma_addr,
1471 size_t size, struct dma_attrs *attrs)
1473 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1474 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1479 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1483 static int __dma_direction_to_prot(enum dma_data_direction dir)
1488 case DMA_BIDIRECTIONAL:
1489 prot = IOMMU_READ | IOMMU_WRITE;
1494 case DMA_FROM_DEVICE:
1505 * Map a part of the scatter-gather list into contiguous io address space
1507 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1508 size_t size, dma_addr_t *handle,
1509 enum dma_data_direction dir, struct dma_attrs *attrs,
1512 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1513 dma_addr_t iova, iova_base;
1516 struct scatterlist *s;
1519 size = PAGE_ALIGN(size);
1520 *handle = DMA_ERROR_CODE;
1522 iova_base = iova = __alloc_iova(mapping, size);
1523 if (iova == DMA_ERROR_CODE)
1526 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1527 phys_addr_t phys = sg_phys(s) & PAGE_MASK;
1528 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1531 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1532 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1534 prot = __dma_direction_to_prot(dir);
1536 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1539 count += len >> PAGE_SHIFT;
1542 *handle = iova_base;
1546 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1547 __free_iova(mapping, iova_base, size);
1551 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1552 enum dma_data_direction dir, struct dma_attrs *attrs,
1555 struct scatterlist *s = sg, *dma = sg, *start = sg;
1557 unsigned int offset = s->offset;
1558 unsigned int size = s->offset + s->length;
1559 unsigned int max = dma_get_max_seg_size(dev);
1561 for (i = 1; i < nents; i++) {
1564 s->dma_address = DMA_ERROR_CODE;
1567 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1568 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1569 dir, attrs, is_coherent) < 0)
1572 dma->dma_address += offset;
1573 dma->dma_length = size - offset;
1575 size = offset = s->offset;
1582 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1586 dma->dma_address += offset;
1587 dma->dma_length = size - offset;
1592 for_each_sg(sg, s, count, i)
1593 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1598 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1599 * @dev: valid struct device pointer
1600 * @sg: list of buffers
1601 * @nents: number of buffers to map
1602 * @dir: DMA transfer direction
1604 * Map a set of i/o coherent buffers described by scatterlist in streaming
1605 * mode for DMA. The scatter gather list elements are merged together (if
1606 * possible) and tagged with the appropriate dma address and length. They are
1607 * obtained via sg_dma_{address,length}.
1609 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1610 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1612 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1616 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1617 * @dev: valid struct device pointer
1618 * @sg: list of buffers
1619 * @nents: number of buffers to map
1620 * @dir: DMA transfer direction
1622 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1623 * The scatter gather list elements are merged together (if possible) and
1624 * tagged with the appropriate dma address and length. They are obtained via
1625 * sg_dma_{address,length}.
1627 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1628 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1630 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1633 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1634 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1637 struct scatterlist *s;
1640 for_each_sg(sg, s, nents, i) {
1642 __iommu_remove_mapping(dev, sg_dma_address(s),
1645 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1646 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1652 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1653 * @dev: valid struct device pointer
1654 * @sg: list of buffers
1655 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1656 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1658 * Unmap a set of streaming mode DMA translations. Again, CPU access
1659 * rules concerning calls here are the same as for dma_unmap_single().
1661 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1662 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1664 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1668 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1669 * @dev: valid struct device pointer
1670 * @sg: list of buffers
1671 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1672 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1674 * Unmap a set of streaming mode DMA translations. Again, CPU access
1675 * rules concerning calls here are the same as for dma_unmap_single().
1677 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1678 enum dma_data_direction dir, struct dma_attrs *attrs)
1680 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1684 * arm_iommu_sync_sg_for_cpu
1685 * @dev: valid struct device pointer
1686 * @sg: list of buffers
1687 * @nents: number of buffers to map (returned from dma_map_sg)
1688 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1690 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1691 int nents, enum dma_data_direction dir)
1693 struct scatterlist *s;
1696 for_each_sg(sg, s, nents, i)
1697 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1702 * arm_iommu_sync_sg_for_device
1703 * @dev: valid struct device pointer
1704 * @sg: list of buffers
1705 * @nents: number of buffers to map (returned from dma_map_sg)
1706 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1708 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1709 int nents, enum dma_data_direction dir)
1711 struct scatterlist *s;
1714 for_each_sg(sg, s, nents, i)
1715 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1720 * arm_coherent_iommu_map_page
1721 * @dev: valid struct device pointer
1722 * @page: page that buffer resides in
1723 * @offset: offset into page for start of buffer
1724 * @size: size of buffer to map
1725 * @dir: DMA transfer direction
1727 * Coherent IOMMU aware version of arm_dma_map_page()
1729 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1730 unsigned long offset, size_t size, enum dma_data_direction dir,
1731 struct dma_attrs *attrs)
1733 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1734 dma_addr_t dma_addr;
1735 int ret, prot, len = PAGE_ALIGN(size + offset);
1737 dma_addr = __alloc_iova(mapping, len);
1738 if (dma_addr == DMA_ERROR_CODE)
1741 prot = __dma_direction_to_prot(dir);
1743 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1747 return dma_addr + offset;
1749 __free_iova(mapping, dma_addr, len);
1750 return DMA_ERROR_CODE;
1754 * arm_iommu_map_page
1755 * @dev: valid struct device pointer
1756 * @page: page that buffer resides in
1757 * @offset: offset into page for start of buffer
1758 * @size: size of buffer to map
1759 * @dir: DMA transfer direction
1761 * IOMMU aware version of arm_dma_map_page()
1763 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1764 unsigned long offset, size_t size, enum dma_data_direction dir,
1765 struct dma_attrs *attrs)
1767 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1768 __dma_page_cpu_to_dev(page, offset, size, dir);
1770 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1774 * arm_coherent_iommu_unmap_page
1775 * @dev: valid struct device pointer
1776 * @handle: DMA address of buffer
1777 * @size: size of buffer (same as passed to dma_map_page)
1778 * @dir: DMA transfer direction (same as passed to dma_map_page)
1780 * Coherent IOMMU aware version of arm_dma_unmap_page()
1782 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1783 size_t size, enum dma_data_direction dir,
1784 struct dma_attrs *attrs)
1786 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1787 dma_addr_t iova = handle & PAGE_MASK;
1788 int offset = handle & ~PAGE_MASK;
1789 int len = PAGE_ALIGN(size + offset);
1794 iommu_unmap(mapping->domain, iova, len);
1795 __free_iova(mapping, iova, len);
1799 * arm_iommu_unmap_page
1800 * @dev: valid struct device pointer
1801 * @handle: DMA address of buffer
1802 * @size: size of buffer (same as passed to dma_map_page)
1803 * @dir: DMA transfer direction (same as passed to dma_map_page)
1805 * IOMMU aware version of arm_dma_unmap_page()
1807 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1808 size_t size, enum dma_data_direction dir,
1809 struct dma_attrs *attrs)
1811 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1812 dma_addr_t iova = handle & PAGE_MASK;
1813 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1814 int offset = handle & ~PAGE_MASK;
1815 int len = PAGE_ALIGN(size + offset);
1820 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1821 __dma_page_dev_to_cpu(page, offset, size, dir);
1823 iommu_unmap(mapping->domain, iova, len);
1824 __free_iova(mapping, iova, len);
1827 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1828 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1830 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1831 dma_addr_t iova = handle & PAGE_MASK;
1832 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1833 unsigned int offset = handle & ~PAGE_MASK;
1838 __dma_page_dev_to_cpu(page, offset, size, dir);
1841 static void arm_iommu_sync_single_for_device(struct device *dev,
1842 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1844 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1845 dma_addr_t iova = handle & PAGE_MASK;
1846 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1847 unsigned int offset = handle & ~PAGE_MASK;
1852 __dma_page_cpu_to_dev(page, offset, size, dir);
1855 struct dma_map_ops iommu_ops = {
1856 .alloc = arm_iommu_alloc_attrs,
1857 .free = arm_iommu_free_attrs,
1858 .mmap = arm_iommu_mmap_attrs,
1859 .get_sgtable = arm_iommu_get_sgtable,
1861 .map_page = arm_iommu_map_page,
1862 .unmap_page = arm_iommu_unmap_page,
1863 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1864 .sync_single_for_device = arm_iommu_sync_single_for_device,
1866 .map_sg = arm_iommu_map_sg,
1867 .unmap_sg = arm_iommu_unmap_sg,
1868 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1869 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1871 .set_dma_mask = arm_dma_set_mask,
1874 struct dma_map_ops iommu_coherent_ops = {
1875 .alloc = arm_iommu_alloc_attrs,
1876 .free = arm_iommu_free_attrs,
1877 .mmap = arm_iommu_mmap_attrs,
1878 .get_sgtable = arm_iommu_get_sgtable,
1880 .map_page = arm_coherent_iommu_map_page,
1881 .unmap_page = arm_coherent_iommu_unmap_page,
1883 .map_sg = arm_coherent_iommu_map_sg,
1884 .unmap_sg = arm_coherent_iommu_unmap_sg,
1886 .set_dma_mask = arm_dma_set_mask,
1890 * arm_iommu_create_mapping
1891 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1892 * @base: start address of the valid IO address space
1893 * @size: maximum size of the valid IO address space
1895 * Creates a mapping structure which holds information about used/unused
1896 * IO address ranges, which is required to perform memory allocation and
1897 * mapping with IOMMU aware functions.
1899 * The client device need to be attached to the mapping with
1900 * arm_iommu_attach_device function.
1902 struct dma_iommu_mapping *
1903 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
1905 unsigned int bits = size >> PAGE_SHIFT;
1906 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1907 struct dma_iommu_mapping *mapping;
1911 /* currently only 32-bit DMA address space is supported */
1912 if (size > DMA_BIT_MASK(32) + 1)
1913 return ERR_PTR(-ERANGE);
1916 return ERR_PTR(-EINVAL);
1918 if (bitmap_size > PAGE_SIZE) {
1919 extensions = bitmap_size / PAGE_SIZE;
1920 bitmap_size = PAGE_SIZE;
1923 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1927 mapping->bitmap_size = bitmap_size;
1928 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1930 if (!mapping->bitmaps)
1933 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1934 if (!mapping->bitmaps[0])
1937 mapping->nr_bitmaps = 1;
1938 mapping->extensions = extensions;
1939 mapping->base = base;
1940 mapping->bits = BITS_PER_BYTE * bitmap_size;
1942 spin_lock_init(&mapping->lock);
1944 mapping->domain = iommu_domain_alloc(bus);
1945 if (!mapping->domain)
1948 kref_init(&mapping->kref);
1951 kfree(mapping->bitmaps[0]);
1953 kfree(mapping->bitmaps);
1957 return ERR_PTR(err);
1959 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1961 static void release_iommu_mapping(struct kref *kref)
1964 struct dma_iommu_mapping *mapping =
1965 container_of(kref, struct dma_iommu_mapping, kref);
1967 iommu_domain_free(mapping->domain);
1968 for (i = 0; i < mapping->nr_bitmaps; i++)
1969 kfree(mapping->bitmaps[i]);
1970 kfree(mapping->bitmaps);
1974 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
1978 if (mapping->nr_bitmaps >= mapping->extensions)
1981 next_bitmap = mapping->nr_bitmaps;
1982 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
1984 if (!mapping->bitmaps[next_bitmap])
1987 mapping->nr_bitmaps++;
1992 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1995 kref_put(&mapping->kref, release_iommu_mapping);
1997 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1999 static int __arm_iommu_attach_device(struct device *dev,
2000 struct dma_iommu_mapping *mapping)
2004 err = iommu_attach_device(mapping->domain, dev);
2008 kref_get(&mapping->kref);
2009 to_dma_iommu_mapping(dev) = mapping;
2011 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2016 * arm_iommu_attach_device
2017 * @dev: valid struct device pointer
2018 * @mapping: io address space mapping structure (returned from
2019 * arm_iommu_create_mapping)
2021 * Attaches specified io address space mapping to the provided device.
2022 * This replaces the dma operations (dma_map_ops pointer) with the
2023 * IOMMU aware version.
2025 * More than one client might be attached to the same io address space
2028 int arm_iommu_attach_device(struct device *dev,
2029 struct dma_iommu_mapping *mapping)
2033 err = __arm_iommu_attach_device(dev, mapping);
2037 set_dma_ops(dev, &iommu_ops);
2040 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2042 static void __arm_iommu_detach_device(struct device *dev)
2044 struct dma_iommu_mapping *mapping;
2046 mapping = to_dma_iommu_mapping(dev);
2048 dev_warn(dev, "Not attached\n");
2052 iommu_detach_device(mapping->domain, dev);
2053 kref_put(&mapping->kref, release_iommu_mapping);
2054 to_dma_iommu_mapping(dev) = NULL;
2056 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2060 * arm_iommu_detach_device
2061 * @dev: valid struct device pointer
2063 * Detaches the provided device from a previously attached map.
2064 * This voids the dma operations (dma_map_ops pointer)
2066 void arm_iommu_detach_device(struct device *dev)
2068 __arm_iommu_detach_device(dev);
2069 set_dma_ops(dev, NULL);
2071 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2073 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2075 return coherent ? &iommu_coherent_ops : &iommu_ops;
2078 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2079 struct iommu_ops *iommu)
2081 struct dma_iommu_mapping *mapping;
2086 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2087 if (IS_ERR(mapping)) {
2088 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2089 size, dev_name(dev));
2093 if (__arm_iommu_attach_device(dev, mapping)) {
2094 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2096 arm_iommu_release_mapping(mapping);
2103 static void arm_teardown_iommu_dma_ops(struct device *dev)
2105 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2110 __arm_iommu_detach_device(dev);
2111 arm_iommu_release_mapping(mapping);
2116 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2117 struct iommu_ops *iommu)
2122 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2124 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2126 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2128 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2130 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2133 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2134 struct iommu_ops *iommu, bool coherent)
2136 struct dma_map_ops *dma_ops;
2138 dev->archdata.dma_coherent = coherent;
2139 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2140 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2142 dma_ops = arm_get_dma_map_ops(coherent);
2144 set_dma_ops(dev, dma_ops);
2147 void arch_teardown_dma_ops(struct device *dev)
2149 arm_teardown_iommu_dma_ops(dev);