2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
45 * The DMA API is built upon the notion of "buffer ownership". A buffer
46 * is either exclusively owned by the CPU (and therefore may be accessed
47 * by it) or exclusively owned by the DMA device. These helper functions
48 * represent the transitions between these two ownership states.
50 * Note, however, that on later ARMs, this notion does not work due to
51 * speculative prefetches. We model our approach on the assumption that
52 * the CPU does do speculative prefetches, which means we clean caches
53 * before transfers and delay cache invalidation until transfer completion.
56 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
57 size_t, enum dma_data_direction);
58 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
59 size_t, enum dma_data_direction);
62 * arm_dma_map_page - map a portion of a page for streaming DMA
63 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
64 * @page: page that buffer resides in
65 * @offset: offset into page for start of buffer
66 * @size: size of buffer to map
67 * @dir: DMA transfer direction
69 * Ensure that any data held in the cache is appropriately discarded
72 * The device owns this memory once this call has completed. The CPU
73 * can regain ownership by calling dma_unmap_page().
75 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
76 unsigned long offset, size_t size, enum dma_data_direction dir,
77 struct dma_attrs *attrs)
79 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
80 __dma_page_cpu_to_dev(page, offset, size, dir);
81 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
84 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
85 unsigned long offset, size_t size, enum dma_data_direction dir,
86 struct dma_attrs *attrs)
88 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
92 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
93 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
94 * @handle: DMA address of buffer
95 * @size: size of buffer (same as passed to dma_map_page)
96 * @dir: DMA transfer direction (same as passed to dma_map_page)
98 * Unmap a page streaming mode DMA translation. The handle and size
99 * must match what was provided in the previous dma_map_page() call.
100 * All other usages are undefined.
102 * After this call, reads by the CPU to the buffer are guaranteed to see
103 * whatever the device wrote there.
105 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
106 size_t size, enum dma_data_direction dir,
107 struct dma_attrs *attrs)
109 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
110 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
111 handle & ~PAGE_MASK, size, dir);
114 static void arm_dma_sync_single_for_cpu(struct device *dev,
115 dma_addr_t handle, size_t size, enum dma_data_direction dir)
117 unsigned int offset = handle & (PAGE_SIZE - 1);
118 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
119 __dma_page_dev_to_cpu(page, offset, size, dir);
122 static void arm_dma_sync_single_for_device(struct device *dev,
123 dma_addr_t handle, size_t size, enum dma_data_direction dir)
125 unsigned int offset = handle & (PAGE_SIZE - 1);
126 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
127 __dma_page_cpu_to_dev(page, offset, size, dir);
130 struct dma_map_ops arm_dma_ops = {
131 .alloc = arm_dma_alloc,
132 .free = arm_dma_free,
133 .mmap = arm_dma_mmap,
134 .get_sgtable = arm_dma_get_sgtable,
135 .map_page = arm_dma_map_page,
136 .unmap_page = arm_dma_unmap_page,
137 .map_sg = arm_dma_map_sg,
138 .unmap_sg = arm_dma_unmap_sg,
139 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
140 .sync_single_for_device = arm_dma_sync_single_for_device,
141 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
142 .sync_sg_for_device = arm_dma_sync_sg_for_device,
143 .set_dma_mask = arm_dma_set_mask,
145 EXPORT_SYMBOL(arm_dma_ops);
147 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
148 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
149 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
150 dma_addr_t handle, struct dma_attrs *attrs);
151 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
152 void *cpu_addr, dma_addr_t dma_addr, size_t size,
153 struct dma_attrs *attrs);
155 struct dma_map_ops arm_coherent_dma_ops = {
156 .alloc = arm_coherent_dma_alloc,
157 .free = arm_coherent_dma_free,
158 .mmap = arm_coherent_dma_mmap,
159 .get_sgtable = arm_dma_get_sgtable,
160 .map_page = arm_coherent_dma_map_page,
161 .map_sg = arm_dma_map_sg,
162 .set_dma_mask = arm_dma_set_mask,
164 EXPORT_SYMBOL(arm_coherent_dma_ops);
166 static int __dma_supported(struct device *dev, u64 mask, bool warn)
168 unsigned long max_dma_pfn;
171 * If the mask allows for more memory than we can address,
172 * and we actually have that much memory, then we must
173 * indicate that DMA to this device is not supported.
175 if (sizeof(mask) != sizeof(dma_addr_t) &&
176 mask > (dma_addr_t)~0 &&
177 dma_to_pfn(dev, ~0) < max_pfn - 1) {
179 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
181 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
186 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
189 * Translate the device's DMA mask to a PFN limit. This
190 * PFN number includes the page which we can DMA to.
192 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
194 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
196 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
204 static u64 get_coherent_dma_mask(struct device *dev)
206 u64 mask = (u64)DMA_BIT_MASK(32);
209 mask = dev->coherent_dma_mask;
212 * Sanity check the DMA mask - it must be non-zero, and
213 * must be able to be satisfied by a DMA allocation.
216 dev_warn(dev, "coherent DMA mask is unset\n");
220 if (!__dma_supported(dev, mask, true))
227 static void __dma_clear_buffer(struct page *page, size_t size)
230 * Ensure that the allocated pages are zeroed, and that any data
231 * lurking in the kernel direct-mapped region is invalidated.
233 if (PageHighMem(page)) {
234 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
235 phys_addr_t end = base + size;
237 void *ptr = kmap_atomic(page);
238 memset(ptr, 0, PAGE_SIZE);
239 dmac_flush_range(ptr, ptr + PAGE_SIZE);
244 outer_flush_range(base, end);
246 void *ptr = page_address(page);
247 memset(ptr, 0, size);
248 dmac_flush_range(ptr, ptr + size);
249 outer_flush_range(__pa(ptr), __pa(ptr) + size);
254 * Allocate a DMA buffer for 'dev' of size 'size' using the
255 * specified gfp mask. Note that 'size' must be page aligned.
257 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
259 unsigned long order = get_order(size);
260 struct page *page, *p, *e;
262 page = alloc_pages(gfp, order);
267 * Now split the huge page and free the excess pages
269 split_page(page, order);
270 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
273 __dma_clear_buffer(page, size);
279 * Free a DMA buffer. 'size' must be page aligned.
281 static void __dma_free_buffer(struct page *page, size_t size)
283 struct page *e = page + (size >> PAGE_SHIFT);
293 static void *__alloc_from_contiguous(struct device *dev, size_t size,
294 pgprot_t prot, struct page **ret_page,
295 const void *caller, bool want_vaddr);
297 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
298 pgprot_t prot, struct page **ret_page,
299 const void *caller, bool want_vaddr);
302 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
306 * DMA allocation can be mapped to user space, so lets
307 * set VM_USERMAP flags too.
309 return dma_common_contiguous_remap(page, size,
310 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
314 static void __dma_free_remap(void *cpu_addr, size_t size)
316 dma_common_free_remap(cpu_addr, size,
317 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
320 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
321 static struct gen_pool *atomic_pool;
323 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
325 static int __init early_coherent_pool(char *p)
327 atomic_pool_size = memparse(p, &p);
330 early_param("coherent_pool", early_coherent_pool);
332 void __init init_dma_coherent_pool_size(unsigned long size)
335 * Catch any attempt to set the pool size too late.
340 * Set architecture specific coherent pool size only if
341 * it has not been changed by kernel command line parameter.
343 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
344 atomic_pool_size = size;
348 * Initialise the coherent pool for atomic allocations.
350 static int __init atomic_pool_init(void)
352 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
353 gfp_t gfp = GFP_KERNEL | GFP_DMA;
357 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
361 if (dev_get_cma_area(NULL))
362 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
363 &page, atomic_pool_init, true);
365 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
366 &page, atomic_pool_init, true);
370 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
372 atomic_pool_size, -1);
374 goto destroy_genpool;
376 gen_pool_set_algo(atomic_pool,
377 gen_pool_first_fit_order_align,
379 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
380 atomic_pool_size / 1024);
385 gen_pool_destroy(atomic_pool);
388 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
389 atomic_pool_size / 1024);
393 * CMA is activated by core_initcall, so we must be called after it.
395 postcore_initcall(atomic_pool_init);
397 struct dma_contig_early_reserve {
402 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
404 static int dma_mmu_remap_num __initdata;
406 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
408 dma_mmu_remap[dma_mmu_remap_num].base = base;
409 dma_mmu_remap[dma_mmu_remap_num].size = size;
413 void __init dma_contiguous_remap(void)
416 for (i = 0; i < dma_mmu_remap_num; i++) {
417 phys_addr_t start = dma_mmu_remap[i].base;
418 phys_addr_t end = start + dma_mmu_remap[i].size;
422 if (end > arm_lowmem_limit)
423 end = arm_lowmem_limit;
427 map.pfn = __phys_to_pfn(start);
428 map.virtual = __phys_to_virt(start);
429 map.length = end - start;
430 map.type = MT_MEMORY_DMA_READY;
433 * Clear previous low-memory mapping to ensure that the
434 * TLB does not see any conflicting entries, then flush
435 * the TLB of the old entries before creating new mappings.
437 * This ensures that any speculatively loaded TLB entries
438 * (even though they may be rare) can not cause any problems,
439 * and ensures that this code is architecturally compliant.
441 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
443 pmd_clear(pmd_off_k(addr));
445 flush_tlb_kernel_range(__phys_to_virt(start),
446 __phys_to_virt(end));
448 iotable_init(&map, 1);
452 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
455 struct page *page = virt_to_page(addr);
456 pgprot_t prot = *(pgprot_t *)data;
458 set_pte_ext(pte, mk_pte(page, prot), 0);
462 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
464 unsigned long start = (unsigned long) page_address(page);
465 unsigned end = start + size;
467 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
468 flush_tlb_kernel_range(start, end);
471 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
472 pgprot_t prot, struct page **ret_page,
473 const void *caller, bool want_vaddr)
477 page = __dma_alloc_buffer(dev, size, gfp);
483 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
485 __dma_free_buffer(page, size);
494 static void *__alloc_from_pool(size_t size, struct page **ret_page)
500 WARN(1, "coherent pool not initialised!\n");
504 val = gen_pool_alloc(atomic_pool, size);
506 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
508 *ret_page = phys_to_page(phys);
515 static bool __in_atomic_pool(void *start, size_t size)
517 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
520 static int __free_from_pool(void *start, size_t size)
522 if (!__in_atomic_pool(start, size))
525 gen_pool_free(atomic_pool, (unsigned long)start, size);
530 static void *__alloc_from_contiguous(struct device *dev, size_t size,
531 pgprot_t prot, struct page **ret_page,
532 const void *caller, bool want_vaddr)
534 unsigned long order = get_order(size);
535 size_t count = size >> PAGE_SHIFT;
539 page = dma_alloc_from_contiguous(dev, count, order);
543 __dma_clear_buffer(page, size);
548 if (PageHighMem(page)) {
549 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
551 dma_release_from_contiguous(dev, page, count);
555 __dma_remap(page, size, prot);
556 ptr = page_address(page);
564 static void __free_from_contiguous(struct device *dev, struct page *page,
565 void *cpu_addr, size_t size, bool want_vaddr)
568 if (PageHighMem(page))
569 __dma_free_remap(cpu_addr, size);
571 __dma_remap(page, size, PAGE_KERNEL);
573 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
576 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
578 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
579 pgprot_writecombine(prot) :
580 pgprot_dmacoherent(prot);
586 #else /* !CONFIG_MMU */
590 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
591 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
592 #define __alloc_from_pool(size, ret_page) NULL
593 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL
594 #define __free_from_pool(cpu_addr, size) 0
595 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
596 #define __dma_free_remap(cpu_addr, size) do { } while (0)
598 #endif /* CONFIG_MMU */
600 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
601 struct page **ret_page)
604 page = __dma_alloc_buffer(dev, size, gfp);
609 return page_address(page);
614 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
615 gfp_t gfp, pgprot_t prot, bool is_coherent,
616 struct dma_attrs *attrs, const void *caller)
618 u64 mask = get_coherent_dma_mask(dev);
619 struct page *page = NULL;
623 #ifdef CONFIG_DMA_API_DEBUG
624 u64 limit = (mask + 1) & ~mask;
625 if (limit && size >= limit) {
626 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
635 if (mask < 0xffffffffULL)
639 * Following is a work-around (a.k.a. hack) to prevent pages
640 * with __GFP_COMP being passed to split_page() which cannot
641 * handle them. The real problem is that this flag probably
642 * should be 0 on ARM as it is not supported on this
643 * platform; see CONFIG_HUGETLBFS.
645 gfp &= ~(__GFP_COMP);
647 *handle = DMA_ERROR_CODE;
648 size = PAGE_ALIGN(size);
649 want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
651 if (is_coherent || nommu())
652 addr = __alloc_simple_buffer(dev, size, gfp, &page);
653 else if (!(gfp & __GFP_WAIT))
654 addr = __alloc_from_pool(size, &page);
655 else if (!dev_get_cma_area(dev))
656 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller, want_vaddr);
658 addr = __alloc_from_contiguous(dev, size, prot, &page, caller, want_vaddr);
661 *handle = pfn_to_dma(dev, page_to_pfn(page));
663 return want_vaddr ? addr : page;
667 * Allocate DMA-coherent memory space and return both the kernel remapped
668 * virtual and bus address for that space.
670 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
671 gfp_t gfp, struct dma_attrs *attrs)
673 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
676 if (dma_alloc_from_coherent(dev, size, handle, &memory))
679 return __dma_alloc(dev, size, handle, gfp, prot, false,
680 attrs, __builtin_return_address(0));
683 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
684 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
686 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
689 if (dma_alloc_from_coherent(dev, size, handle, &memory))
692 return __dma_alloc(dev, size, handle, gfp, prot, true,
693 attrs, __builtin_return_address(0));
696 static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
697 void *cpu_addr, dma_addr_t dma_addr, size_t size,
698 struct dma_attrs *attrs)
702 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
703 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
704 unsigned long pfn = dma_to_pfn(dev, dma_addr);
705 unsigned long off = vma->vm_pgoff;
707 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
710 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
711 ret = remap_pfn_range(vma, vma->vm_start,
713 vma->vm_end - vma->vm_start,
716 #endif /* CONFIG_MMU */
722 * Create userspace mapping for the DMA-coherent memory.
724 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
725 void *cpu_addr, dma_addr_t dma_addr, size_t size,
726 struct dma_attrs *attrs)
728 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
731 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
732 void *cpu_addr, dma_addr_t dma_addr, size_t size,
733 struct dma_attrs *attrs)
736 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
737 #endif /* CONFIG_MMU */
738 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
742 * Free a buffer as defined by the above mapping.
744 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
745 dma_addr_t handle, struct dma_attrs *attrs,
748 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
749 bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
751 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
754 size = PAGE_ALIGN(size);
756 if (is_coherent || nommu()) {
757 __dma_free_buffer(page, size);
758 } else if (__free_from_pool(cpu_addr, size)) {
760 } else if (!dev_get_cma_area(dev)) {
762 __dma_free_remap(cpu_addr, size);
763 __dma_free_buffer(page, size);
766 * Non-atomic allocations cannot be freed with IRQs disabled
768 WARN_ON(irqs_disabled());
769 __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr);
773 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
774 dma_addr_t handle, struct dma_attrs *attrs)
776 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
779 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
780 dma_addr_t handle, struct dma_attrs *attrs)
782 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
785 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
786 void *cpu_addr, dma_addr_t handle, size_t size,
787 struct dma_attrs *attrs)
789 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
792 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
796 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
800 static void dma_cache_maint_page(struct page *page, unsigned long offset,
801 size_t size, enum dma_data_direction dir,
802 void (*op)(const void *, size_t, int))
807 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
811 * A single sg entry may refer to multiple physically contiguous
812 * pages. But we still need to process highmem pages individually.
813 * If highmem is not configured then the bulk of this loop gets
820 page = pfn_to_page(pfn);
822 if (PageHighMem(page)) {
823 if (len + offset > PAGE_SIZE)
824 len = PAGE_SIZE - offset;
826 if (cache_is_vipt_nonaliasing()) {
827 vaddr = kmap_atomic(page);
828 op(vaddr + offset, len, dir);
829 kunmap_atomic(vaddr);
831 vaddr = kmap_high_get(page);
833 op(vaddr + offset, len, dir);
838 vaddr = page_address(page) + offset;
848 * Make an area consistent for devices.
849 * Note: Drivers should NOT use this function directly, as it will break
850 * platforms with CONFIG_DMABOUNCE.
851 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
853 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
854 size_t size, enum dma_data_direction dir)
858 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
860 paddr = page_to_phys(page) + off;
861 if (dir == DMA_FROM_DEVICE) {
862 outer_inv_range(paddr, paddr + size);
864 outer_clean_range(paddr, paddr + size);
866 /* FIXME: non-speculating: flush on bidirectional mappings? */
869 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
870 size_t size, enum dma_data_direction dir)
872 phys_addr_t paddr = page_to_phys(page) + off;
874 /* FIXME: non-speculating: not required */
875 /* in any case, don't bother invalidating if DMA to device */
876 if (dir != DMA_TO_DEVICE) {
877 outer_inv_range(paddr, paddr + size);
879 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
883 * Mark the D-cache clean for these pages to avoid extra flushing.
885 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
889 pfn = page_to_pfn(page) + off / PAGE_SIZE;
893 left -= PAGE_SIZE - off;
895 while (left >= PAGE_SIZE) {
896 page = pfn_to_page(pfn++);
897 set_bit(PG_dcache_clean, &page->flags);
904 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
905 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
906 * @sg: list of buffers
907 * @nents: number of buffers to map
908 * @dir: DMA transfer direction
910 * Map a set of buffers described by scatterlist in streaming mode for DMA.
911 * This is the scatter-gather version of the dma_map_single interface.
912 * Here the scatter gather list elements are each tagged with the
913 * appropriate dma address and length. They are obtained via
914 * sg_dma_{address,length}.
916 * Device ownership issues as mentioned for dma_map_single are the same
919 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
920 enum dma_data_direction dir, struct dma_attrs *attrs)
922 struct dma_map_ops *ops = get_dma_ops(dev);
923 struct scatterlist *s;
926 for_each_sg(sg, s, nents, i) {
927 #ifdef CONFIG_NEED_SG_DMA_LENGTH
928 s->dma_length = s->length;
930 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
931 s->length, dir, attrs);
932 if (dma_mapping_error(dev, s->dma_address))
938 for_each_sg(sg, s, i, j)
939 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
944 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
945 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
946 * @sg: list of buffers
947 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
948 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
950 * Unmap a set of streaming mode DMA translations. Again, CPU access
951 * rules concerning calls here are the same as for dma_unmap_single().
953 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
954 enum dma_data_direction dir, struct dma_attrs *attrs)
956 struct dma_map_ops *ops = get_dma_ops(dev);
957 struct scatterlist *s;
961 for_each_sg(sg, s, nents, i)
962 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
966 * arm_dma_sync_sg_for_cpu
967 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
968 * @sg: list of buffers
969 * @nents: number of buffers to map (returned from dma_map_sg)
970 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
972 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
973 int nents, enum dma_data_direction dir)
975 struct dma_map_ops *ops = get_dma_ops(dev);
976 struct scatterlist *s;
979 for_each_sg(sg, s, nents, i)
980 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
985 * arm_dma_sync_sg_for_device
986 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
987 * @sg: list of buffers
988 * @nents: number of buffers to map (returned from dma_map_sg)
989 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
991 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
992 int nents, enum dma_data_direction dir)
994 struct dma_map_ops *ops = get_dma_ops(dev);
995 struct scatterlist *s;
998 for_each_sg(sg, s, nents, i)
999 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1004 * Return whether the given device DMA address mask can be supported
1005 * properly. For example, if your device can only drive the low 24-bits
1006 * during bus mastering, then you would pass 0x00ffffff as the mask
1009 int dma_supported(struct device *dev, u64 mask)
1011 return __dma_supported(dev, mask, false);
1013 EXPORT_SYMBOL(dma_supported);
1015 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1017 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1020 *dev->dma_mask = dma_mask;
1025 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1027 static int __init dma_debug_do_init(void)
1029 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1032 fs_initcall(dma_debug_do_init);
1034 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1038 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1040 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1043 unsigned int order = get_order(size);
1044 unsigned int align = 0;
1045 unsigned int count, start;
1046 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1047 unsigned long flags;
1051 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1052 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1054 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1055 align = (1 << order) - 1;
1057 spin_lock_irqsave(&mapping->lock, flags);
1058 for (i = 0; i < mapping->nr_bitmaps; i++) {
1059 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1060 mapping->bits, 0, count, align);
1062 if (start > mapping->bits)
1065 bitmap_set(mapping->bitmaps[i], start, count);
1070 * No unused range found. Try to extend the existing mapping
1071 * and perform a second attempt to reserve an IO virtual
1072 * address range of size bytes.
1074 if (i == mapping->nr_bitmaps) {
1075 if (extend_iommu_mapping(mapping)) {
1076 spin_unlock_irqrestore(&mapping->lock, flags);
1077 return DMA_ERROR_CODE;
1080 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1081 mapping->bits, 0, count, align);
1083 if (start > mapping->bits) {
1084 spin_unlock_irqrestore(&mapping->lock, flags);
1085 return DMA_ERROR_CODE;
1088 bitmap_set(mapping->bitmaps[i], start, count);
1090 spin_unlock_irqrestore(&mapping->lock, flags);
1092 iova = mapping->base + (mapping_size * i);
1093 iova += start << PAGE_SHIFT;
1098 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1099 dma_addr_t addr, size_t size)
1101 unsigned int start, count;
1102 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1103 unsigned long flags;
1104 dma_addr_t bitmap_base;
1110 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1111 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1113 bitmap_base = mapping->base + mapping_size * bitmap_index;
1115 start = (addr - bitmap_base) >> PAGE_SHIFT;
1117 if (addr + size > bitmap_base + mapping_size) {
1119 * The address range to be freed reaches into the iova
1120 * range of the next bitmap. This should not happen as
1121 * we don't allow this in __alloc_iova (at the
1126 count = size >> PAGE_SHIFT;
1128 spin_lock_irqsave(&mapping->lock, flags);
1129 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1130 spin_unlock_irqrestore(&mapping->lock, flags);
1133 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1134 gfp_t gfp, struct dma_attrs *attrs)
1136 struct page **pages;
1137 int count = size >> PAGE_SHIFT;
1138 int array_size = count * sizeof(struct page *);
1141 if (array_size <= PAGE_SIZE)
1142 pages = kzalloc(array_size, GFP_KERNEL);
1144 pages = vzalloc(array_size);
1148 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1150 unsigned long order = get_order(size);
1153 page = dma_alloc_from_contiguous(dev, count, order);
1157 __dma_clear_buffer(page, size);
1159 for (i = 0; i < count; i++)
1160 pages[i] = page + i;
1166 * IOMMU can map any pages, so himem can also be used here
1168 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1173 for (order = __fls(count); order > 0; --order) {
1175 * We do not want OOM killer to be invoked as long
1176 * as we can fall back to single pages, so we force
1177 * __GFP_NORETRY for orders higher than zero.
1179 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1186 * Fall back to single page allocation.
1187 * Might invoke OOM killer as last resort.
1189 pages[i] = alloc_pages(gfp, 0);
1195 split_page(pages[i], order);
1198 pages[i + j] = pages[i] + j;
1201 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1203 count -= 1 << order;
1210 __free_pages(pages[i], 0);
1211 if (array_size <= PAGE_SIZE)
1218 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1219 size_t size, struct dma_attrs *attrs)
1221 int count = size >> PAGE_SHIFT;
1222 int array_size = count * sizeof(struct page *);
1225 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1226 dma_release_from_contiguous(dev, pages[0], count);
1228 for (i = 0; i < count; i++)
1230 __free_pages(pages[i], 0);
1233 if (array_size <= PAGE_SIZE)
1241 * Create a CPU mapping for a specified pages
1244 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1247 return dma_common_pages_remap(pages, size,
1248 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1252 * Create a mapping in device IO address space for specified pages
1255 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1257 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1258 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1259 dma_addr_t dma_addr, iova;
1262 dma_addr = __alloc_iova(mapping, size);
1263 if (dma_addr == DMA_ERROR_CODE)
1267 for (i = 0; i < count; ) {
1270 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1271 phys_addr_t phys = page_to_phys(pages[i]);
1272 unsigned int len, j;
1274 for (j = i + 1; j < count; j++, next_pfn++)
1275 if (page_to_pfn(pages[j]) != next_pfn)
1278 len = (j - i) << PAGE_SHIFT;
1279 ret = iommu_map(mapping->domain, iova, phys, len,
1280 IOMMU_READ|IOMMU_WRITE);
1288 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1289 __free_iova(mapping, dma_addr, size);
1290 return DMA_ERROR_CODE;
1293 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1295 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1298 * add optional in-page offset from iova to size and align
1299 * result to page size
1301 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1304 iommu_unmap(mapping->domain, iova, size);
1305 __free_iova(mapping, iova, size);
1309 static struct page **__atomic_get_pages(void *addr)
1314 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1315 page = phys_to_page(phys);
1317 return (struct page **)page;
1320 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1322 struct vm_struct *area;
1324 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1325 return __atomic_get_pages(cpu_addr);
1327 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1330 area = find_vm_area(cpu_addr);
1331 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1336 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1342 addr = __alloc_from_pool(size, &page);
1346 *handle = __iommu_create_mapping(dev, &page, size);
1347 if (*handle == DMA_ERROR_CODE)
1353 __free_from_pool(addr, size);
1357 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1358 dma_addr_t handle, size_t size)
1360 __iommu_remove_mapping(dev, handle, size);
1361 __free_from_pool(cpu_addr, size);
1364 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1365 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1367 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1368 struct page **pages;
1371 *handle = DMA_ERROR_CODE;
1372 size = PAGE_ALIGN(size);
1374 if (!(gfp & __GFP_WAIT))
1375 return __iommu_alloc_atomic(dev, size, handle);
1378 * Following is a work-around (a.k.a. hack) to prevent pages
1379 * with __GFP_COMP being passed to split_page() which cannot
1380 * handle them. The real problem is that this flag probably
1381 * should be 0 on ARM as it is not supported on this
1382 * platform; see CONFIG_HUGETLBFS.
1384 gfp &= ~(__GFP_COMP);
1386 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1390 *handle = __iommu_create_mapping(dev, pages, size);
1391 if (*handle == DMA_ERROR_CODE)
1394 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1397 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1398 __builtin_return_address(0));
1405 __iommu_remove_mapping(dev, *handle, size);
1407 __iommu_free_buffer(dev, pages, size, attrs);
1411 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1412 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1413 struct dma_attrs *attrs)
1415 unsigned long uaddr = vma->vm_start;
1416 unsigned long usize = vma->vm_end - vma->vm_start;
1417 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1419 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1425 int ret = vm_insert_page(vma, uaddr, *pages++);
1427 pr_err("Remapping memory failed: %d\n", ret);
1432 } while (usize > 0);
1438 * free a page as defined by the above mapping.
1439 * Must not be called with IRQs disabled.
1441 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1442 dma_addr_t handle, struct dma_attrs *attrs)
1444 struct page **pages;
1445 size = PAGE_ALIGN(size);
1447 if (__in_atomic_pool(cpu_addr, size)) {
1448 __iommu_free_atomic(dev, cpu_addr, handle, size);
1452 pages = __iommu_get_pages(cpu_addr, attrs);
1454 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1458 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1459 dma_common_free_remap(cpu_addr, size,
1460 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1463 __iommu_remove_mapping(dev, handle, size);
1464 __iommu_free_buffer(dev, pages, size, attrs);
1467 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1468 void *cpu_addr, dma_addr_t dma_addr,
1469 size_t size, struct dma_attrs *attrs)
1471 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1472 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1477 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1481 static int __dma_direction_to_prot(enum dma_data_direction dir)
1486 case DMA_BIDIRECTIONAL:
1487 prot = IOMMU_READ | IOMMU_WRITE;
1492 case DMA_FROM_DEVICE:
1503 * Map a part of the scatter-gather list into contiguous io address space
1505 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1506 size_t size, dma_addr_t *handle,
1507 enum dma_data_direction dir, struct dma_attrs *attrs,
1510 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1511 dma_addr_t iova, iova_base;
1514 struct scatterlist *s;
1517 size = PAGE_ALIGN(size);
1518 *handle = DMA_ERROR_CODE;
1520 iova_base = iova = __alloc_iova(mapping, size);
1521 if (iova == DMA_ERROR_CODE)
1524 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1525 phys_addr_t phys = page_to_phys(sg_page(s));
1526 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1529 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1530 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1532 prot = __dma_direction_to_prot(dir);
1534 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1537 count += len >> PAGE_SHIFT;
1540 *handle = iova_base;
1544 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1545 __free_iova(mapping, iova_base, size);
1549 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1550 enum dma_data_direction dir, struct dma_attrs *attrs,
1553 struct scatterlist *s = sg, *dma = sg, *start = sg;
1555 unsigned int offset = s->offset;
1556 unsigned int size = s->offset + s->length;
1557 unsigned int max = dma_get_max_seg_size(dev);
1559 for (i = 1; i < nents; i++) {
1562 s->dma_address = DMA_ERROR_CODE;
1565 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1566 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1567 dir, attrs, is_coherent) < 0)
1570 dma->dma_address += offset;
1571 dma->dma_length = size - offset;
1573 size = offset = s->offset;
1580 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1584 dma->dma_address += offset;
1585 dma->dma_length = size - offset;
1590 for_each_sg(sg, s, count, i)
1591 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1596 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1597 * @dev: valid struct device pointer
1598 * @sg: list of buffers
1599 * @nents: number of buffers to map
1600 * @dir: DMA transfer direction
1602 * Map a set of i/o coherent buffers described by scatterlist in streaming
1603 * mode for DMA. The scatter gather list elements are merged together (if
1604 * possible) and tagged with the appropriate dma address and length. They are
1605 * obtained via sg_dma_{address,length}.
1607 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1608 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1610 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1614 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1615 * @dev: valid struct device pointer
1616 * @sg: list of buffers
1617 * @nents: number of buffers to map
1618 * @dir: DMA transfer direction
1620 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1621 * The scatter gather list elements are merged together (if possible) and
1622 * tagged with the appropriate dma address and length. They are obtained via
1623 * sg_dma_{address,length}.
1625 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1626 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1628 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1631 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1632 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1635 struct scatterlist *s;
1638 for_each_sg(sg, s, nents, i) {
1640 __iommu_remove_mapping(dev, sg_dma_address(s),
1643 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1644 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1650 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1651 * @dev: valid struct device pointer
1652 * @sg: list of buffers
1653 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1654 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1656 * Unmap a set of streaming mode DMA translations. Again, CPU access
1657 * rules concerning calls here are the same as for dma_unmap_single().
1659 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1660 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1662 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1666 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1667 * @dev: valid struct device pointer
1668 * @sg: list of buffers
1669 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1670 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1672 * Unmap a set of streaming mode DMA translations. Again, CPU access
1673 * rules concerning calls here are the same as for dma_unmap_single().
1675 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1676 enum dma_data_direction dir, struct dma_attrs *attrs)
1678 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1682 * arm_iommu_sync_sg_for_cpu
1683 * @dev: valid struct device pointer
1684 * @sg: list of buffers
1685 * @nents: number of buffers to map (returned from dma_map_sg)
1686 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1688 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1689 int nents, enum dma_data_direction dir)
1691 struct scatterlist *s;
1694 for_each_sg(sg, s, nents, i)
1695 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1700 * arm_iommu_sync_sg_for_device
1701 * @dev: valid struct device pointer
1702 * @sg: list of buffers
1703 * @nents: number of buffers to map (returned from dma_map_sg)
1704 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1706 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1707 int nents, enum dma_data_direction dir)
1709 struct scatterlist *s;
1712 for_each_sg(sg, s, nents, i)
1713 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1718 * arm_coherent_iommu_map_page
1719 * @dev: valid struct device pointer
1720 * @page: page that buffer resides in
1721 * @offset: offset into page for start of buffer
1722 * @size: size of buffer to map
1723 * @dir: DMA transfer direction
1725 * Coherent IOMMU aware version of arm_dma_map_page()
1727 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1728 unsigned long offset, size_t size, enum dma_data_direction dir,
1729 struct dma_attrs *attrs)
1731 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1732 dma_addr_t dma_addr;
1733 int ret, prot, len = PAGE_ALIGN(size + offset);
1735 dma_addr = __alloc_iova(mapping, len);
1736 if (dma_addr == DMA_ERROR_CODE)
1739 prot = __dma_direction_to_prot(dir);
1741 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1745 return dma_addr + offset;
1747 __free_iova(mapping, dma_addr, len);
1748 return DMA_ERROR_CODE;
1752 * arm_iommu_map_page
1753 * @dev: valid struct device pointer
1754 * @page: page that buffer resides in
1755 * @offset: offset into page for start of buffer
1756 * @size: size of buffer to map
1757 * @dir: DMA transfer direction
1759 * IOMMU aware version of arm_dma_map_page()
1761 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1762 unsigned long offset, size_t size, enum dma_data_direction dir,
1763 struct dma_attrs *attrs)
1765 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1766 __dma_page_cpu_to_dev(page, offset, size, dir);
1768 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1772 * arm_coherent_iommu_unmap_page
1773 * @dev: valid struct device pointer
1774 * @handle: DMA address of buffer
1775 * @size: size of buffer (same as passed to dma_map_page)
1776 * @dir: DMA transfer direction (same as passed to dma_map_page)
1778 * Coherent IOMMU aware version of arm_dma_unmap_page()
1780 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1781 size_t size, enum dma_data_direction dir,
1782 struct dma_attrs *attrs)
1784 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1785 dma_addr_t iova = handle & PAGE_MASK;
1786 int offset = handle & ~PAGE_MASK;
1787 int len = PAGE_ALIGN(size + offset);
1792 iommu_unmap(mapping->domain, iova, len);
1793 __free_iova(mapping, iova, len);
1797 * arm_iommu_unmap_page
1798 * @dev: valid struct device pointer
1799 * @handle: DMA address of buffer
1800 * @size: size of buffer (same as passed to dma_map_page)
1801 * @dir: DMA transfer direction (same as passed to dma_map_page)
1803 * IOMMU aware version of arm_dma_unmap_page()
1805 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1806 size_t size, enum dma_data_direction dir,
1807 struct dma_attrs *attrs)
1809 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1810 dma_addr_t iova = handle & PAGE_MASK;
1811 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1812 int offset = handle & ~PAGE_MASK;
1813 int len = PAGE_ALIGN(size + offset);
1818 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1819 __dma_page_dev_to_cpu(page, offset, size, dir);
1821 iommu_unmap(mapping->domain, iova, len);
1822 __free_iova(mapping, iova, len);
1825 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1826 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1828 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1829 dma_addr_t iova = handle & PAGE_MASK;
1830 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1831 unsigned int offset = handle & ~PAGE_MASK;
1836 __dma_page_dev_to_cpu(page, offset, size, dir);
1839 static void arm_iommu_sync_single_for_device(struct device *dev,
1840 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1842 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1843 dma_addr_t iova = handle & PAGE_MASK;
1844 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1845 unsigned int offset = handle & ~PAGE_MASK;
1850 __dma_page_cpu_to_dev(page, offset, size, dir);
1853 struct dma_map_ops iommu_ops = {
1854 .alloc = arm_iommu_alloc_attrs,
1855 .free = arm_iommu_free_attrs,
1856 .mmap = arm_iommu_mmap_attrs,
1857 .get_sgtable = arm_iommu_get_sgtable,
1859 .map_page = arm_iommu_map_page,
1860 .unmap_page = arm_iommu_unmap_page,
1861 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1862 .sync_single_for_device = arm_iommu_sync_single_for_device,
1864 .map_sg = arm_iommu_map_sg,
1865 .unmap_sg = arm_iommu_unmap_sg,
1866 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1867 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1869 .set_dma_mask = arm_dma_set_mask,
1872 struct dma_map_ops iommu_coherent_ops = {
1873 .alloc = arm_iommu_alloc_attrs,
1874 .free = arm_iommu_free_attrs,
1875 .mmap = arm_iommu_mmap_attrs,
1876 .get_sgtable = arm_iommu_get_sgtable,
1878 .map_page = arm_coherent_iommu_map_page,
1879 .unmap_page = arm_coherent_iommu_unmap_page,
1881 .map_sg = arm_coherent_iommu_map_sg,
1882 .unmap_sg = arm_coherent_iommu_unmap_sg,
1884 .set_dma_mask = arm_dma_set_mask,
1888 * arm_iommu_create_mapping
1889 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1890 * @base: start address of the valid IO address space
1891 * @size: maximum size of the valid IO address space
1893 * Creates a mapping structure which holds information about used/unused
1894 * IO address ranges, which is required to perform memory allocation and
1895 * mapping with IOMMU aware functions.
1897 * The client device need to be attached to the mapping with
1898 * arm_iommu_attach_device function.
1900 struct dma_iommu_mapping *
1901 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
1903 unsigned int bits = size >> PAGE_SHIFT;
1904 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1905 struct dma_iommu_mapping *mapping;
1909 /* currently only 32-bit DMA address space is supported */
1910 if (size > DMA_BIT_MASK(32) + 1)
1911 return ERR_PTR(-ERANGE);
1914 return ERR_PTR(-EINVAL);
1916 if (bitmap_size > PAGE_SIZE) {
1917 extensions = bitmap_size / PAGE_SIZE;
1918 bitmap_size = PAGE_SIZE;
1921 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1925 mapping->bitmap_size = bitmap_size;
1926 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1928 if (!mapping->bitmaps)
1931 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1932 if (!mapping->bitmaps[0])
1935 mapping->nr_bitmaps = 1;
1936 mapping->extensions = extensions;
1937 mapping->base = base;
1938 mapping->bits = BITS_PER_BYTE * bitmap_size;
1940 spin_lock_init(&mapping->lock);
1942 mapping->domain = iommu_domain_alloc(bus);
1943 if (!mapping->domain)
1946 kref_init(&mapping->kref);
1949 kfree(mapping->bitmaps[0]);
1951 kfree(mapping->bitmaps);
1955 return ERR_PTR(err);
1957 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1959 static void release_iommu_mapping(struct kref *kref)
1962 struct dma_iommu_mapping *mapping =
1963 container_of(kref, struct dma_iommu_mapping, kref);
1965 iommu_domain_free(mapping->domain);
1966 for (i = 0; i < mapping->nr_bitmaps; i++)
1967 kfree(mapping->bitmaps[i]);
1968 kfree(mapping->bitmaps);
1972 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
1976 if (mapping->nr_bitmaps >= mapping->extensions)
1979 next_bitmap = mapping->nr_bitmaps;
1980 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
1982 if (!mapping->bitmaps[next_bitmap])
1985 mapping->nr_bitmaps++;
1990 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1993 kref_put(&mapping->kref, release_iommu_mapping);
1995 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1997 static int __arm_iommu_attach_device(struct device *dev,
1998 struct dma_iommu_mapping *mapping)
2002 err = iommu_attach_device(mapping->domain, dev);
2006 kref_get(&mapping->kref);
2007 to_dma_iommu_mapping(dev) = mapping;
2009 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2014 * arm_iommu_attach_device
2015 * @dev: valid struct device pointer
2016 * @mapping: io address space mapping structure (returned from
2017 * arm_iommu_create_mapping)
2019 * Attaches specified io address space mapping to the provided device.
2020 * This replaces the dma operations (dma_map_ops pointer) with the
2021 * IOMMU aware version.
2023 * More than one client might be attached to the same io address space
2026 int arm_iommu_attach_device(struct device *dev,
2027 struct dma_iommu_mapping *mapping)
2031 err = __arm_iommu_attach_device(dev, mapping);
2035 set_dma_ops(dev, &iommu_ops);
2038 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2040 static void __arm_iommu_detach_device(struct device *dev)
2042 struct dma_iommu_mapping *mapping;
2044 mapping = to_dma_iommu_mapping(dev);
2046 dev_warn(dev, "Not attached\n");
2050 iommu_detach_device(mapping->domain, dev);
2051 kref_put(&mapping->kref, release_iommu_mapping);
2052 to_dma_iommu_mapping(dev) = NULL;
2054 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2058 * arm_iommu_detach_device
2059 * @dev: valid struct device pointer
2061 * Detaches the provided device from a previously attached map.
2062 * This voids the dma operations (dma_map_ops pointer)
2064 void arm_iommu_detach_device(struct device *dev)
2066 __arm_iommu_detach_device(dev);
2067 set_dma_ops(dev, NULL);
2069 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2071 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2073 return coherent ? &iommu_coherent_ops : &iommu_ops;
2076 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2077 struct iommu_ops *iommu)
2079 struct dma_iommu_mapping *mapping;
2084 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2085 if (IS_ERR(mapping)) {
2086 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2087 size, dev_name(dev));
2091 if (__arm_iommu_attach_device(dev, mapping)) {
2092 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2094 arm_iommu_release_mapping(mapping);
2101 static void arm_teardown_iommu_dma_ops(struct device *dev)
2103 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2108 __arm_iommu_detach_device(dev);
2109 arm_iommu_release_mapping(mapping);
2114 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2115 struct iommu_ops *iommu)
2120 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2122 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2124 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2126 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2128 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2131 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2132 struct iommu_ops *iommu, bool coherent)
2134 struct dma_map_ops *dma_ops;
2136 dev->archdata.dma_coherent = coherent;
2137 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2138 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2140 dma_ops = arm_get_dma_map_ops(coherent);
2142 set_dma_ops(dev, dma_ops);
2145 void arch_teardown_dma_ops(struct device *dev)
2147 arm_teardown_iommu_dma_ops(dev);