2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/gfp.h>
16 #include <linux/errno.h>
17 #include <linux/list.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dma-contiguous.h>
22 #include <linux/highmem.h>
23 #include <linux/memblock.h>
24 #include <linux/slab.h>
25 #include <linux/iommu.h>
27 #include <linux/vmalloc.h>
28 #include <linux/sizes.h>
30 #include <asm/memory.h>
31 #include <asm/highmem.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <asm/mach/arch.h>
35 #include <asm/dma-iommu.h>
36 #include <asm/mach/map.h>
37 #include <asm/system_info.h>
38 #include <asm/dma-contiguous.h>
43 * The DMA API is built upon the notion of "buffer ownership". A buffer
44 * is either exclusively owned by the CPU (and therefore may be accessed
45 * by it) or exclusively owned by the DMA device. These helper functions
46 * represent the transitions between these two ownership states.
48 * Note, however, that on later ARMs, this notion does not work due to
49 * speculative prefetches. We model our approach on the assumption that
50 * the CPU does do speculative prefetches, which means we clean caches
51 * before transfers and delay cache invalidation until transfer completion.
54 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
55 size_t, enum dma_data_direction);
56 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
57 size_t, enum dma_data_direction);
60 * arm_dma_map_page - map a portion of a page for streaming DMA
61 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
62 * @page: page that buffer resides in
63 * @offset: offset into page for start of buffer
64 * @size: size of buffer to map
65 * @dir: DMA transfer direction
67 * Ensure that any data held in the cache is appropriately discarded
70 * The device owns this memory once this call has completed. The CPU
71 * can regain ownership by calling dma_unmap_page().
73 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
74 unsigned long offset, size_t size, enum dma_data_direction dir,
75 struct dma_attrs *attrs)
77 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
78 __dma_page_cpu_to_dev(page, offset, size, dir);
79 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
82 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
83 unsigned long offset, size_t size, enum dma_data_direction dir,
84 struct dma_attrs *attrs)
86 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
90 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
91 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
92 * @handle: DMA address of buffer
93 * @size: size of buffer (same as passed to dma_map_page)
94 * @dir: DMA transfer direction (same as passed to dma_map_page)
96 * Unmap a page streaming mode DMA translation. The handle and size
97 * must match what was provided in the previous dma_map_page() call.
98 * All other usages are undefined.
100 * After this call, reads by the CPU to the buffer are guaranteed to see
101 * whatever the device wrote there.
103 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
104 size_t size, enum dma_data_direction dir,
105 struct dma_attrs *attrs)
107 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
108 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
109 handle & ~PAGE_MASK, size, dir);
112 static void arm_dma_sync_single_for_cpu(struct device *dev,
113 dma_addr_t handle, size_t size, enum dma_data_direction dir)
115 unsigned int offset = handle & (PAGE_SIZE - 1);
116 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
117 __dma_page_dev_to_cpu(page, offset, size, dir);
120 static void arm_dma_sync_single_for_device(struct device *dev,
121 dma_addr_t handle, size_t size, enum dma_data_direction dir)
123 unsigned int offset = handle & (PAGE_SIZE - 1);
124 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
125 __dma_page_cpu_to_dev(page, offset, size, dir);
128 struct dma_map_ops arm_dma_ops = {
129 .alloc = arm_dma_alloc,
130 .free = arm_dma_free,
131 .mmap = arm_dma_mmap,
132 .get_sgtable = arm_dma_get_sgtable,
133 .map_page = arm_dma_map_page,
134 .unmap_page = arm_dma_unmap_page,
135 .map_sg = arm_dma_map_sg,
136 .unmap_sg = arm_dma_unmap_sg,
137 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
138 .sync_single_for_device = arm_dma_sync_single_for_device,
139 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
140 .sync_sg_for_device = arm_dma_sync_sg_for_device,
141 .set_dma_mask = arm_dma_set_mask,
143 EXPORT_SYMBOL(arm_dma_ops);
145 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
146 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
147 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
148 dma_addr_t handle, struct dma_attrs *attrs);
150 struct dma_map_ops arm_coherent_dma_ops = {
151 .alloc = arm_coherent_dma_alloc,
152 .free = arm_coherent_dma_free,
153 .mmap = arm_dma_mmap,
154 .get_sgtable = arm_dma_get_sgtable,
155 .map_page = arm_coherent_dma_map_page,
156 .map_sg = arm_dma_map_sg,
157 .set_dma_mask = arm_dma_set_mask,
159 EXPORT_SYMBOL(arm_coherent_dma_ops);
161 static u64 get_coherent_dma_mask(struct device *dev)
163 u64 mask = (u64)DMA_BIT_MASK(32);
166 unsigned long max_dma_pfn;
168 mask = dev->coherent_dma_mask;
171 * Sanity check the DMA mask - it must be non-zero, and
172 * must be able to be satisfied by a DMA allocation.
175 dev_warn(dev, "coherent DMA mask is unset\n");
179 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
182 * If the mask allows for more memory than we can address,
183 * and we actually have that much memory, then fail the
186 if (sizeof(mask) != sizeof(dma_addr_t) &&
187 mask > (dma_addr_t)~0 &&
188 dma_to_pfn(dev, ~0) > max_dma_pfn) {
189 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
191 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
196 * Now check that the mask, when translated to a PFN,
197 * fits within the allowable addresses which we can
200 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
201 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
203 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
204 arm_dma_pfn_limit + 1);
212 static void __dma_clear_buffer(struct page *page, size_t size)
215 * Ensure that the allocated pages are zeroed, and that any data
216 * lurking in the kernel direct-mapped region is invalidated.
218 if (PageHighMem(page)) {
219 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
220 phys_addr_t end = base + size;
222 void *ptr = kmap_atomic(page);
223 memset(ptr, 0, PAGE_SIZE);
224 dmac_flush_range(ptr, ptr + PAGE_SIZE);
229 outer_flush_range(base, end);
231 void *ptr = page_address(page);
232 memset(ptr, 0, size);
233 dmac_flush_range(ptr, ptr + size);
234 outer_flush_range(__pa(ptr), __pa(ptr) + size);
239 * Allocate a DMA buffer for 'dev' of size 'size' using the
240 * specified gfp mask. Note that 'size' must be page aligned.
242 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
244 unsigned long order = get_order(size);
245 struct page *page, *p, *e;
247 page = alloc_pages(gfp, order);
252 * Now split the huge page and free the excess pages
254 split_page(page, order);
255 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
258 __dma_clear_buffer(page, size);
264 * Free a DMA buffer. 'size' must be page aligned.
266 static void __dma_free_buffer(struct page *page, size_t size)
268 struct page *e = page + (size >> PAGE_SHIFT);
277 #ifdef CONFIG_HUGETLB_PAGE
278 #warning ARM Coherent DMA allocator does not (yet) support huge TLB
281 static void *__alloc_from_contiguous(struct device *dev, size_t size,
282 pgprot_t prot, struct page **ret_page,
285 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
286 pgprot_t prot, struct page **ret_page,
290 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
293 struct vm_struct *area;
297 * DMA allocation can be mapped to user space, so lets
298 * set VM_USERMAP flags too.
300 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
304 addr = (unsigned long)area->addr;
305 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
307 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
308 vunmap((void *)addr);
314 static void __dma_free_remap(void *cpu_addr, size_t size)
316 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
317 struct vm_struct *area = find_vm_area(cpu_addr);
318 if (!area || (area->flags & flags) != flags) {
319 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
322 unmap_kernel_range((unsigned long)cpu_addr, size);
326 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
331 unsigned long *bitmap;
332 unsigned long nr_pages;
337 static struct dma_pool atomic_pool = {
338 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
341 static int __init early_coherent_pool(char *p)
343 atomic_pool.size = memparse(p, &p);
346 early_param("coherent_pool", early_coherent_pool);
348 void __init init_dma_coherent_pool_size(unsigned long size)
351 * Catch any attempt to set the pool size too late.
353 BUG_ON(atomic_pool.vaddr);
356 * Set architecture specific coherent pool size only if
357 * it has not been changed by kernel command line parameter.
359 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
360 atomic_pool.size = size;
364 * Initialise the coherent pool for atomic allocations.
366 static int __init atomic_pool_init(void)
368 struct dma_pool *pool = &atomic_pool;
369 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
370 gfp_t gfp = GFP_KERNEL | GFP_DMA;
371 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
372 unsigned long *bitmap;
376 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
378 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
382 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
386 if (IS_ENABLED(CONFIG_DMA_CMA))
387 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
390 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
395 for (i = 0; i < nr_pages; i++)
398 spin_lock_init(&pool->lock);
401 pool->bitmap = bitmap;
402 pool->nr_pages = nr_pages;
403 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
404 (unsigned)pool->size / 1024);
412 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
413 (unsigned)pool->size / 1024);
417 * CMA is activated by core_initcall, so we must be called after it.
419 postcore_initcall(atomic_pool_init);
421 struct dma_contig_early_reserve {
426 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
428 static int dma_mmu_remap_num __initdata;
430 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
432 dma_mmu_remap[dma_mmu_remap_num].base = base;
433 dma_mmu_remap[dma_mmu_remap_num].size = size;
437 void __init dma_contiguous_remap(void)
440 for (i = 0; i < dma_mmu_remap_num; i++) {
441 phys_addr_t start = dma_mmu_remap[i].base;
442 phys_addr_t end = start + dma_mmu_remap[i].size;
446 if (end > arm_lowmem_limit)
447 end = arm_lowmem_limit;
451 map.pfn = __phys_to_pfn(start);
452 map.virtual = __phys_to_virt(start);
453 map.length = end - start;
454 map.type = MT_MEMORY_DMA_READY;
457 * Clear previous low-memory mapping
459 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
461 pmd_clear(pmd_off_k(addr));
463 iotable_init(&map, 1);
467 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
470 struct page *page = virt_to_page(addr);
471 pgprot_t prot = *(pgprot_t *)data;
473 set_pte_ext(pte, mk_pte(page, prot), 0);
477 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
479 unsigned long start = (unsigned long) page_address(page);
480 unsigned end = start + size;
482 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
483 flush_tlb_kernel_range(start, end);
486 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
487 pgprot_t prot, struct page **ret_page,
492 page = __dma_alloc_buffer(dev, size, gfp);
496 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
498 __dma_free_buffer(page, size);
506 static void *__alloc_from_pool(size_t size, struct page **ret_page)
508 struct dma_pool *pool = &atomic_pool;
509 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
513 unsigned long align_mask;
516 WARN(1, "coherent pool not initialised!\n");
521 * Align the region allocation - allocations from pool are rather
522 * small, so align them to their order in pages, minimum is a page
523 * size. This helps reduce fragmentation of the DMA space.
525 align_mask = (1 << get_order(size)) - 1;
527 spin_lock_irqsave(&pool->lock, flags);
528 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
529 0, count, align_mask);
530 if (pageno < pool->nr_pages) {
531 bitmap_set(pool->bitmap, pageno, count);
532 ptr = pool->vaddr + PAGE_SIZE * pageno;
533 *ret_page = pool->pages[pageno];
535 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
536 "Please increase it with coherent_pool= kernel parameter!\n",
537 (unsigned)pool->size / 1024);
539 spin_unlock_irqrestore(&pool->lock, flags);
544 static bool __in_atomic_pool(void *start, size_t size)
546 struct dma_pool *pool = &atomic_pool;
547 void *end = start + size;
548 void *pool_start = pool->vaddr;
549 void *pool_end = pool->vaddr + pool->size;
551 if (start < pool_start || start >= pool_end)
557 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
558 start, end - 1, pool_start, pool_end - 1);
563 static int __free_from_pool(void *start, size_t size)
565 struct dma_pool *pool = &atomic_pool;
566 unsigned long pageno, count;
569 if (!__in_atomic_pool(start, size))
572 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
573 count = size >> PAGE_SHIFT;
575 spin_lock_irqsave(&pool->lock, flags);
576 bitmap_clear(pool->bitmap, pageno, count);
577 spin_unlock_irqrestore(&pool->lock, flags);
582 static void *__alloc_from_contiguous(struct device *dev, size_t size,
583 pgprot_t prot, struct page **ret_page,
586 unsigned long order = get_order(size);
587 size_t count = size >> PAGE_SHIFT;
591 page = dma_alloc_from_contiguous(dev, count, order);
595 __dma_clear_buffer(page, size);
597 if (PageHighMem(page)) {
598 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
600 dma_release_from_contiguous(dev, page, count);
604 __dma_remap(page, size, prot);
605 ptr = page_address(page);
611 static void __free_from_contiguous(struct device *dev, struct page *page,
612 void *cpu_addr, size_t size)
614 if (PageHighMem(page))
615 __dma_free_remap(cpu_addr, size);
617 __dma_remap(page, size, pgprot_kernel);
618 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
621 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
623 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
624 pgprot_writecombine(prot) :
625 pgprot_dmacoherent(prot);
631 #else /* !CONFIG_MMU */
635 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
636 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
637 #define __alloc_from_pool(size, ret_page) NULL
638 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
639 #define __free_from_pool(cpu_addr, size) 0
640 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
641 #define __dma_free_remap(cpu_addr, size) do { } while (0)
643 #endif /* CONFIG_MMU */
645 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
646 struct page **ret_page)
649 page = __dma_alloc_buffer(dev, size, gfp);
654 return page_address(page);
659 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
660 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
662 u64 mask = get_coherent_dma_mask(dev);
663 struct page *page = NULL;
666 #ifdef CONFIG_DMA_API_DEBUG
667 u64 limit = (mask + 1) & ~mask;
668 if (limit && size >= limit) {
669 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
678 if (mask < 0xffffffffULL)
682 * Following is a work-around (a.k.a. hack) to prevent pages
683 * with __GFP_COMP being passed to split_page() which cannot
684 * handle them. The real problem is that this flag probably
685 * should be 0 on ARM as it is not supported on this
686 * platform; see CONFIG_HUGETLBFS.
688 gfp &= ~(__GFP_COMP);
690 *handle = DMA_ERROR_CODE;
691 size = PAGE_ALIGN(size);
693 if (is_coherent || nommu())
694 addr = __alloc_simple_buffer(dev, size, gfp, &page);
695 else if (!(gfp & __GFP_WAIT))
696 addr = __alloc_from_pool(size, &page);
697 else if (!IS_ENABLED(CONFIG_DMA_CMA))
698 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
700 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
703 *handle = pfn_to_dma(dev, page_to_pfn(page));
709 * Allocate DMA-coherent memory space and return both the kernel remapped
710 * virtual and bus address for that space.
712 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
713 gfp_t gfp, struct dma_attrs *attrs)
715 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
718 if (dma_alloc_from_coherent(dev, size, handle, &memory))
721 return __dma_alloc(dev, size, handle, gfp, prot, false,
722 __builtin_return_address(0));
725 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
726 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
728 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
731 if (dma_alloc_from_coherent(dev, size, handle, &memory))
734 return __dma_alloc(dev, size, handle, gfp, prot, true,
735 __builtin_return_address(0));
739 * Create userspace mapping for the DMA-coherent memory.
741 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
742 void *cpu_addr, dma_addr_t dma_addr, size_t size,
743 struct dma_attrs *attrs)
747 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
748 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
749 unsigned long pfn = dma_to_pfn(dev, dma_addr);
750 unsigned long off = vma->vm_pgoff;
752 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
754 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
757 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
758 ret = remap_pfn_range(vma, vma->vm_start,
760 vma->vm_end - vma->vm_start,
763 #endif /* CONFIG_MMU */
769 * Free a buffer as defined by the above mapping.
771 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
772 dma_addr_t handle, struct dma_attrs *attrs,
775 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
777 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
780 size = PAGE_ALIGN(size);
782 if (is_coherent || nommu()) {
783 __dma_free_buffer(page, size);
784 } else if (__free_from_pool(cpu_addr, size)) {
786 } else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
787 __dma_free_remap(cpu_addr, size);
788 __dma_free_buffer(page, size);
791 * Non-atomic allocations cannot be freed with IRQs disabled
793 WARN_ON(irqs_disabled());
794 __free_from_contiguous(dev, page, cpu_addr, size);
798 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
799 dma_addr_t handle, struct dma_attrs *attrs)
801 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
804 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
805 dma_addr_t handle, struct dma_attrs *attrs)
807 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
810 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
811 void *cpu_addr, dma_addr_t handle, size_t size,
812 struct dma_attrs *attrs)
814 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
817 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
821 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
825 static void dma_cache_maint_page(struct page *page, unsigned long offset,
826 size_t size, enum dma_data_direction dir,
827 void (*op)(const void *, size_t, int))
832 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
836 * A single sg entry may refer to multiple physically contiguous
837 * pages. But we still need to process highmem pages individually.
838 * If highmem is not configured then the bulk of this loop gets
845 page = pfn_to_page(pfn);
847 if (PageHighMem(page)) {
848 if (len + offset > PAGE_SIZE)
849 len = PAGE_SIZE - offset;
851 if (cache_is_vipt_nonaliasing()) {
852 vaddr = kmap_atomic(page);
853 op(vaddr + offset, len, dir);
854 kunmap_atomic(vaddr);
856 vaddr = kmap_high_get(page);
858 op(vaddr + offset, len, dir);
863 vaddr = page_address(page) + offset;
873 * Make an area consistent for devices.
874 * Note: Drivers should NOT use this function directly, as it will break
875 * platforms with CONFIG_DMABOUNCE.
876 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
878 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
879 size_t size, enum dma_data_direction dir)
883 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
885 paddr = page_to_phys(page) + off;
886 if (dir == DMA_FROM_DEVICE) {
887 outer_inv_range(paddr, paddr + size);
889 outer_clean_range(paddr, paddr + size);
891 /* FIXME: non-speculating: flush on bidirectional mappings? */
894 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
895 size_t size, enum dma_data_direction dir)
897 unsigned long paddr = page_to_phys(page) + off;
899 /* FIXME: non-speculating: not required */
900 /* don't bother invalidating if DMA to device */
901 if (dir != DMA_TO_DEVICE)
902 outer_inv_range(paddr, paddr + size);
904 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
907 * Mark the D-cache clean for these pages to avoid extra flushing.
909 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
913 pfn = page_to_pfn(page) + off / PAGE_SIZE;
917 left -= PAGE_SIZE - off;
919 while (left >= PAGE_SIZE) {
920 page = pfn_to_page(pfn++);
921 set_bit(PG_dcache_clean, &page->flags);
928 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
929 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
930 * @sg: list of buffers
931 * @nents: number of buffers to map
932 * @dir: DMA transfer direction
934 * Map a set of buffers described by scatterlist in streaming mode for DMA.
935 * This is the scatter-gather version of the dma_map_single interface.
936 * Here the scatter gather list elements are each tagged with the
937 * appropriate dma address and length. They are obtained via
938 * sg_dma_{address,length}.
940 * Device ownership issues as mentioned for dma_map_single are the same
943 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
944 enum dma_data_direction dir, struct dma_attrs *attrs)
946 struct dma_map_ops *ops = get_dma_ops(dev);
947 struct scatterlist *s;
950 for_each_sg(sg, s, nents, i) {
951 #ifdef CONFIG_NEED_SG_DMA_LENGTH
952 s->dma_length = s->length;
954 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
955 s->length, dir, attrs);
956 if (dma_mapping_error(dev, s->dma_address))
962 for_each_sg(sg, s, i, j)
963 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
968 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
969 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
970 * @sg: list of buffers
971 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
972 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
974 * Unmap a set of streaming mode DMA translations. Again, CPU access
975 * rules concerning calls here are the same as for dma_unmap_single().
977 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
978 enum dma_data_direction dir, struct dma_attrs *attrs)
980 struct dma_map_ops *ops = get_dma_ops(dev);
981 struct scatterlist *s;
985 for_each_sg(sg, s, nents, i)
986 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
990 * arm_dma_sync_sg_for_cpu
991 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
992 * @sg: list of buffers
993 * @nents: number of buffers to map (returned from dma_map_sg)
994 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
996 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
997 int nents, enum dma_data_direction dir)
999 struct dma_map_ops *ops = get_dma_ops(dev);
1000 struct scatterlist *s;
1003 for_each_sg(sg, s, nents, i)
1004 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1009 * arm_dma_sync_sg_for_device
1010 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1011 * @sg: list of buffers
1012 * @nents: number of buffers to map (returned from dma_map_sg)
1013 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1015 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1016 int nents, enum dma_data_direction dir)
1018 struct dma_map_ops *ops = get_dma_ops(dev);
1019 struct scatterlist *s;
1022 for_each_sg(sg, s, nents, i)
1023 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1028 * Return whether the given device DMA address mask can be supported
1029 * properly. For example, if your device can only drive the low 24-bits
1030 * during bus mastering, then you would pass 0x00ffffff as the mask
1033 int dma_supported(struct device *dev, u64 mask)
1035 unsigned long limit;
1038 * If the mask allows for more memory than we can address,
1039 * and we actually have that much memory, then we must
1040 * indicate that DMA to this device is not supported.
1042 if (sizeof(mask) != sizeof(dma_addr_t) &&
1043 mask > (dma_addr_t)~0 &&
1044 dma_to_pfn(dev, ~0) > arm_dma_pfn_limit)
1048 * Translate the device's DMA mask to a PFN limit. This
1049 * PFN number includes the page which we can DMA to.
1051 limit = dma_to_pfn(dev, mask);
1053 if (limit < arm_dma_pfn_limit)
1058 EXPORT_SYMBOL(dma_supported);
1060 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1062 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1065 *dev->dma_mask = dma_mask;
1070 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1072 static int __init dma_debug_do_init(void)
1074 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1077 fs_initcall(dma_debug_do_init);
1079 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1083 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1086 unsigned int order = get_order(size);
1087 unsigned int align = 0;
1088 unsigned int count, start;
1089 unsigned long flags;
1091 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1092 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1094 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1095 (1 << mapping->order) - 1) >> mapping->order;
1097 if (order > mapping->order)
1098 align = (1 << (order - mapping->order)) - 1;
1100 spin_lock_irqsave(&mapping->lock, flags);
1101 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1103 if (start > mapping->bits) {
1104 spin_unlock_irqrestore(&mapping->lock, flags);
1105 return DMA_ERROR_CODE;
1108 bitmap_set(mapping->bitmap, start, count);
1109 spin_unlock_irqrestore(&mapping->lock, flags);
1111 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1114 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1115 dma_addr_t addr, size_t size)
1117 unsigned int start = (addr - mapping->base) >>
1118 (mapping->order + PAGE_SHIFT);
1119 unsigned int count = ((size >> PAGE_SHIFT) +
1120 (1 << mapping->order) - 1) >> mapping->order;
1121 unsigned long flags;
1123 spin_lock_irqsave(&mapping->lock, flags);
1124 bitmap_clear(mapping->bitmap, start, count);
1125 spin_unlock_irqrestore(&mapping->lock, flags);
1128 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1129 gfp_t gfp, struct dma_attrs *attrs)
1131 struct page **pages;
1132 int count = size >> PAGE_SHIFT;
1133 int array_size = count * sizeof(struct page *);
1136 if (array_size <= PAGE_SIZE)
1137 pages = kzalloc(array_size, gfp);
1139 pages = vzalloc(array_size);
1143 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1145 unsigned long order = get_order(size);
1148 page = dma_alloc_from_contiguous(dev, count, order);
1152 __dma_clear_buffer(page, size);
1154 for (i = 0; i < count; i++)
1155 pages[i] = page + i;
1161 * IOMMU can map any pages, so himem can also be used here
1163 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1166 int j, order = __fls(count);
1168 pages[i] = alloc_pages(gfp, order);
1169 while (!pages[i] && order)
1170 pages[i] = alloc_pages(gfp, --order);
1175 split_page(pages[i], order);
1178 pages[i + j] = pages[i] + j;
1181 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1183 count -= 1 << order;
1190 __free_pages(pages[i], 0);
1191 if (array_size <= PAGE_SIZE)
1198 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1199 size_t size, struct dma_attrs *attrs)
1201 int count = size >> PAGE_SHIFT;
1202 int array_size = count * sizeof(struct page *);
1205 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1206 dma_release_from_contiguous(dev, pages[0], count);
1208 for (i = 0; i < count; i++)
1210 __free_pages(pages[i], 0);
1213 if (array_size <= PAGE_SIZE)
1221 * Create a CPU mapping for a specified pages
1224 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1227 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1228 struct vm_struct *area;
1231 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1236 area->pages = pages;
1237 area->nr_pages = nr_pages;
1238 p = (unsigned long)area->addr;
1240 for (i = 0; i < nr_pages; i++) {
1241 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1242 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1248 unmap_kernel_range((unsigned long)area->addr, size);
1254 * Create a mapping in device IO address space for specified pages
1257 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1259 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1260 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1261 dma_addr_t dma_addr, iova;
1262 int i, ret = DMA_ERROR_CODE;
1264 dma_addr = __alloc_iova(mapping, size);
1265 if (dma_addr == DMA_ERROR_CODE)
1269 for (i = 0; i < count; ) {
1270 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1271 phys_addr_t phys = page_to_phys(pages[i]);
1272 unsigned int len, j;
1274 for (j = i + 1; j < count; j++, next_pfn++)
1275 if (page_to_pfn(pages[j]) != next_pfn)
1278 len = (j - i) << PAGE_SHIFT;
1279 ret = iommu_map(mapping->domain, iova, phys, len,
1280 IOMMU_READ|IOMMU_WRITE);
1288 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1289 __free_iova(mapping, dma_addr, size);
1290 return DMA_ERROR_CODE;
1293 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1295 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1298 * add optional in-page offset from iova to size and align
1299 * result to page size
1301 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1304 iommu_unmap(mapping->domain, iova, size);
1305 __free_iova(mapping, iova, size);
1309 static struct page **__atomic_get_pages(void *addr)
1311 struct dma_pool *pool = &atomic_pool;
1312 struct page **pages = pool->pages;
1313 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1315 return pages + offs;
1318 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1320 struct vm_struct *area;
1322 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1323 return __atomic_get_pages(cpu_addr);
1325 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1328 area = find_vm_area(cpu_addr);
1329 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1334 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1340 addr = __alloc_from_pool(size, &page);
1344 *handle = __iommu_create_mapping(dev, &page, size);
1345 if (*handle == DMA_ERROR_CODE)
1351 __free_from_pool(addr, size);
1355 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1356 dma_addr_t handle, size_t size)
1358 __iommu_remove_mapping(dev, handle, size);
1359 __free_from_pool(cpu_addr, size);
1362 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1363 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1365 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1366 struct page **pages;
1369 *handle = DMA_ERROR_CODE;
1370 size = PAGE_ALIGN(size);
1372 if (gfp & GFP_ATOMIC)
1373 return __iommu_alloc_atomic(dev, size, handle);
1376 * Following is a work-around (a.k.a. hack) to prevent pages
1377 * with __GFP_COMP being passed to split_page() which cannot
1378 * handle them. The real problem is that this flag probably
1379 * should be 0 on ARM as it is not supported on this
1380 * platform; see CONFIG_HUGETLBFS.
1382 gfp &= ~(__GFP_COMP);
1384 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1388 *handle = __iommu_create_mapping(dev, pages, size);
1389 if (*handle == DMA_ERROR_CODE)
1392 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1395 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1396 __builtin_return_address(0));
1403 __iommu_remove_mapping(dev, *handle, size);
1405 __iommu_free_buffer(dev, pages, size, attrs);
1409 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1410 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1411 struct dma_attrs *attrs)
1413 unsigned long uaddr = vma->vm_start;
1414 unsigned long usize = vma->vm_end - vma->vm_start;
1415 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1417 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1423 int ret = vm_insert_page(vma, uaddr, *pages++);
1425 pr_err("Remapping memory failed: %d\n", ret);
1430 } while (usize > 0);
1436 * free a page as defined by the above mapping.
1437 * Must not be called with IRQs disabled.
1439 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1440 dma_addr_t handle, struct dma_attrs *attrs)
1442 struct page **pages;
1443 size = PAGE_ALIGN(size);
1445 if (__in_atomic_pool(cpu_addr, size)) {
1446 __iommu_free_atomic(dev, cpu_addr, handle, size);
1450 pages = __iommu_get_pages(cpu_addr, attrs);
1452 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1456 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1457 unmap_kernel_range((unsigned long)cpu_addr, size);
1461 __iommu_remove_mapping(dev, handle, size);
1462 __iommu_free_buffer(dev, pages, size, attrs);
1465 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1466 void *cpu_addr, dma_addr_t dma_addr,
1467 size_t size, struct dma_attrs *attrs)
1469 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1470 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1475 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1479 static int __dma_direction_to_prot(enum dma_data_direction dir)
1484 case DMA_BIDIRECTIONAL:
1485 prot = IOMMU_READ | IOMMU_WRITE;
1490 case DMA_FROM_DEVICE:
1501 * Map a part of the scatter-gather list into contiguous io address space
1503 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1504 size_t size, dma_addr_t *handle,
1505 enum dma_data_direction dir, struct dma_attrs *attrs,
1508 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1509 dma_addr_t iova, iova_base;
1512 struct scatterlist *s;
1515 size = PAGE_ALIGN(size);
1516 *handle = DMA_ERROR_CODE;
1518 iova_base = iova = __alloc_iova(mapping, size);
1519 if (iova == DMA_ERROR_CODE)
1522 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1523 phys_addr_t phys = page_to_phys(sg_page(s));
1524 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1527 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1528 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1530 prot = __dma_direction_to_prot(dir);
1532 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1535 count += len >> PAGE_SHIFT;
1538 *handle = iova_base;
1542 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1543 __free_iova(mapping, iova_base, size);
1547 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1548 enum dma_data_direction dir, struct dma_attrs *attrs,
1551 struct scatterlist *s = sg, *dma = sg, *start = sg;
1553 unsigned int offset = s->offset;
1554 unsigned int size = s->offset + s->length;
1555 unsigned int max = dma_get_max_seg_size(dev);
1557 for (i = 1; i < nents; i++) {
1560 s->dma_address = DMA_ERROR_CODE;
1563 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1564 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1565 dir, attrs, is_coherent) < 0)
1568 dma->dma_address += offset;
1569 dma->dma_length = size - offset;
1571 size = offset = s->offset;
1578 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1582 dma->dma_address += offset;
1583 dma->dma_length = size - offset;
1588 for_each_sg(sg, s, count, i)
1589 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1594 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1595 * @dev: valid struct device pointer
1596 * @sg: list of buffers
1597 * @nents: number of buffers to map
1598 * @dir: DMA transfer direction
1600 * Map a set of i/o coherent buffers described by scatterlist in streaming
1601 * mode for DMA. The scatter gather list elements are merged together (if
1602 * possible) and tagged with the appropriate dma address and length. They are
1603 * obtained via sg_dma_{address,length}.
1605 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1606 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1608 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1612 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1613 * @dev: valid struct device pointer
1614 * @sg: list of buffers
1615 * @nents: number of buffers to map
1616 * @dir: DMA transfer direction
1618 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1619 * The scatter gather list elements are merged together (if possible) and
1620 * tagged with the appropriate dma address and length. They are obtained via
1621 * sg_dma_{address,length}.
1623 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1624 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1626 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1629 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1630 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1633 struct scatterlist *s;
1636 for_each_sg(sg, s, nents, i) {
1638 __iommu_remove_mapping(dev, sg_dma_address(s),
1641 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1642 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1648 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1649 * @dev: valid struct device pointer
1650 * @sg: list of buffers
1651 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1652 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1654 * Unmap a set of streaming mode DMA translations. Again, CPU access
1655 * rules concerning calls here are the same as for dma_unmap_single().
1657 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1658 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1660 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1664 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1665 * @dev: valid struct device pointer
1666 * @sg: list of buffers
1667 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1668 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1670 * Unmap a set of streaming mode DMA translations. Again, CPU access
1671 * rules concerning calls here are the same as for dma_unmap_single().
1673 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1674 enum dma_data_direction dir, struct dma_attrs *attrs)
1676 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1680 * arm_iommu_sync_sg_for_cpu
1681 * @dev: valid struct device pointer
1682 * @sg: list of buffers
1683 * @nents: number of buffers to map (returned from dma_map_sg)
1684 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1686 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1687 int nents, enum dma_data_direction dir)
1689 struct scatterlist *s;
1692 for_each_sg(sg, s, nents, i)
1693 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1698 * arm_iommu_sync_sg_for_device
1699 * @dev: valid struct device pointer
1700 * @sg: list of buffers
1701 * @nents: number of buffers to map (returned from dma_map_sg)
1702 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1704 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1705 int nents, enum dma_data_direction dir)
1707 struct scatterlist *s;
1710 for_each_sg(sg, s, nents, i)
1711 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1716 * arm_coherent_iommu_map_page
1717 * @dev: valid struct device pointer
1718 * @page: page that buffer resides in
1719 * @offset: offset into page for start of buffer
1720 * @size: size of buffer to map
1721 * @dir: DMA transfer direction
1723 * Coherent IOMMU aware version of arm_dma_map_page()
1725 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1726 unsigned long offset, size_t size, enum dma_data_direction dir,
1727 struct dma_attrs *attrs)
1729 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1730 dma_addr_t dma_addr;
1731 int ret, prot, len = PAGE_ALIGN(size + offset);
1733 dma_addr = __alloc_iova(mapping, len);
1734 if (dma_addr == DMA_ERROR_CODE)
1737 prot = __dma_direction_to_prot(dir);
1739 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1743 return dma_addr + offset;
1745 __free_iova(mapping, dma_addr, len);
1746 return DMA_ERROR_CODE;
1750 * arm_iommu_map_page
1751 * @dev: valid struct device pointer
1752 * @page: page that buffer resides in
1753 * @offset: offset into page for start of buffer
1754 * @size: size of buffer to map
1755 * @dir: DMA transfer direction
1757 * IOMMU aware version of arm_dma_map_page()
1759 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1760 unsigned long offset, size_t size, enum dma_data_direction dir,
1761 struct dma_attrs *attrs)
1763 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1764 __dma_page_cpu_to_dev(page, offset, size, dir);
1766 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1770 * arm_coherent_iommu_unmap_page
1771 * @dev: valid struct device pointer
1772 * @handle: DMA address of buffer
1773 * @size: size of buffer (same as passed to dma_map_page)
1774 * @dir: DMA transfer direction (same as passed to dma_map_page)
1776 * Coherent IOMMU aware version of arm_dma_unmap_page()
1778 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1779 size_t size, enum dma_data_direction dir,
1780 struct dma_attrs *attrs)
1782 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1783 dma_addr_t iova = handle & PAGE_MASK;
1784 int offset = handle & ~PAGE_MASK;
1785 int len = PAGE_ALIGN(size + offset);
1790 iommu_unmap(mapping->domain, iova, len);
1791 __free_iova(mapping, iova, len);
1795 * arm_iommu_unmap_page
1796 * @dev: valid struct device pointer
1797 * @handle: DMA address of buffer
1798 * @size: size of buffer (same as passed to dma_map_page)
1799 * @dir: DMA transfer direction (same as passed to dma_map_page)
1801 * IOMMU aware version of arm_dma_unmap_page()
1803 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1804 size_t size, enum dma_data_direction dir,
1805 struct dma_attrs *attrs)
1807 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1808 dma_addr_t iova = handle & PAGE_MASK;
1809 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1810 int offset = handle & ~PAGE_MASK;
1811 int len = PAGE_ALIGN(size + offset);
1816 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1817 __dma_page_dev_to_cpu(page, offset, size, dir);
1819 iommu_unmap(mapping->domain, iova, len);
1820 __free_iova(mapping, iova, len);
1823 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1824 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1826 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1827 dma_addr_t iova = handle & PAGE_MASK;
1828 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1829 unsigned int offset = handle & ~PAGE_MASK;
1834 __dma_page_dev_to_cpu(page, offset, size, dir);
1837 static void arm_iommu_sync_single_for_device(struct device *dev,
1838 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1840 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1841 dma_addr_t iova = handle & PAGE_MASK;
1842 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1843 unsigned int offset = handle & ~PAGE_MASK;
1848 __dma_page_cpu_to_dev(page, offset, size, dir);
1851 struct dma_map_ops iommu_ops = {
1852 .alloc = arm_iommu_alloc_attrs,
1853 .free = arm_iommu_free_attrs,
1854 .mmap = arm_iommu_mmap_attrs,
1855 .get_sgtable = arm_iommu_get_sgtable,
1857 .map_page = arm_iommu_map_page,
1858 .unmap_page = arm_iommu_unmap_page,
1859 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1860 .sync_single_for_device = arm_iommu_sync_single_for_device,
1862 .map_sg = arm_iommu_map_sg,
1863 .unmap_sg = arm_iommu_unmap_sg,
1864 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1865 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1867 .set_dma_mask = arm_dma_set_mask,
1870 struct dma_map_ops iommu_coherent_ops = {
1871 .alloc = arm_iommu_alloc_attrs,
1872 .free = arm_iommu_free_attrs,
1873 .mmap = arm_iommu_mmap_attrs,
1874 .get_sgtable = arm_iommu_get_sgtable,
1876 .map_page = arm_coherent_iommu_map_page,
1877 .unmap_page = arm_coherent_iommu_unmap_page,
1879 .map_sg = arm_coherent_iommu_map_sg,
1880 .unmap_sg = arm_coherent_iommu_unmap_sg,
1882 .set_dma_mask = arm_dma_set_mask,
1886 * arm_iommu_create_mapping
1887 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1888 * @base: start address of the valid IO address space
1889 * @size: size of the valid IO address space
1890 * @order: accuracy of the IO addresses allocations
1892 * Creates a mapping structure which holds information about used/unused
1893 * IO address ranges, which is required to perform memory allocation and
1894 * mapping with IOMMU aware functions.
1896 * The client device need to be attached to the mapping with
1897 * arm_iommu_attach_device function.
1899 struct dma_iommu_mapping *
1900 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1903 unsigned int count = size >> (PAGE_SHIFT + order);
1904 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1905 struct dma_iommu_mapping *mapping;
1909 return ERR_PTR(-EINVAL);
1911 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1915 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1916 if (!mapping->bitmap)
1919 mapping->base = base;
1920 mapping->bits = BITS_PER_BYTE * bitmap_size;
1921 mapping->order = order;
1922 spin_lock_init(&mapping->lock);
1924 mapping->domain = iommu_domain_alloc(bus);
1925 if (!mapping->domain)
1928 kref_init(&mapping->kref);
1931 kfree(mapping->bitmap);
1935 return ERR_PTR(err);
1937 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1939 static void release_iommu_mapping(struct kref *kref)
1941 struct dma_iommu_mapping *mapping =
1942 container_of(kref, struct dma_iommu_mapping, kref);
1944 iommu_domain_free(mapping->domain);
1945 kfree(mapping->bitmap);
1949 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1952 kref_put(&mapping->kref, release_iommu_mapping);
1954 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1957 * arm_iommu_attach_device
1958 * @dev: valid struct device pointer
1959 * @mapping: io address space mapping structure (returned from
1960 * arm_iommu_create_mapping)
1962 * Attaches specified io address space mapping to the provided device,
1963 * this replaces the dma operations (dma_map_ops pointer) with the
1964 * IOMMU aware version. More than one client might be attached to
1965 * the same io address space mapping.
1967 int arm_iommu_attach_device(struct device *dev,
1968 struct dma_iommu_mapping *mapping)
1972 err = iommu_attach_device(mapping->domain, dev);
1976 kref_get(&mapping->kref);
1977 dev->archdata.mapping = mapping;
1978 set_dma_ops(dev, &iommu_ops);
1980 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1983 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
1986 * arm_iommu_detach_device
1987 * @dev: valid struct device pointer
1989 * Detaches the provided device from a previously attached map.
1990 * This voids the dma operations (dma_map_ops pointer)
1992 void arm_iommu_detach_device(struct device *dev)
1994 struct dma_iommu_mapping *mapping;
1996 mapping = to_dma_iommu_mapping(dev);
1998 dev_warn(dev, "Not attached\n");
2002 iommu_detach_device(mapping->domain, dev);
2003 kref_put(&mapping->kref, release_iommu_mapping);
2004 dev->archdata.mapping = NULL;
2005 set_dma_ops(dev, NULL);
2007 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2009 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);