2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
46 * The DMA API is built upon the notion of "buffer ownership". A buffer
47 * is either exclusively owned by the CPU (and therefore may be accessed
48 * by it) or exclusively owned by the DMA device. These helper functions
49 * represent the transitions between these two ownership states.
51 * Note, however, that on later ARMs, this notion does not work due to
52 * speculative prefetches. We model our approach on the assumption that
53 * the CPU does do speculative prefetches, which means we clean caches
54 * before transfers and delay cache invalidation until transfer completion.
57 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
58 size_t, enum dma_data_direction);
59 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
60 size_t, enum dma_data_direction);
63 * arm_dma_map_page - map a portion of a page for streaming DMA
64 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
65 * @page: page that buffer resides in
66 * @offset: offset into page for start of buffer
67 * @size: size of buffer to map
68 * @dir: DMA transfer direction
70 * Ensure that any data held in the cache is appropriately discarded
73 * The device owns this memory once this call has completed. The CPU
74 * can regain ownership by calling dma_unmap_page().
76 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
77 unsigned long offset, size_t size, enum dma_data_direction dir,
78 struct dma_attrs *attrs)
80 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
81 __dma_page_cpu_to_dev(page, offset, size, dir);
82 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
85 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
86 unsigned long offset, size_t size, enum dma_data_direction dir,
87 struct dma_attrs *attrs)
89 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
93 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
94 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
95 * @handle: DMA address of buffer
96 * @size: size of buffer (same as passed to dma_map_page)
97 * @dir: DMA transfer direction (same as passed to dma_map_page)
99 * Unmap a page streaming mode DMA translation. The handle and size
100 * must match what was provided in the previous dma_map_page() call.
101 * All other usages are undefined.
103 * After this call, reads by the CPU to the buffer are guaranteed to see
104 * whatever the device wrote there.
106 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
107 size_t size, enum dma_data_direction dir,
108 struct dma_attrs *attrs)
110 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
111 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
112 handle & ~PAGE_MASK, size, dir);
115 static void arm_dma_sync_single_for_cpu(struct device *dev,
116 dma_addr_t handle, size_t size, enum dma_data_direction dir)
118 unsigned int offset = handle & (PAGE_SIZE - 1);
119 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
120 __dma_page_dev_to_cpu(page, offset, size, dir);
123 static void arm_dma_sync_single_for_device(struct device *dev,
124 dma_addr_t handle, size_t size, enum dma_data_direction dir)
126 unsigned int offset = handle & (PAGE_SIZE - 1);
127 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
128 __dma_page_cpu_to_dev(page, offset, size, dir);
131 struct dma_map_ops arm_dma_ops = {
132 .alloc = arm_dma_alloc,
133 .free = arm_dma_free,
134 .mmap = arm_dma_mmap,
135 .get_sgtable = arm_dma_get_sgtable,
136 .map_page = arm_dma_map_page,
137 .unmap_page = arm_dma_unmap_page,
138 .map_sg = arm_dma_map_sg,
139 .unmap_sg = arm_dma_unmap_sg,
140 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
141 .sync_single_for_device = arm_dma_sync_single_for_device,
142 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
143 .sync_sg_for_device = arm_dma_sync_sg_for_device,
144 .set_dma_mask = arm_dma_set_mask,
146 EXPORT_SYMBOL(arm_dma_ops);
148 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
149 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
150 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
151 dma_addr_t handle, struct dma_attrs *attrs);
152 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
153 void *cpu_addr, dma_addr_t dma_addr, size_t size,
154 struct dma_attrs *attrs);
156 struct dma_map_ops arm_coherent_dma_ops = {
157 .alloc = arm_coherent_dma_alloc,
158 .free = arm_coherent_dma_free,
159 .mmap = arm_coherent_dma_mmap,
160 .get_sgtable = arm_dma_get_sgtable,
161 .map_page = arm_coherent_dma_map_page,
162 .map_sg = arm_dma_map_sg,
163 .set_dma_mask = arm_dma_set_mask,
165 EXPORT_SYMBOL(arm_coherent_dma_ops);
167 static int __dma_supported(struct device *dev, u64 mask, bool warn)
169 unsigned long max_dma_pfn;
172 * If the mask allows for more memory than we can address,
173 * and we actually have that much memory, then we must
174 * indicate that DMA to this device is not supported.
176 if (sizeof(mask) != sizeof(dma_addr_t) &&
177 mask > (dma_addr_t)~0 &&
178 dma_to_pfn(dev, ~0) < max_pfn - 1) {
180 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
182 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
187 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
190 * Translate the device's DMA mask to a PFN limit. This
191 * PFN number includes the page which we can DMA to.
193 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
195 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
197 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
205 static u64 get_coherent_dma_mask(struct device *dev)
207 u64 mask = (u64)DMA_BIT_MASK(32);
210 mask = dev->coherent_dma_mask;
213 * Sanity check the DMA mask - it must be non-zero, and
214 * must be able to be satisfied by a DMA allocation.
217 dev_warn(dev, "coherent DMA mask is unset\n");
221 if (!__dma_supported(dev, mask, true))
228 static void __dma_clear_buffer(struct page *page, size_t size)
231 * Ensure that the allocated pages are zeroed, and that any data
232 * lurking in the kernel direct-mapped region is invalidated.
234 if (PageHighMem(page)) {
235 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
236 phys_addr_t end = base + size;
238 void *ptr = kmap_atomic(page);
239 memset(ptr, 0, PAGE_SIZE);
240 dmac_flush_range(ptr, ptr + PAGE_SIZE);
245 outer_flush_range(base, end);
247 void *ptr = page_address(page);
248 memset(ptr, 0, size);
249 dmac_flush_range(ptr, ptr + size);
250 outer_flush_range(__pa(ptr), __pa(ptr) + size);
255 * Allocate a DMA buffer for 'dev' of size 'size' using the
256 * specified gfp mask. Note that 'size' must be page aligned.
258 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
260 unsigned long order = get_order(size);
261 struct page *page, *p, *e;
263 page = alloc_pages(gfp, order);
268 * Now split the huge page and free the excess pages
270 split_page(page, order);
271 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
274 __dma_clear_buffer(page, size);
280 * Free a DMA buffer. 'size' must be page aligned.
282 static void __dma_free_buffer(struct page *page, size_t size)
284 struct page *e = page + (size >> PAGE_SHIFT);
294 static void *__alloc_from_contiguous(struct device *dev, size_t size,
295 pgprot_t prot, struct page **ret_page,
296 const void *caller, bool want_vaddr);
298 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
299 pgprot_t prot, struct page **ret_page,
300 const void *caller, bool want_vaddr);
303 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
307 * DMA allocation can be mapped to user space, so lets
308 * set VM_USERMAP flags too.
310 return dma_common_contiguous_remap(page, size,
311 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
315 static void __dma_free_remap(void *cpu_addr, size_t size)
317 dma_common_free_remap(cpu_addr, size,
318 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
321 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
322 static struct gen_pool *atomic_pool;
324 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
326 static int __init early_coherent_pool(char *p)
328 atomic_pool_size = memparse(p, &p);
331 early_param("coherent_pool", early_coherent_pool);
333 void __init init_dma_coherent_pool_size(unsigned long size)
336 * Catch any attempt to set the pool size too late.
341 * Set architecture specific coherent pool size only if
342 * it has not been changed by kernel command line parameter.
344 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
345 atomic_pool_size = size;
349 * Initialise the coherent pool for atomic allocations.
351 static int __init atomic_pool_init(void)
353 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
354 gfp_t gfp = GFP_KERNEL | GFP_DMA;
358 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
362 if (dev_get_cma_area(NULL))
363 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
364 &page, atomic_pool_init, true);
366 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
367 &page, atomic_pool_init, true);
371 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
373 atomic_pool_size, -1);
375 goto destroy_genpool;
377 gen_pool_set_algo(atomic_pool,
378 gen_pool_first_fit_order_align,
380 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
381 atomic_pool_size / 1024);
386 gen_pool_destroy(atomic_pool);
389 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
390 atomic_pool_size / 1024);
394 * CMA is activated by core_initcall, so we must be called after it.
396 postcore_initcall(atomic_pool_init);
398 struct dma_contig_early_reserve {
403 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
405 static int dma_mmu_remap_num __initdata;
407 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
409 dma_mmu_remap[dma_mmu_remap_num].base = base;
410 dma_mmu_remap[dma_mmu_remap_num].size = size;
414 void __init dma_contiguous_remap(void)
417 for (i = 0; i < dma_mmu_remap_num; i++) {
418 phys_addr_t start = dma_mmu_remap[i].base;
419 phys_addr_t end = start + dma_mmu_remap[i].size;
423 if (end > arm_lowmem_limit)
424 end = arm_lowmem_limit;
428 map.pfn = __phys_to_pfn(start);
429 map.virtual = __phys_to_virt(start);
430 map.length = end - start;
431 map.type = MT_MEMORY_DMA_READY;
434 * Clear previous low-memory mapping to ensure that the
435 * TLB does not see any conflicting entries, then flush
436 * the TLB of the old entries before creating new mappings.
438 * This ensures that any speculatively loaded TLB entries
439 * (even though they may be rare) can not cause any problems,
440 * and ensures that this code is architecturally compliant.
442 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
444 pmd_clear(pmd_off_k(addr));
446 flush_tlb_kernel_range(__phys_to_virt(start),
447 __phys_to_virt(end));
449 iotable_init(&map, 1);
453 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
456 struct page *page = virt_to_page(addr);
457 pgprot_t prot = *(pgprot_t *)data;
459 set_pte_ext(pte, mk_pte(page, prot), 0);
463 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
465 unsigned long start = (unsigned long) page_address(page);
466 unsigned end = start + size;
468 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
469 flush_tlb_kernel_range(start, end);
472 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
473 pgprot_t prot, struct page **ret_page,
474 const void *caller, bool want_vaddr)
478 page = __dma_alloc_buffer(dev, size, gfp);
484 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
486 __dma_free_buffer(page, size);
495 static void *__alloc_from_pool(size_t size, struct page **ret_page)
501 WARN(1, "coherent pool not initialised!\n");
505 val = gen_pool_alloc(atomic_pool, size);
507 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
509 *ret_page = phys_to_page(phys);
516 static bool __in_atomic_pool(void *start, size_t size)
518 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
521 static int __free_from_pool(void *start, size_t size)
523 if (!__in_atomic_pool(start, size))
526 gen_pool_free(atomic_pool, (unsigned long)start, size);
531 static void *__alloc_from_contiguous(struct device *dev, size_t size,
532 pgprot_t prot, struct page **ret_page,
533 const void *caller, bool want_vaddr)
535 unsigned long order = get_order(size);
536 size_t count = size >> PAGE_SHIFT;
540 page = dma_alloc_from_contiguous(dev, count, order);
544 __dma_clear_buffer(page, size);
549 if (PageHighMem(page)) {
550 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
552 dma_release_from_contiguous(dev, page, count);
556 __dma_remap(page, size, prot);
557 ptr = page_address(page);
565 static void __free_from_contiguous(struct device *dev, struct page *page,
566 void *cpu_addr, size_t size, bool want_vaddr)
569 if (PageHighMem(page))
570 __dma_free_remap(cpu_addr, size);
572 __dma_remap(page, size, PAGE_KERNEL);
574 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
577 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
579 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
580 pgprot_writecombine(prot) :
581 pgprot_dmacoherent(prot);
587 #else /* !CONFIG_MMU */
591 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
592 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
593 #define __alloc_from_pool(size, ret_page) NULL
594 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL
595 #define __free_from_pool(cpu_addr, size) 0
596 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
597 #define __dma_free_remap(cpu_addr, size) do { } while (0)
599 #endif /* CONFIG_MMU */
601 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
602 struct page **ret_page)
605 page = __dma_alloc_buffer(dev, size, gfp);
610 return page_address(page);
615 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
616 gfp_t gfp, pgprot_t prot, bool is_coherent,
617 struct dma_attrs *attrs, const void *caller)
619 u64 mask = get_coherent_dma_mask(dev);
620 struct page *page = NULL;
624 #ifdef CONFIG_DMA_API_DEBUG
625 u64 limit = (mask + 1) & ~mask;
626 if (limit && size >= limit) {
627 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
636 if (mask < 0xffffffffULL)
640 * Following is a work-around (a.k.a. hack) to prevent pages
641 * with __GFP_COMP being passed to split_page() which cannot
642 * handle them. The real problem is that this flag probably
643 * should be 0 on ARM as it is not supported on this
644 * platform; see CONFIG_HUGETLBFS.
646 gfp &= ~(__GFP_COMP);
648 *handle = DMA_ERROR_CODE;
649 size = PAGE_ALIGN(size);
650 want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
653 addr = __alloc_simple_buffer(dev, size, gfp, &page);
654 else if (dev_get_cma_area(dev) && (gfp & __GFP_WAIT))
655 addr = __alloc_from_contiguous(dev, size, prot, &page,
657 else if (is_coherent)
658 addr = __alloc_simple_buffer(dev, size, gfp, &page);
659 else if (!(gfp & __GFP_WAIT))
660 addr = __alloc_from_pool(size, &page);
662 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page,
666 *handle = pfn_to_dma(dev, page_to_pfn(page));
668 return want_vaddr ? addr : page;
672 * Allocate DMA-coherent memory space and return both the kernel remapped
673 * virtual and bus address for that space.
675 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
676 gfp_t gfp, struct dma_attrs *attrs)
678 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
680 return __dma_alloc(dev, size, handle, gfp, prot, false,
681 attrs, __builtin_return_address(0));
684 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
685 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
687 return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true,
688 attrs, __builtin_return_address(0));
691 static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
692 void *cpu_addr, dma_addr_t dma_addr, size_t size,
693 struct dma_attrs *attrs)
697 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
698 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
699 unsigned long pfn = dma_to_pfn(dev, dma_addr);
700 unsigned long off = vma->vm_pgoff;
702 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
705 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
706 ret = remap_pfn_range(vma, vma->vm_start,
708 vma->vm_end - vma->vm_start,
711 #endif /* CONFIG_MMU */
717 * Create userspace mapping for the DMA-coherent memory.
719 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
720 void *cpu_addr, dma_addr_t dma_addr, size_t size,
721 struct dma_attrs *attrs)
723 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
726 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
727 void *cpu_addr, dma_addr_t dma_addr, size_t size,
728 struct dma_attrs *attrs)
731 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
732 #endif /* CONFIG_MMU */
733 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
737 * Free a buffer as defined by the above mapping.
739 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
740 dma_addr_t handle, struct dma_attrs *attrs,
743 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
744 bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs);
746 size = PAGE_ALIGN(size);
749 __dma_free_buffer(page, size);
750 } else if (!is_coherent && __free_from_pool(cpu_addr, size)) {
752 } else if (!dev_get_cma_area(dev)) {
753 if (want_vaddr && !is_coherent)
754 __dma_free_remap(cpu_addr, size);
755 __dma_free_buffer(page, size);
758 * Non-atomic allocations cannot be freed with IRQs disabled
760 WARN_ON(irqs_disabled());
761 __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr);
765 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
766 dma_addr_t handle, struct dma_attrs *attrs)
768 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
771 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
772 dma_addr_t handle, struct dma_attrs *attrs)
774 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
777 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
778 void *cpu_addr, dma_addr_t handle, size_t size,
779 struct dma_attrs *attrs)
781 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
784 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
788 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
792 static void dma_cache_maint_page(struct page *page, unsigned long offset,
793 size_t size, enum dma_data_direction dir,
794 void (*op)(const void *, size_t, int))
799 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
803 * A single sg entry may refer to multiple physically contiguous
804 * pages. But we still need to process highmem pages individually.
805 * If highmem is not configured then the bulk of this loop gets
812 page = pfn_to_page(pfn);
814 if (PageHighMem(page)) {
815 if (len + offset > PAGE_SIZE)
816 len = PAGE_SIZE - offset;
818 if (cache_is_vipt_nonaliasing()) {
819 vaddr = kmap_atomic(page);
820 op(vaddr + offset, len, dir);
821 kunmap_atomic(vaddr);
823 vaddr = kmap_high_get(page);
825 op(vaddr + offset, len, dir);
830 vaddr = page_address(page) + offset;
840 * Make an area consistent for devices.
841 * Note: Drivers should NOT use this function directly, as it will break
842 * platforms with CONFIG_DMABOUNCE.
843 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
845 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
846 size_t size, enum dma_data_direction dir)
850 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
852 paddr = page_to_phys(page) + off;
853 if (dir == DMA_FROM_DEVICE) {
854 outer_inv_range(paddr, paddr + size);
856 outer_clean_range(paddr, paddr + size);
858 /* FIXME: non-speculating: flush on bidirectional mappings? */
861 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
862 size_t size, enum dma_data_direction dir)
864 phys_addr_t paddr = page_to_phys(page) + off;
866 /* FIXME: non-speculating: not required */
867 /* in any case, don't bother invalidating if DMA to device */
868 if (dir != DMA_TO_DEVICE) {
869 outer_inv_range(paddr, paddr + size);
871 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
875 * Mark the D-cache clean for these pages to avoid extra flushing.
877 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
881 pfn = page_to_pfn(page) + off / PAGE_SIZE;
885 left -= PAGE_SIZE - off;
887 while (left >= PAGE_SIZE) {
888 page = pfn_to_page(pfn++);
889 set_bit(PG_dcache_clean, &page->flags);
896 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
897 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
898 * @sg: list of buffers
899 * @nents: number of buffers to map
900 * @dir: DMA transfer direction
902 * Map a set of buffers described by scatterlist in streaming mode for DMA.
903 * This is the scatter-gather version of the dma_map_single interface.
904 * Here the scatter gather list elements are each tagged with the
905 * appropriate dma address and length. They are obtained via
906 * sg_dma_{address,length}.
908 * Device ownership issues as mentioned for dma_map_single are the same
911 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
912 enum dma_data_direction dir, struct dma_attrs *attrs)
914 struct dma_map_ops *ops = get_dma_ops(dev);
915 struct scatterlist *s;
918 for_each_sg(sg, s, nents, i) {
919 #ifdef CONFIG_NEED_SG_DMA_LENGTH
920 s->dma_length = s->length;
922 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
923 s->length, dir, attrs);
924 if (dma_mapping_error(dev, s->dma_address))
930 for_each_sg(sg, s, i, j)
931 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
936 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
937 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
938 * @sg: list of buffers
939 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
940 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
942 * Unmap a set of streaming mode DMA translations. Again, CPU access
943 * rules concerning calls here are the same as for dma_unmap_single().
945 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
946 enum dma_data_direction dir, struct dma_attrs *attrs)
948 struct dma_map_ops *ops = get_dma_ops(dev);
949 struct scatterlist *s;
953 for_each_sg(sg, s, nents, i)
954 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
958 * arm_dma_sync_sg_for_cpu
959 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
960 * @sg: list of buffers
961 * @nents: number of buffers to map (returned from dma_map_sg)
962 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
964 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
965 int nents, enum dma_data_direction dir)
967 struct dma_map_ops *ops = get_dma_ops(dev);
968 struct scatterlist *s;
971 for_each_sg(sg, s, nents, i)
972 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
977 * arm_dma_sync_sg_for_device
978 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
979 * @sg: list of buffers
980 * @nents: number of buffers to map (returned from dma_map_sg)
981 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
983 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
984 int nents, enum dma_data_direction dir)
986 struct dma_map_ops *ops = get_dma_ops(dev);
987 struct scatterlist *s;
990 for_each_sg(sg, s, nents, i)
991 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
996 * Return whether the given device DMA address mask can be supported
997 * properly. For example, if your device can only drive the low 24-bits
998 * during bus mastering, then you would pass 0x00ffffff as the mask
1001 int dma_supported(struct device *dev, u64 mask)
1003 return __dma_supported(dev, mask, false);
1005 EXPORT_SYMBOL(dma_supported);
1007 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1009 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1012 *dev->dma_mask = dma_mask;
1017 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1019 static int __init dma_debug_do_init(void)
1021 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1024 fs_initcall(dma_debug_do_init);
1026 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1030 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1032 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1035 unsigned int order = get_order(size);
1036 unsigned int align = 0;
1037 unsigned int count, start;
1038 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1039 unsigned long flags;
1043 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1044 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1046 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1047 align = (1 << order) - 1;
1049 spin_lock_irqsave(&mapping->lock, flags);
1050 for (i = 0; i < mapping->nr_bitmaps; i++) {
1051 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1052 mapping->bits, 0, count, align);
1054 if (start > mapping->bits)
1057 bitmap_set(mapping->bitmaps[i], start, count);
1062 * No unused range found. Try to extend the existing mapping
1063 * and perform a second attempt to reserve an IO virtual
1064 * address range of size bytes.
1066 if (i == mapping->nr_bitmaps) {
1067 if (extend_iommu_mapping(mapping)) {
1068 spin_unlock_irqrestore(&mapping->lock, flags);
1069 return DMA_ERROR_CODE;
1072 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1073 mapping->bits, 0, count, align);
1075 if (start > mapping->bits) {
1076 spin_unlock_irqrestore(&mapping->lock, flags);
1077 return DMA_ERROR_CODE;
1080 bitmap_set(mapping->bitmaps[i], start, count);
1082 spin_unlock_irqrestore(&mapping->lock, flags);
1084 iova = mapping->base + (mapping_size * i);
1085 iova += start << PAGE_SHIFT;
1090 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1091 dma_addr_t addr, size_t size)
1093 unsigned int start, count;
1094 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1095 unsigned long flags;
1096 dma_addr_t bitmap_base;
1102 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1103 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1105 bitmap_base = mapping->base + mapping_size * bitmap_index;
1107 start = (addr - bitmap_base) >> PAGE_SHIFT;
1109 if (addr + size > bitmap_base + mapping_size) {
1111 * The address range to be freed reaches into the iova
1112 * range of the next bitmap. This should not happen as
1113 * we don't allow this in __alloc_iova (at the
1118 count = size >> PAGE_SHIFT;
1120 spin_lock_irqsave(&mapping->lock, flags);
1121 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1122 spin_unlock_irqrestore(&mapping->lock, flags);
1125 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1126 gfp_t gfp, struct dma_attrs *attrs)
1128 struct page **pages;
1129 int count = size >> PAGE_SHIFT;
1130 int array_size = count * sizeof(struct page *);
1133 if (array_size <= PAGE_SIZE)
1134 pages = kzalloc(array_size, GFP_KERNEL);
1136 pages = vzalloc(array_size);
1140 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1142 unsigned long order = get_order(size);
1145 page = dma_alloc_from_contiguous(dev, count, order);
1149 __dma_clear_buffer(page, size);
1151 for (i = 0; i < count; i++)
1152 pages[i] = page + i;
1158 * IOMMU can map any pages, so himem can also be used here
1160 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1165 for (order = __fls(count); order > 0; --order) {
1167 * We do not want OOM killer to be invoked as long
1168 * as we can fall back to single pages, so we force
1169 * __GFP_NORETRY for orders higher than zero.
1171 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1178 * Fall back to single page allocation.
1179 * Might invoke OOM killer as last resort.
1181 pages[i] = alloc_pages(gfp, 0);
1187 split_page(pages[i], order);
1190 pages[i + j] = pages[i] + j;
1193 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1195 count -= 1 << order;
1202 __free_pages(pages[i], 0);
1203 if (array_size <= PAGE_SIZE)
1210 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1211 size_t size, struct dma_attrs *attrs)
1213 int count = size >> PAGE_SHIFT;
1214 int array_size = count * sizeof(struct page *);
1217 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1218 dma_release_from_contiguous(dev, pages[0], count);
1220 for (i = 0; i < count; i++)
1222 __free_pages(pages[i], 0);
1225 if (array_size <= PAGE_SIZE)
1233 * Create a CPU mapping for a specified pages
1236 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1239 return dma_common_pages_remap(pages, size,
1240 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1244 * Create a mapping in device IO address space for specified pages
1247 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1249 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1250 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1251 dma_addr_t dma_addr, iova;
1252 int i, ret = DMA_ERROR_CODE;
1254 dma_addr = __alloc_iova(mapping, size);
1255 if (dma_addr == DMA_ERROR_CODE)
1259 for (i = 0; i < count; ) {
1260 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1261 phys_addr_t phys = page_to_phys(pages[i]);
1262 unsigned int len, j;
1264 for (j = i + 1; j < count; j++, next_pfn++)
1265 if (page_to_pfn(pages[j]) != next_pfn)
1268 len = (j - i) << PAGE_SHIFT;
1269 ret = iommu_map(mapping->domain, iova, phys, len,
1270 IOMMU_READ|IOMMU_WRITE);
1278 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1279 __free_iova(mapping, dma_addr, size);
1280 return DMA_ERROR_CODE;
1283 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1285 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1288 * add optional in-page offset from iova to size and align
1289 * result to page size
1291 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1294 iommu_unmap(mapping->domain, iova, size);
1295 __free_iova(mapping, iova, size);
1299 static struct page **__atomic_get_pages(void *addr)
1304 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1305 page = phys_to_page(phys);
1307 return (struct page **)page;
1310 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1312 struct vm_struct *area;
1314 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1315 return __atomic_get_pages(cpu_addr);
1317 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1320 area = find_vm_area(cpu_addr);
1321 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1326 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1332 addr = __alloc_from_pool(size, &page);
1336 *handle = __iommu_create_mapping(dev, &page, size);
1337 if (*handle == DMA_ERROR_CODE)
1343 __free_from_pool(addr, size);
1347 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1348 dma_addr_t handle, size_t size)
1350 __iommu_remove_mapping(dev, handle, size);
1351 __free_from_pool(cpu_addr, size);
1354 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1355 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1357 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1358 struct page **pages;
1361 *handle = DMA_ERROR_CODE;
1362 size = PAGE_ALIGN(size);
1364 if (!(gfp & __GFP_WAIT))
1365 return __iommu_alloc_atomic(dev, size, handle);
1368 * Following is a work-around (a.k.a. hack) to prevent pages
1369 * with __GFP_COMP being passed to split_page() which cannot
1370 * handle them. The real problem is that this flag probably
1371 * should be 0 on ARM as it is not supported on this
1372 * platform; see CONFIG_HUGETLBFS.
1374 gfp &= ~(__GFP_COMP);
1376 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1380 *handle = __iommu_create_mapping(dev, pages, size);
1381 if (*handle == DMA_ERROR_CODE)
1384 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1387 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1388 __builtin_return_address(0));
1395 __iommu_remove_mapping(dev, *handle, size);
1397 __iommu_free_buffer(dev, pages, size, attrs);
1401 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1402 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1403 struct dma_attrs *attrs)
1405 unsigned long uaddr = vma->vm_start;
1406 unsigned long usize = vma->vm_end - vma->vm_start;
1407 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1409 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1415 int ret = vm_insert_page(vma, uaddr, *pages++);
1417 pr_err("Remapping memory failed: %d\n", ret);
1422 } while (usize > 0);
1428 * free a page as defined by the above mapping.
1429 * Must not be called with IRQs disabled.
1431 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1432 dma_addr_t handle, struct dma_attrs *attrs)
1434 struct page **pages;
1435 size = PAGE_ALIGN(size);
1437 if (__in_atomic_pool(cpu_addr, size)) {
1438 __iommu_free_atomic(dev, cpu_addr, handle, size);
1442 pages = __iommu_get_pages(cpu_addr, attrs);
1444 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1448 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1449 dma_common_free_remap(cpu_addr, size,
1450 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1453 __iommu_remove_mapping(dev, handle, size);
1454 __iommu_free_buffer(dev, pages, size, attrs);
1457 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1458 void *cpu_addr, dma_addr_t dma_addr,
1459 size_t size, struct dma_attrs *attrs)
1461 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1462 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1467 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1471 static int __dma_direction_to_prot(enum dma_data_direction dir)
1476 case DMA_BIDIRECTIONAL:
1477 prot = IOMMU_READ | IOMMU_WRITE;
1482 case DMA_FROM_DEVICE:
1493 * Map a part of the scatter-gather list into contiguous io address space
1495 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1496 size_t size, dma_addr_t *handle,
1497 enum dma_data_direction dir, struct dma_attrs *attrs,
1500 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1501 dma_addr_t iova, iova_base;
1504 struct scatterlist *s;
1507 size = PAGE_ALIGN(size);
1508 *handle = DMA_ERROR_CODE;
1510 iova_base = iova = __alloc_iova(mapping, size);
1511 if (iova == DMA_ERROR_CODE)
1514 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1515 phys_addr_t phys = sg_phys(s) & PAGE_MASK;
1516 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1519 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1520 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1522 prot = __dma_direction_to_prot(dir);
1524 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1527 count += len >> PAGE_SHIFT;
1530 *handle = iova_base;
1534 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1535 __free_iova(mapping, iova_base, size);
1539 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1540 enum dma_data_direction dir, struct dma_attrs *attrs,
1543 struct scatterlist *s = sg, *dma = sg, *start = sg;
1545 unsigned int offset = s->offset;
1546 unsigned int size = s->offset + s->length;
1547 unsigned int max = dma_get_max_seg_size(dev);
1549 for (i = 1; i < nents; i++) {
1552 s->dma_address = DMA_ERROR_CODE;
1555 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1556 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1557 dir, attrs, is_coherent) < 0)
1560 dma->dma_address += offset;
1561 dma->dma_length = size - offset;
1563 size = offset = s->offset;
1570 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1574 dma->dma_address += offset;
1575 dma->dma_length = size - offset;
1580 for_each_sg(sg, s, count, i)
1581 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1586 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1587 * @dev: valid struct device pointer
1588 * @sg: list of buffers
1589 * @nents: number of buffers to map
1590 * @dir: DMA transfer direction
1592 * Map a set of i/o coherent buffers described by scatterlist in streaming
1593 * mode for DMA. The scatter gather list elements are merged together (if
1594 * possible) and tagged with the appropriate dma address and length. They are
1595 * obtained via sg_dma_{address,length}.
1597 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1598 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1600 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1604 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1605 * @dev: valid struct device pointer
1606 * @sg: list of buffers
1607 * @nents: number of buffers to map
1608 * @dir: DMA transfer direction
1610 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1611 * The scatter gather list elements are merged together (if possible) and
1612 * tagged with the appropriate dma address and length. They are obtained via
1613 * sg_dma_{address,length}.
1615 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1616 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1618 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1621 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1622 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1625 struct scatterlist *s;
1628 for_each_sg(sg, s, nents, i) {
1630 __iommu_remove_mapping(dev, sg_dma_address(s),
1633 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1634 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1640 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1641 * @dev: valid struct device pointer
1642 * @sg: list of buffers
1643 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1644 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1646 * Unmap a set of streaming mode DMA translations. Again, CPU access
1647 * rules concerning calls here are the same as for dma_unmap_single().
1649 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1650 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1652 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1656 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1657 * @dev: valid struct device pointer
1658 * @sg: list of buffers
1659 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1660 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1662 * Unmap a set of streaming mode DMA translations. Again, CPU access
1663 * rules concerning calls here are the same as for dma_unmap_single().
1665 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1666 enum dma_data_direction dir, struct dma_attrs *attrs)
1668 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1672 * arm_iommu_sync_sg_for_cpu
1673 * @dev: valid struct device pointer
1674 * @sg: list of buffers
1675 * @nents: number of buffers to map (returned from dma_map_sg)
1676 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1678 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1679 int nents, enum dma_data_direction dir)
1681 struct scatterlist *s;
1684 for_each_sg(sg, s, nents, i)
1685 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1690 * arm_iommu_sync_sg_for_device
1691 * @dev: valid struct device pointer
1692 * @sg: list of buffers
1693 * @nents: number of buffers to map (returned from dma_map_sg)
1694 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1696 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1697 int nents, enum dma_data_direction dir)
1699 struct scatterlist *s;
1702 for_each_sg(sg, s, nents, i)
1703 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1708 * arm_coherent_iommu_map_page
1709 * @dev: valid struct device pointer
1710 * @page: page that buffer resides in
1711 * @offset: offset into page for start of buffer
1712 * @size: size of buffer to map
1713 * @dir: DMA transfer direction
1715 * Coherent IOMMU aware version of arm_dma_map_page()
1717 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1718 unsigned long offset, size_t size, enum dma_data_direction dir,
1719 struct dma_attrs *attrs)
1721 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1722 dma_addr_t dma_addr;
1723 int ret, prot, len = PAGE_ALIGN(size + offset);
1725 dma_addr = __alloc_iova(mapping, len);
1726 if (dma_addr == DMA_ERROR_CODE)
1729 prot = __dma_direction_to_prot(dir);
1731 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1735 return dma_addr + offset;
1737 __free_iova(mapping, dma_addr, len);
1738 return DMA_ERROR_CODE;
1742 * arm_iommu_map_page
1743 * @dev: valid struct device pointer
1744 * @page: page that buffer resides in
1745 * @offset: offset into page for start of buffer
1746 * @size: size of buffer to map
1747 * @dir: DMA transfer direction
1749 * IOMMU aware version of arm_dma_map_page()
1751 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1752 unsigned long offset, size_t size, enum dma_data_direction dir,
1753 struct dma_attrs *attrs)
1755 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1756 __dma_page_cpu_to_dev(page, offset, size, dir);
1758 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1762 * arm_coherent_iommu_unmap_page
1763 * @dev: valid struct device pointer
1764 * @handle: DMA address of buffer
1765 * @size: size of buffer (same as passed to dma_map_page)
1766 * @dir: DMA transfer direction (same as passed to dma_map_page)
1768 * Coherent IOMMU aware version of arm_dma_unmap_page()
1770 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1771 size_t size, enum dma_data_direction dir,
1772 struct dma_attrs *attrs)
1774 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1775 dma_addr_t iova = handle & PAGE_MASK;
1776 int offset = handle & ~PAGE_MASK;
1777 int len = PAGE_ALIGN(size + offset);
1782 iommu_unmap(mapping->domain, iova, len);
1783 __free_iova(mapping, iova, len);
1787 * arm_iommu_unmap_page
1788 * @dev: valid struct device pointer
1789 * @handle: DMA address of buffer
1790 * @size: size of buffer (same as passed to dma_map_page)
1791 * @dir: DMA transfer direction (same as passed to dma_map_page)
1793 * IOMMU aware version of arm_dma_unmap_page()
1795 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1796 size_t size, enum dma_data_direction dir,
1797 struct dma_attrs *attrs)
1799 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1800 dma_addr_t iova = handle & PAGE_MASK;
1801 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1802 int offset = handle & ~PAGE_MASK;
1803 int len = PAGE_ALIGN(size + offset);
1808 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1809 __dma_page_dev_to_cpu(page, offset, size, dir);
1811 iommu_unmap(mapping->domain, iova, len);
1812 __free_iova(mapping, iova, len);
1815 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1816 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1818 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1819 dma_addr_t iova = handle & PAGE_MASK;
1820 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1821 unsigned int offset = handle & ~PAGE_MASK;
1826 __dma_page_dev_to_cpu(page, offset, size, dir);
1829 static void arm_iommu_sync_single_for_device(struct device *dev,
1830 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1832 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1833 dma_addr_t iova = handle & PAGE_MASK;
1834 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1835 unsigned int offset = handle & ~PAGE_MASK;
1840 __dma_page_cpu_to_dev(page, offset, size, dir);
1843 struct dma_map_ops iommu_ops = {
1844 .alloc = arm_iommu_alloc_attrs,
1845 .free = arm_iommu_free_attrs,
1846 .mmap = arm_iommu_mmap_attrs,
1847 .get_sgtable = arm_iommu_get_sgtable,
1849 .map_page = arm_iommu_map_page,
1850 .unmap_page = arm_iommu_unmap_page,
1851 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1852 .sync_single_for_device = arm_iommu_sync_single_for_device,
1854 .map_sg = arm_iommu_map_sg,
1855 .unmap_sg = arm_iommu_unmap_sg,
1856 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1857 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1859 .set_dma_mask = arm_dma_set_mask,
1862 struct dma_map_ops iommu_coherent_ops = {
1863 .alloc = arm_iommu_alloc_attrs,
1864 .free = arm_iommu_free_attrs,
1865 .mmap = arm_iommu_mmap_attrs,
1866 .get_sgtable = arm_iommu_get_sgtable,
1868 .map_page = arm_coherent_iommu_map_page,
1869 .unmap_page = arm_coherent_iommu_unmap_page,
1871 .map_sg = arm_coherent_iommu_map_sg,
1872 .unmap_sg = arm_coherent_iommu_unmap_sg,
1874 .set_dma_mask = arm_dma_set_mask,
1878 * arm_iommu_create_mapping
1879 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1880 * @base: start address of the valid IO address space
1881 * @size: maximum size of the valid IO address space
1883 * Creates a mapping structure which holds information about used/unused
1884 * IO address ranges, which is required to perform memory allocation and
1885 * mapping with IOMMU aware functions.
1887 * The client device need to be attached to the mapping with
1888 * arm_iommu_attach_device function.
1890 struct dma_iommu_mapping *
1891 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
1893 unsigned int bits = size >> PAGE_SHIFT;
1894 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1895 struct dma_iommu_mapping *mapping;
1899 /* currently only 32-bit DMA address space is supported */
1900 if (size > DMA_BIT_MASK(32) + 1)
1901 return ERR_PTR(-ERANGE);
1904 return ERR_PTR(-EINVAL);
1906 if (bitmap_size > PAGE_SIZE) {
1907 extensions = bitmap_size / PAGE_SIZE;
1908 bitmap_size = PAGE_SIZE;
1911 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1915 mapping->bitmap_size = bitmap_size;
1916 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1918 if (!mapping->bitmaps)
1921 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1922 if (!mapping->bitmaps[0])
1925 mapping->nr_bitmaps = 1;
1926 mapping->extensions = extensions;
1927 mapping->base = base;
1928 mapping->bits = BITS_PER_BYTE * bitmap_size;
1930 spin_lock_init(&mapping->lock);
1932 mapping->domain = iommu_domain_alloc(bus);
1933 if (!mapping->domain)
1936 kref_init(&mapping->kref);
1939 kfree(mapping->bitmaps[0]);
1941 kfree(mapping->bitmaps);
1945 return ERR_PTR(err);
1947 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1949 static void release_iommu_mapping(struct kref *kref)
1952 struct dma_iommu_mapping *mapping =
1953 container_of(kref, struct dma_iommu_mapping, kref);
1955 iommu_domain_free(mapping->domain);
1956 for (i = 0; i < mapping->nr_bitmaps; i++)
1957 kfree(mapping->bitmaps[i]);
1958 kfree(mapping->bitmaps);
1962 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
1966 if (mapping->nr_bitmaps >= mapping->extensions)
1969 next_bitmap = mapping->nr_bitmaps;
1970 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
1972 if (!mapping->bitmaps[next_bitmap])
1975 mapping->nr_bitmaps++;
1980 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1983 kref_put(&mapping->kref, release_iommu_mapping);
1985 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1987 static int __arm_iommu_attach_device(struct device *dev,
1988 struct dma_iommu_mapping *mapping)
1992 err = iommu_attach_device(mapping->domain, dev);
1996 kref_get(&mapping->kref);
1997 to_dma_iommu_mapping(dev) = mapping;
1999 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2004 * arm_iommu_attach_device
2005 * @dev: valid struct device pointer
2006 * @mapping: io address space mapping structure (returned from
2007 * arm_iommu_create_mapping)
2009 * Attaches specified io address space mapping to the provided device.
2010 * This replaces the dma operations (dma_map_ops pointer) with the
2011 * IOMMU aware version.
2013 * More than one client might be attached to the same io address space
2016 int arm_iommu_attach_device(struct device *dev,
2017 struct dma_iommu_mapping *mapping)
2021 err = __arm_iommu_attach_device(dev, mapping);
2025 set_dma_ops(dev, &iommu_ops);
2028 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2030 static void __arm_iommu_detach_device(struct device *dev)
2032 struct dma_iommu_mapping *mapping;
2034 mapping = to_dma_iommu_mapping(dev);
2036 dev_warn(dev, "Not attached\n");
2040 iommu_detach_device(mapping->domain, dev);
2041 kref_put(&mapping->kref, release_iommu_mapping);
2042 to_dma_iommu_mapping(dev) = NULL;
2044 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2048 * arm_iommu_detach_device
2049 * @dev: valid struct device pointer
2051 * Detaches the provided device from a previously attached map.
2052 * This voids the dma operations (dma_map_ops pointer)
2054 void arm_iommu_detach_device(struct device *dev)
2056 __arm_iommu_detach_device(dev);
2057 set_dma_ops(dev, NULL);
2059 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2061 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2063 return coherent ? &iommu_coherent_ops : &iommu_ops;
2066 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2067 struct iommu_ops *iommu)
2069 struct dma_iommu_mapping *mapping;
2074 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2075 if (IS_ERR(mapping)) {
2076 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2077 size, dev_name(dev));
2081 if (__arm_iommu_attach_device(dev, mapping)) {
2082 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2084 arm_iommu_release_mapping(mapping);
2091 static void arm_teardown_iommu_dma_ops(struct device *dev)
2093 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2098 __arm_iommu_detach_device(dev);
2099 arm_iommu_release_mapping(mapping);
2104 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2105 struct iommu_ops *iommu)
2110 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2112 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2114 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2116 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2118 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2121 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2122 struct iommu_ops *iommu, bool coherent)
2124 struct dma_map_ops *dma_ops;
2126 dev->archdata.dma_coherent = coherent;
2127 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2128 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2130 dma_ops = arm_get_dma_map_ops(coherent);
2132 set_dma_ops(dev, dma_ops);
2135 void arch_teardown_dma_ops(struct device *dev)
2137 arm_teardown_iommu_dma_ops(dev);