2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/gfp.h>
16 #include <linux/errno.h>
17 #include <linux/list.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dma-contiguous.h>
22 #include <linux/highmem.h>
23 #include <linux/memblock.h>
24 #include <linux/slab.h>
25 #include <linux/iommu.h>
27 #include <linux/vmalloc.h>
28 #include <linux/sizes.h>
30 #include <asm/memory.h>
31 #include <asm/highmem.h>
32 #include <asm/cacheflush.h>
33 #include <asm/tlbflush.h>
34 #include <asm/mach/arch.h>
35 #include <asm/dma-iommu.h>
36 #include <asm/mach/map.h>
37 #include <asm/system_info.h>
38 #include <asm/dma-contiguous.h>
43 * The DMA API is built upon the notion of "buffer ownership". A buffer
44 * is either exclusively owned by the CPU (and therefore may be accessed
45 * by it) or exclusively owned by the DMA device. These helper functions
46 * represent the transitions between these two ownership states.
48 * Note, however, that on later ARMs, this notion does not work due to
49 * speculative prefetches. We model our approach on the assumption that
50 * the CPU does do speculative prefetches, which means we clean caches
51 * before transfers and delay cache invalidation until transfer completion.
54 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
55 size_t, enum dma_data_direction);
56 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
57 size_t, enum dma_data_direction);
60 * arm_dma_map_page - map a portion of a page for streaming DMA
61 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
62 * @page: page that buffer resides in
63 * @offset: offset into page for start of buffer
64 * @size: size of buffer to map
65 * @dir: DMA transfer direction
67 * Ensure that any data held in the cache is appropriately discarded
70 * The device owns this memory once this call has completed. The CPU
71 * can regain ownership by calling dma_unmap_page().
73 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
74 unsigned long offset, size_t size, enum dma_data_direction dir,
75 struct dma_attrs *attrs)
77 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
78 __dma_page_cpu_to_dev(page, offset, size, dir);
79 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
82 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
83 unsigned long offset, size_t size, enum dma_data_direction dir,
84 struct dma_attrs *attrs)
86 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
90 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
91 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
92 * @handle: DMA address of buffer
93 * @size: size of buffer (same as passed to dma_map_page)
94 * @dir: DMA transfer direction (same as passed to dma_map_page)
96 * Unmap a page streaming mode DMA translation. The handle and size
97 * must match what was provided in the previous dma_map_page() call.
98 * All other usages are undefined.
100 * After this call, reads by the CPU to the buffer are guaranteed to see
101 * whatever the device wrote there.
103 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
104 size_t size, enum dma_data_direction dir,
105 struct dma_attrs *attrs)
107 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
108 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
109 handle & ~PAGE_MASK, size, dir);
112 static void arm_dma_sync_single_for_cpu(struct device *dev,
113 dma_addr_t handle, size_t size, enum dma_data_direction dir)
115 unsigned int offset = handle & (PAGE_SIZE - 1);
116 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
117 __dma_page_dev_to_cpu(page, offset, size, dir);
120 static void arm_dma_sync_single_for_device(struct device *dev,
121 dma_addr_t handle, size_t size, enum dma_data_direction dir)
123 unsigned int offset = handle & (PAGE_SIZE - 1);
124 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
125 __dma_page_cpu_to_dev(page, offset, size, dir);
128 struct dma_map_ops arm_dma_ops = {
129 .alloc = arm_dma_alloc,
130 .free = arm_dma_free,
131 .mmap = arm_dma_mmap,
132 .get_sgtable = arm_dma_get_sgtable,
133 .map_page = arm_dma_map_page,
134 .unmap_page = arm_dma_unmap_page,
135 .map_sg = arm_dma_map_sg,
136 .unmap_sg = arm_dma_unmap_sg,
137 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
138 .sync_single_for_device = arm_dma_sync_single_for_device,
139 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
140 .sync_sg_for_device = arm_dma_sync_sg_for_device,
141 .set_dma_mask = arm_dma_set_mask,
143 EXPORT_SYMBOL(arm_dma_ops);
145 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
146 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
147 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
148 dma_addr_t handle, struct dma_attrs *attrs);
150 struct dma_map_ops arm_coherent_dma_ops = {
151 .alloc = arm_coherent_dma_alloc,
152 .free = arm_coherent_dma_free,
153 .mmap = arm_dma_mmap,
154 .get_sgtable = arm_dma_get_sgtable,
155 .map_page = arm_coherent_dma_map_page,
156 .map_sg = arm_dma_map_sg,
157 .set_dma_mask = arm_dma_set_mask,
159 EXPORT_SYMBOL(arm_coherent_dma_ops);
161 static int __dma_supported(struct device *dev, u64 mask, bool warn)
163 unsigned long max_dma_pfn;
166 * If the mask allows for more memory than we can address,
167 * and we actually have that much memory, then we must
168 * indicate that DMA to this device is not supported.
170 if (sizeof(mask) != sizeof(dma_addr_t) &&
171 mask > (dma_addr_t)~0 &&
172 dma_to_pfn(dev, ~0) < max_pfn) {
174 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
176 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
181 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
184 * Translate the device's DMA mask to a PFN limit. This
185 * PFN number includes the page which we can DMA to.
187 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
189 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
191 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
199 static u64 get_coherent_dma_mask(struct device *dev)
201 u64 mask = (u64)DMA_BIT_MASK(32);
204 mask = dev->coherent_dma_mask;
207 * Sanity check the DMA mask - it must be non-zero, and
208 * must be able to be satisfied by a DMA allocation.
211 dev_warn(dev, "coherent DMA mask is unset\n");
215 if (!__dma_supported(dev, mask, true))
222 static void __dma_clear_buffer(struct page *page, size_t size)
225 * Ensure that the allocated pages are zeroed, and that any data
226 * lurking in the kernel direct-mapped region is invalidated.
228 if (PageHighMem(page)) {
229 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
230 phys_addr_t end = base + size;
232 void *ptr = kmap_atomic(page);
233 memset(ptr, 0, PAGE_SIZE);
234 dmac_flush_range(ptr, ptr + PAGE_SIZE);
239 outer_flush_range(base, end);
241 void *ptr = page_address(page);
242 memset(ptr, 0, size);
243 dmac_flush_range(ptr, ptr + size);
244 outer_flush_range(__pa(ptr), __pa(ptr) + size);
249 * Allocate a DMA buffer for 'dev' of size 'size' using the
250 * specified gfp mask. Note that 'size' must be page aligned.
252 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
254 unsigned long order = get_order(size);
255 struct page *page, *p, *e;
257 page = alloc_pages(gfp, order);
262 * Now split the huge page and free the excess pages
264 split_page(page, order);
265 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
268 __dma_clear_buffer(page, size);
274 * Free a DMA buffer. 'size' must be page aligned.
276 static void __dma_free_buffer(struct page *page, size_t size)
278 struct page *e = page + (size >> PAGE_SHIFT);
287 #ifdef CONFIG_HUGETLB_PAGE
288 #warning ARM Coherent DMA allocator does not (yet) support huge TLB
291 static void *__alloc_from_contiguous(struct device *dev, size_t size,
292 pgprot_t prot, struct page **ret_page,
295 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
296 pgprot_t prot, struct page **ret_page,
300 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
303 struct vm_struct *area;
307 * DMA allocation can be mapped to user space, so lets
308 * set VM_USERMAP flags too.
310 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
314 addr = (unsigned long)area->addr;
315 area->phys_addr = __pfn_to_phys(page_to_pfn(page));
317 if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
318 vunmap((void *)addr);
324 static void __dma_free_remap(void *cpu_addr, size_t size)
326 unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
327 struct vm_struct *area = find_vm_area(cpu_addr);
328 if (!area || (area->flags & flags) != flags) {
329 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
332 unmap_kernel_range((unsigned long)cpu_addr, size);
336 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
341 unsigned long *bitmap;
342 unsigned long nr_pages;
347 static struct dma_pool atomic_pool = {
348 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
351 static int __init early_coherent_pool(char *p)
353 atomic_pool.size = memparse(p, &p);
356 early_param("coherent_pool", early_coherent_pool);
358 void __init init_dma_coherent_pool_size(unsigned long size)
361 * Catch any attempt to set the pool size too late.
363 BUG_ON(atomic_pool.vaddr);
366 * Set architecture specific coherent pool size only if
367 * it has not been changed by kernel command line parameter.
369 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
370 atomic_pool.size = size;
374 * Initialise the coherent pool for atomic allocations.
376 static int __init atomic_pool_init(void)
378 struct dma_pool *pool = &atomic_pool;
379 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
380 gfp_t gfp = GFP_KERNEL | GFP_DMA;
381 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
382 unsigned long *bitmap;
386 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
388 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
392 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
396 if (IS_ENABLED(CONFIG_DMA_CMA))
397 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
400 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
405 for (i = 0; i < nr_pages; i++)
408 spin_lock_init(&pool->lock);
411 pool->bitmap = bitmap;
412 pool->nr_pages = nr_pages;
413 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
414 (unsigned)pool->size / 1024);
422 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
423 (unsigned)pool->size / 1024);
427 * CMA is activated by core_initcall, so we must be called after it.
429 postcore_initcall(atomic_pool_init);
431 struct dma_contig_early_reserve {
436 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
438 static int dma_mmu_remap_num __initdata;
440 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
442 dma_mmu_remap[dma_mmu_remap_num].base = base;
443 dma_mmu_remap[dma_mmu_remap_num].size = size;
447 void __init dma_contiguous_remap(void)
450 for (i = 0; i < dma_mmu_remap_num; i++) {
451 phys_addr_t start = dma_mmu_remap[i].base;
452 phys_addr_t end = start + dma_mmu_remap[i].size;
456 if (end > arm_lowmem_limit)
457 end = arm_lowmem_limit;
461 map.pfn = __phys_to_pfn(start);
462 map.virtual = __phys_to_virt(start);
463 map.length = end - start;
464 map.type = MT_MEMORY_DMA_READY;
467 * Clear previous low-memory mapping
469 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
471 pmd_clear(pmd_off_k(addr));
473 iotable_init(&map, 1);
477 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
480 struct page *page = virt_to_page(addr);
481 pgprot_t prot = *(pgprot_t *)data;
483 set_pte_ext(pte, mk_pte(page, prot), 0);
487 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
489 unsigned long start = (unsigned long) page_address(page);
490 unsigned end = start + size;
492 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
493 flush_tlb_kernel_range(start, end);
496 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
497 pgprot_t prot, struct page **ret_page,
502 page = __dma_alloc_buffer(dev, size, gfp);
506 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
508 __dma_free_buffer(page, size);
516 static void *__alloc_from_pool(size_t size, struct page **ret_page)
518 struct dma_pool *pool = &atomic_pool;
519 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
523 unsigned long align_mask;
526 WARN(1, "coherent pool not initialised!\n");
531 * Align the region allocation - allocations from pool are rather
532 * small, so align them to their order in pages, minimum is a page
533 * size. This helps reduce fragmentation of the DMA space.
535 align_mask = (1 << get_order(size)) - 1;
537 spin_lock_irqsave(&pool->lock, flags);
538 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
539 0, count, align_mask);
540 if (pageno < pool->nr_pages) {
541 bitmap_set(pool->bitmap, pageno, count);
542 ptr = pool->vaddr + PAGE_SIZE * pageno;
543 *ret_page = pool->pages[pageno];
545 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
546 "Please increase it with coherent_pool= kernel parameter!\n",
547 (unsigned)pool->size / 1024);
549 spin_unlock_irqrestore(&pool->lock, flags);
554 static bool __in_atomic_pool(void *start, size_t size)
556 struct dma_pool *pool = &atomic_pool;
557 void *end = start + size;
558 void *pool_start = pool->vaddr;
559 void *pool_end = pool->vaddr + pool->size;
561 if (start < pool_start || start >= pool_end)
567 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
568 start, end - 1, pool_start, pool_end - 1);
573 static int __free_from_pool(void *start, size_t size)
575 struct dma_pool *pool = &atomic_pool;
576 unsigned long pageno, count;
579 if (!__in_atomic_pool(start, size))
582 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
583 count = size >> PAGE_SHIFT;
585 spin_lock_irqsave(&pool->lock, flags);
586 bitmap_clear(pool->bitmap, pageno, count);
587 spin_unlock_irqrestore(&pool->lock, flags);
592 static void *__alloc_from_contiguous(struct device *dev, size_t size,
593 pgprot_t prot, struct page **ret_page,
596 unsigned long order = get_order(size);
597 size_t count = size >> PAGE_SHIFT;
601 page = dma_alloc_from_contiguous(dev, count, order);
605 __dma_clear_buffer(page, size);
607 if (PageHighMem(page)) {
608 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
610 dma_release_from_contiguous(dev, page, count);
614 __dma_remap(page, size, prot);
615 ptr = page_address(page);
621 static void __free_from_contiguous(struct device *dev, struct page *page,
622 void *cpu_addr, size_t size)
624 if (PageHighMem(page))
625 __dma_free_remap(cpu_addr, size);
627 __dma_remap(page, size, pgprot_kernel);
628 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
631 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
633 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
634 pgprot_writecombine(prot) :
635 pgprot_dmacoherent(prot);
641 #else /* !CONFIG_MMU */
645 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
646 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
647 #define __alloc_from_pool(size, ret_page) NULL
648 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
649 #define __free_from_pool(cpu_addr, size) 0
650 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
651 #define __dma_free_remap(cpu_addr, size) do { } while (0)
653 #endif /* CONFIG_MMU */
655 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
656 struct page **ret_page)
659 page = __dma_alloc_buffer(dev, size, gfp);
664 return page_address(page);
669 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
670 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
672 u64 mask = get_coherent_dma_mask(dev);
673 struct page *page = NULL;
676 #ifdef CONFIG_DMA_API_DEBUG
677 u64 limit = (mask + 1) & ~mask;
678 if (limit && size >= limit) {
679 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
688 if (mask < 0xffffffffULL)
692 * Following is a work-around (a.k.a. hack) to prevent pages
693 * with __GFP_COMP being passed to split_page() which cannot
694 * handle them. The real problem is that this flag probably
695 * should be 0 on ARM as it is not supported on this
696 * platform; see CONFIG_HUGETLBFS.
698 gfp &= ~(__GFP_COMP);
700 *handle = DMA_ERROR_CODE;
701 size = PAGE_ALIGN(size);
703 if (is_coherent || nommu())
704 addr = __alloc_simple_buffer(dev, size, gfp, &page);
705 else if (!(gfp & __GFP_WAIT))
706 addr = __alloc_from_pool(size, &page);
707 else if (!IS_ENABLED(CONFIG_DMA_CMA))
708 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
710 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
713 *handle = pfn_to_dma(dev, page_to_pfn(page));
719 * Allocate DMA-coherent memory space and return both the kernel remapped
720 * virtual and bus address for that space.
722 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
723 gfp_t gfp, struct dma_attrs *attrs)
725 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
728 if (dma_alloc_from_coherent(dev, size, handle, &memory))
731 return __dma_alloc(dev, size, handle, gfp, prot, false,
732 __builtin_return_address(0));
735 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
736 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
738 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
741 if (dma_alloc_from_coherent(dev, size, handle, &memory))
744 return __dma_alloc(dev, size, handle, gfp, prot, true,
745 __builtin_return_address(0));
749 * Create userspace mapping for the DMA-coherent memory.
751 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
752 void *cpu_addr, dma_addr_t dma_addr, size_t size,
753 struct dma_attrs *attrs)
757 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
758 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
759 unsigned long pfn = dma_to_pfn(dev, dma_addr);
760 unsigned long off = vma->vm_pgoff;
762 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
764 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
767 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
768 ret = remap_pfn_range(vma, vma->vm_start,
770 vma->vm_end - vma->vm_start,
773 #endif /* CONFIG_MMU */
779 * Free a buffer as defined by the above mapping.
781 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
782 dma_addr_t handle, struct dma_attrs *attrs,
785 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
787 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
790 size = PAGE_ALIGN(size);
792 if (is_coherent || nommu()) {
793 __dma_free_buffer(page, size);
794 } else if (__free_from_pool(cpu_addr, size)) {
796 } else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
797 __dma_free_remap(cpu_addr, size);
798 __dma_free_buffer(page, size);
801 * Non-atomic allocations cannot be freed with IRQs disabled
803 WARN_ON(irqs_disabled());
804 __free_from_contiguous(dev, page, cpu_addr, size);
808 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
809 dma_addr_t handle, struct dma_attrs *attrs)
811 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
814 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
815 dma_addr_t handle, struct dma_attrs *attrs)
817 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
820 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
821 void *cpu_addr, dma_addr_t handle, size_t size,
822 struct dma_attrs *attrs)
824 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
827 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
831 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
835 static void dma_cache_maint_page(struct page *page, unsigned long offset,
836 size_t size, enum dma_data_direction dir,
837 void (*op)(const void *, size_t, int))
842 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
846 * A single sg entry may refer to multiple physically contiguous
847 * pages. But we still need to process highmem pages individually.
848 * If highmem is not configured then the bulk of this loop gets
855 page = pfn_to_page(pfn);
857 if (PageHighMem(page)) {
858 if (len + offset > PAGE_SIZE)
859 len = PAGE_SIZE - offset;
861 if (cache_is_vipt_nonaliasing()) {
862 vaddr = kmap_atomic(page);
863 op(vaddr + offset, len, dir);
864 kunmap_atomic(vaddr);
866 vaddr = kmap_high_get(page);
868 op(vaddr + offset, len, dir);
873 vaddr = page_address(page) + offset;
883 * Make an area consistent for devices.
884 * Note: Drivers should NOT use this function directly, as it will break
885 * platforms with CONFIG_DMABOUNCE.
886 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
888 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
889 size_t size, enum dma_data_direction dir)
893 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
895 paddr = page_to_phys(page) + off;
896 if (dir == DMA_FROM_DEVICE) {
897 outer_inv_range(paddr, paddr + size);
899 outer_clean_range(paddr, paddr + size);
901 /* FIXME: non-speculating: flush on bidirectional mappings? */
904 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
905 size_t size, enum dma_data_direction dir)
907 unsigned long paddr = page_to_phys(page) + off;
909 /* FIXME: non-speculating: not required */
910 /* don't bother invalidating if DMA to device */
911 if (dir != DMA_TO_DEVICE)
912 outer_inv_range(paddr, paddr + size);
914 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
917 * Mark the D-cache clean for these pages to avoid extra flushing.
919 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
923 pfn = page_to_pfn(page) + off / PAGE_SIZE;
927 left -= PAGE_SIZE - off;
929 while (left >= PAGE_SIZE) {
930 page = pfn_to_page(pfn++);
931 set_bit(PG_dcache_clean, &page->flags);
938 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
939 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
940 * @sg: list of buffers
941 * @nents: number of buffers to map
942 * @dir: DMA transfer direction
944 * Map a set of buffers described by scatterlist in streaming mode for DMA.
945 * This is the scatter-gather version of the dma_map_single interface.
946 * Here the scatter gather list elements are each tagged with the
947 * appropriate dma address and length. They are obtained via
948 * sg_dma_{address,length}.
950 * Device ownership issues as mentioned for dma_map_single are the same
953 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
954 enum dma_data_direction dir, struct dma_attrs *attrs)
956 struct dma_map_ops *ops = get_dma_ops(dev);
957 struct scatterlist *s;
960 for_each_sg(sg, s, nents, i) {
961 #ifdef CONFIG_NEED_SG_DMA_LENGTH
962 s->dma_length = s->length;
964 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
965 s->length, dir, attrs);
966 if (dma_mapping_error(dev, s->dma_address))
972 for_each_sg(sg, s, i, j)
973 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
978 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
979 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
980 * @sg: list of buffers
981 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
982 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
984 * Unmap a set of streaming mode DMA translations. Again, CPU access
985 * rules concerning calls here are the same as for dma_unmap_single().
987 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
988 enum dma_data_direction dir, struct dma_attrs *attrs)
990 struct dma_map_ops *ops = get_dma_ops(dev);
991 struct scatterlist *s;
995 for_each_sg(sg, s, nents, i)
996 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1000 * arm_dma_sync_sg_for_cpu
1001 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1002 * @sg: list of buffers
1003 * @nents: number of buffers to map (returned from dma_map_sg)
1004 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1006 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1007 int nents, enum dma_data_direction dir)
1009 struct dma_map_ops *ops = get_dma_ops(dev);
1010 struct scatterlist *s;
1013 for_each_sg(sg, s, nents, i)
1014 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1019 * arm_dma_sync_sg_for_device
1020 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1021 * @sg: list of buffers
1022 * @nents: number of buffers to map (returned from dma_map_sg)
1023 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1025 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1026 int nents, enum dma_data_direction dir)
1028 struct dma_map_ops *ops = get_dma_ops(dev);
1029 struct scatterlist *s;
1032 for_each_sg(sg, s, nents, i)
1033 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1038 * Return whether the given device DMA address mask can be supported
1039 * properly. For example, if your device can only drive the low 24-bits
1040 * during bus mastering, then you would pass 0x00ffffff as the mask
1043 int dma_supported(struct device *dev, u64 mask)
1045 return __dma_supported(dev, mask, false);
1047 EXPORT_SYMBOL(dma_supported);
1049 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1051 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1054 *dev->dma_mask = dma_mask;
1059 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1061 static int __init dma_debug_do_init(void)
1063 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1066 fs_initcall(dma_debug_do_init);
1068 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1072 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1075 unsigned int order = get_order(size);
1076 unsigned int align = 0;
1077 unsigned int count, start;
1078 unsigned long flags;
1080 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1081 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1083 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1084 (1 << mapping->order) - 1) >> mapping->order;
1086 if (order > mapping->order)
1087 align = (1 << (order - mapping->order)) - 1;
1089 spin_lock_irqsave(&mapping->lock, flags);
1090 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1092 if (start > mapping->bits) {
1093 spin_unlock_irqrestore(&mapping->lock, flags);
1094 return DMA_ERROR_CODE;
1097 bitmap_set(mapping->bitmap, start, count);
1098 spin_unlock_irqrestore(&mapping->lock, flags);
1100 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1103 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1104 dma_addr_t addr, size_t size)
1106 unsigned int start = (addr - mapping->base) >>
1107 (mapping->order + PAGE_SHIFT);
1108 unsigned int count = ((size >> PAGE_SHIFT) +
1109 (1 << mapping->order) - 1) >> mapping->order;
1110 unsigned long flags;
1112 spin_lock_irqsave(&mapping->lock, flags);
1113 bitmap_clear(mapping->bitmap, start, count);
1114 spin_unlock_irqrestore(&mapping->lock, flags);
1117 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1118 gfp_t gfp, struct dma_attrs *attrs)
1120 struct page **pages;
1121 int count = size >> PAGE_SHIFT;
1122 int array_size = count * sizeof(struct page *);
1125 if (array_size <= PAGE_SIZE)
1126 pages = kzalloc(array_size, gfp);
1128 pages = vzalloc(array_size);
1132 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1134 unsigned long order = get_order(size);
1137 page = dma_alloc_from_contiguous(dev, count, order);
1141 __dma_clear_buffer(page, size);
1143 for (i = 0; i < count; i++)
1144 pages[i] = page + i;
1150 * IOMMU can map any pages, so himem can also be used here
1152 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1155 int j, order = __fls(count);
1157 pages[i] = alloc_pages(gfp, order);
1158 while (!pages[i] && order)
1159 pages[i] = alloc_pages(gfp, --order);
1164 split_page(pages[i], order);
1167 pages[i + j] = pages[i] + j;
1170 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1172 count -= 1 << order;
1179 __free_pages(pages[i], 0);
1180 if (array_size <= PAGE_SIZE)
1187 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1188 size_t size, struct dma_attrs *attrs)
1190 int count = size >> PAGE_SHIFT;
1191 int array_size = count * sizeof(struct page *);
1194 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1195 dma_release_from_contiguous(dev, pages[0], count);
1197 for (i = 0; i < count; i++)
1199 __free_pages(pages[i], 0);
1202 if (array_size <= PAGE_SIZE)
1210 * Create a CPU mapping for a specified pages
1213 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1216 unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1217 struct vm_struct *area;
1220 area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
1225 area->pages = pages;
1226 area->nr_pages = nr_pages;
1227 p = (unsigned long)area->addr;
1229 for (i = 0; i < nr_pages; i++) {
1230 phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
1231 if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
1237 unmap_kernel_range((unsigned long)area->addr, size);
1243 * Create a mapping in device IO address space for specified pages
1246 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1248 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1249 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1250 dma_addr_t dma_addr, iova;
1251 int i, ret = DMA_ERROR_CODE;
1253 dma_addr = __alloc_iova(mapping, size);
1254 if (dma_addr == DMA_ERROR_CODE)
1258 for (i = 0; i < count; ) {
1259 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1260 phys_addr_t phys = page_to_phys(pages[i]);
1261 unsigned int len, j;
1263 for (j = i + 1; j < count; j++, next_pfn++)
1264 if (page_to_pfn(pages[j]) != next_pfn)
1267 len = (j - i) << PAGE_SHIFT;
1268 ret = iommu_map(mapping->domain, iova, phys, len,
1269 IOMMU_READ|IOMMU_WRITE);
1277 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1278 __free_iova(mapping, dma_addr, size);
1279 return DMA_ERROR_CODE;
1282 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1284 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1287 * add optional in-page offset from iova to size and align
1288 * result to page size
1290 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1293 iommu_unmap(mapping->domain, iova, size);
1294 __free_iova(mapping, iova, size);
1298 static struct page **__atomic_get_pages(void *addr)
1300 struct dma_pool *pool = &atomic_pool;
1301 struct page **pages = pool->pages;
1302 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1304 return pages + offs;
1307 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1309 struct vm_struct *area;
1311 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1312 return __atomic_get_pages(cpu_addr);
1314 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1317 area = find_vm_area(cpu_addr);
1318 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1323 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1329 addr = __alloc_from_pool(size, &page);
1333 *handle = __iommu_create_mapping(dev, &page, size);
1334 if (*handle == DMA_ERROR_CODE)
1340 __free_from_pool(addr, size);
1344 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1345 dma_addr_t handle, size_t size)
1347 __iommu_remove_mapping(dev, handle, size);
1348 __free_from_pool(cpu_addr, size);
1351 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1352 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1354 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1355 struct page **pages;
1358 *handle = DMA_ERROR_CODE;
1359 size = PAGE_ALIGN(size);
1361 if (gfp & GFP_ATOMIC)
1362 return __iommu_alloc_atomic(dev, size, handle);
1365 * Following is a work-around (a.k.a. hack) to prevent pages
1366 * with __GFP_COMP being passed to split_page() which cannot
1367 * handle them. The real problem is that this flag probably
1368 * should be 0 on ARM as it is not supported on this
1369 * platform; see CONFIG_HUGETLBFS.
1371 gfp &= ~(__GFP_COMP);
1373 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1377 *handle = __iommu_create_mapping(dev, pages, size);
1378 if (*handle == DMA_ERROR_CODE)
1381 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1384 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1385 __builtin_return_address(0));
1392 __iommu_remove_mapping(dev, *handle, size);
1394 __iommu_free_buffer(dev, pages, size, attrs);
1398 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1399 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1400 struct dma_attrs *attrs)
1402 unsigned long uaddr = vma->vm_start;
1403 unsigned long usize = vma->vm_end - vma->vm_start;
1404 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1406 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1412 int ret = vm_insert_page(vma, uaddr, *pages++);
1414 pr_err("Remapping memory failed: %d\n", ret);
1419 } while (usize > 0);
1425 * free a page as defined by the above mapping.
1426 * Must not be called with IRQs disabled.
1428 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1429 dma_addr_t handle, struct dma_attrs *attrs)
1431 struct page **pages;
1432 size = PAGE_ALIGN(size);
1434 if (__in_atomic_pool(cpu_addr, size)) {
1435 __iommu_free_atomic(dev, cpu_addr, handle, size);
1439 pages = __iommu_get_pages(cpu_addr, attrs);
1441 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1445 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1446 unmap_kernel_range((unsigned long)cpu_addr, size);
1450 __iommu_remove_mapping(dev, handle, size);
1451 __iommu_free_buffer(dev, pages, size, attrs);
1454 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1455 void *cpu_addr, dma_addr_t dma_addr,
1456 size_t size, struct dma_attrs *attrs)
1458 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1459 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1464 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1468 static int __dma_direction_to_prot(enum dma_data_direction dir)
1473 case DMA_BIDIRECTIONAL:
1474 prot = IOMMU_READ | IOMMU_WRITE;
1479 case DMA_FROM_DEVICE:
1490 * Map a part of the scatter-gather list into contiguous io address space
1492 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1493 size_t size, dma_addr_t *handle,
1494 enum dma_data_direction dir, struct dma_attrs *attrs,
1497 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1498 dma_addr_t iova, iova_base;
1501 struct scatterlist *s;
1504 size = PAGE_ALIGN(size);
1505 *handle = DMA_ERROR_CODE;
1507 iova_base = iova = __alloc_iova(mapping, size);
1508 if (iova == DMA_ERROR_CODE)
1511 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1512 phys_addr_t phys = page_to_phys(sg_page(s));
1513 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1516 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1517 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1519 prot = __dma_direction_to_prot(dir);
1521 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1524 count += len >> PAGE_SHIFT;
1527 *handle = iova_base;
1531 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1532 __free_iova(mapping, iova_base, size);
1536 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1537 enum dma_data_direction dir, struct dma_attrs *attrs,
1540 struct scatterlist *s = sg, *dma = sg, *start = sg;
1542 unsigned int offset = s->offset;
1543 unsigned int size = s->offset + s->length;
1544 unsigned int max = dma_get_max_seg_size(dev);
1546 for (i = 1; i < nents; i++) {
1549 s->dma_address = DMA_ERROR_CODE;
1552 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1553 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1554 dir, attrs, is_coherent) < 0)
1557 dma->dma_address += offset;
1558 dma->dma_length = size - offset;
1560 size = offset = s->offset;
1567 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1571 dma->dma_address += offset;
1572 dma->dma_length = size - offset;
1577 for_each_sg(sg, s, count, i)
1578 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1583 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1584 * @dev: valid struct device pointer
1585 * @sg: list of buffers
1586 * @nents: number of buffers to map
1587 * @dir: DMA transfer direction
1589 * Map a set of i/o coherent buffers described by scatterlist in streaming
1590 * mode for DMA. The scatter gather list elements are merged together (if
1591 * possible) and tagged with the appropriate dma address and length. They are
1592 * obtained via sg_dma_{address,length}.
1594 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1595 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1597 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1601 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1602 * @dev: valid struct device pointer
1603 * @sg: list of buffers
1604 * @nents: number of buffers to map
1605 * @dir: DMA transfer direction
1607 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1608 * The scatter gather list elements are merged together (if possible) and
1609 * tagged with the appropriate dma address and length. They are obtained via
1610 * sg_dma_{address,length}.
1612 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1613 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1615 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1618 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1619 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1622 struct scatterlist *s;
1625 for_each_sg(sg, s, nents, i) {
1627 __iommu_remove_mapping(dev, sg_dma_address(s),
1630 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1631 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1637 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1638 * @dev: valid struct device pointer
1639 * @sg: list of buffers
1640 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1641 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1643 * Unmap a set of streaming mode DMA translations. Again, CPU access
1644 * rules concerning calls here are the same as for dma_unmap_single().
1646 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1647 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1649 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1653 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1654 * @dev: valid struct device pointer
1655 * @sg: list of buffers
1656 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1657 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1659 * Unmap a set of streaming mode DMA translations. Again, CPU access
1660 * rules concerning calls here are the same as for dma_unmap_single().
1662 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1663 enum dma_data_direction dir, struct dma_attrs *attrs)
1665 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1669 * arm_iommu_sync_sg_for_cpu
1670 * @dev: valid struct device pointer
1671 * @sg: list of buffers
1672 * @nents: number of buffers to map (returned from dma_map_sg)
1673 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1675 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1676 int nents, enum dma_data_direction dir)
1678 struct scatterlist *s;
1681 for_each_sg(sg, s, nents, i)
1682 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1687 * arm_iommu_sync_sg_for_device
1688 * @dev: valid struct device pointer
1689 * @sg: list of buffers
1690 * @nents: number of buffers to map (returned from dma_map_sg)
1691 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1693 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1694 int nents, enum dma_data_direction dir)
1696 struct scatterlist *s;
1699 for_each_sg(sg, s, nents, i)
1700 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1705 * arm_coherent_iommu_map_page
1706 * @dev: valid struct device pointer
1707 * @page: page that buffer resides in
1708 * @offset: offset into page for start of buffer
1709 * @size: size of buffer to map
1710 * @dir: DMA transfer direction
1712 * Coherent IOMMU aware version of arm_dma_map_page()
1714 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1715 unsigned long offset, size_t size, enum dma_data_direction dir,
1716 struct dma_attrs *attrs)
1718 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1719 dma_addr_t dma_addr;
1720 int ret, prot, len = PAGE_ALIGN(size + offset);
1722 dma_addr = __alloc_iova(mapping, len);
1723 if (dma_addr == DMA_ERROR_CODE)
1726 prot = __dma_direction_to_prot(dir);
1728 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1732 return dma_addr + offset;
1734 __free_iova(mapping, dma_addr, len);
1735 return DMA_ERROR_CODE;
1739 * arm_iommu_map_page
1740 * @dev: valid struct device pointer
1741 * @page: page that buffer resides in
1742 * @offset: offset into page for start of buffer
1743 * @size: size of buffer to map
1744 * @dir: DMA transfer direction
1746 * IOMMU aware version of arm_dma_map_page()
1748 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1749 unsigned long offset, size_t size, enum dma_data_direction dir,
1750 struct dma_attrs *attrs)
1752 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1753 __dma_page_cpu_to_dev(page, offset, size, dir);
1755 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1759 * arm_coherent_iommu_unmap_page
1760 * @dev: valid struct device pointer
1761 * @handle: DMA address of buffer
1762 * @size: size of buffer (same as passed to dma_map_page)
1763 * @dir: DMA transfer direction (same as passed to dma_map_page)
1765 * Coherent IOMMU aware version of arm_dma_unmap_page()
1767 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1768 size_t size, enum dma_data_direction dir,
1769 struct dma_attrs *attrs)
1771 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1772 dma_addr_t iova = handle & PAGE_MASK;
1773 int offset = handle & ~PAGE_MASK;
1774 int len = PAGE_ALIGN(size + offset);
1779 iommu_unmap(mapping->domain, iova, len);
1780 __free_iova(mapping, iova, len);
1784 * arm_iommu_unmap_page
1785 * @dev: valid struct device pointer
1786 * @handle: DMA address of buffer
1787 * @size: size of buffer (same as passed to dma_map_page)
1788 * @dir: DMA transfer direction (same as passed to dma_map_page)
1790 * IOMMU aware version of arm_dma_unmap_page()
1792 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1793 size_t size, enum dma_data_direction dir,
1794 struct dma_attrs *attrs)
1796 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1797 dma_addr_t iova = handle & PAGE_MASK;
1798 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1799 int offset = handle & ~PAGE_MASK;
1800 int len = PAGE_ALIGN(size + offset);
1805 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1806 __dma_page_dev_to_cpu(page, offset, size, dir);
1808 iommu_unmap(mapping->domain, iova, len);
1809 __free_iova(mapping, iova, len);
1812 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1813 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1815 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1816 dma_addr_t iova = handle & PAGE_MASK;
1817 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1818 unsigned int offset = handle & ~PAGE_MASK;
1823 __dma_page_dev_to_cpu(page, offset, size, dir);
1826 static void arm_iommu_sync_single_for_device(struct device *dev,
1827 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1829 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1830 dma_addr_t iova = handle & PAGE_MASK;
1831 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1832 unsigned int offset = handle & ~PAGE_MASK;
1837 __dma_page_cpu_to_dev(page, offset, size, dir);
1840 struct dma_map_ops iommu_ops = {
1841 .alloc = arm_iommu_alloc_attrs,
1842 .free = arm_iommu_free_attrs,
1843 .mmap = arm_iommu_mmap_attrs,
1844 .get_sgtable = arm_iommu_get_sgtable,
1846 .map_page = arm_iommu_map_page,
1847 .unmap_page = arm_iommu_unmap_page,
1848 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1849 .sync_single_for_device = arm_iommu_sync_single_for_device,
1851 .map_sg = arm_iommu_map_sg,
1852 .unmap_sg = arm_iommu_unmap_sg,
1853 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1854 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1856 .set_dma_mask = arm_dma_set_mask,
1859 struct dma_map_ops iommu_coherent_ops = {
1860 .alloc = arm_iommu_alloc_attrs,
1861 .free = arm_iommu_free_attrs,
1862 .mmap = arm_iommu_mmap_attrs,
1863 .get_sgtable = arm_iommu_get_sgtable,
1865 .map_page = arm_coherent_iommu_map_page,
1866 .unmap_page = arm_coherent_iommu_unmap_page,
1868 .map_sg = arm_coherent_iommu_map_sg,
1869 .unmap_sg = arm_coherent_iommu_unmap_sg,
1871 .set_dma_mask = arm_dma_set_mask,
1875 * arm_iommu_create_mapping
1876 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1877 * @base: start address of the valid IO address space
1878 * @size: size of the valid IO address space
1879 * @order: accuracy of the IO addresses allocations
1881 * Creates a mapping structure which holds information about used/unused
1882 * IO address ranges, which is required to perform memory allocation and
1883 * mapping with IOMMU aware functions.
1885 * The client device need to be attached to the mapping with
1886 * arm_iommu_attach_device function.
1888 struct dma_iommu_mapping *
1889 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1892 unsigned int count = size >> (PAGE_SHIFT + order);
1893 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1894 struct dma_iommu_mapping *mapping;
1898 return ERR_PTR(-EINVAL);
1900 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1904 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1905 if (!mapping->bitmap)
1908 mapping->base = base;
1909 mapping->bits = BITS_PER_BYTE * bitmap_size;
1910 mapping->order = order;
1911 spin_lock_init(&mapping->lock);
1913 mapping->domain = iommu_domain_alloc(bus);
1914 if (!mapping->domain)
1917 kref_init(&mapping->kref);
1920 kfree(mapping->bitmap);
1924 return ERR_PTR(err);
1926 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1928 static void release_iommu_mapping(struct kref *kref)
1930 struct dma_iommu_mapping *mapping =
1931 container_of(kref, struct dma_iommu_mapping, kref);
1933 iommu_domain_free(mapping->domain);
1934 kfree(mapping->bitmap);
1938 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1941 kref_put(&mapping->kref, release_iommu_mapping);
1943 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
1946 * arm_iommu_attach_device
1947 * @dev: valid struct device pointer
1948 * @mapping: io address space mapping structure (returned from
1949 * arm_iommu_create_mapping)
1951 * Attaches specified io address space mapping to the provided device,
1952 * this replaces the dma operations (dma_map_ops pointer) with the
1953 * IOMMU aware version. More than one client might be attached to
1954 * the same io address space mapping.
1956 int arm_iommu_attach_device(struct device *dev,
1957 struct dma_iommu_mapping *mapping)
1961 err = iommu_attach_device(mapping->domain, dev);
1965 kref_get(&mapping->kref);
1966 dev->archdata.mapping = mapping;
1967 set_dma_ops(dev, &iommu_ops);
1969 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
1972 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
1975 * arm_iommu_detach_device
1976 * @dev: valid struct device pointer
1978 * Detaches the provided device from a previously attached map.
1979 * This voids the dma operations (dma_map_ops pointer)
1981 void arm_iommu_detach_device(struct device *dev)
1983 struct dma_iommu_mapping *mapping;
1985 mapping = to_dma_iommu_mapping(dev);
1987 dev_warn(dev, "Not attached\n");
1991 iommu_detach_device(mapping->domain, dev);
1992 kref_put(&mapping->kref, release_iommu_mapping);
1993 dev->archdata.mapping = NULL;
1994 set_dma_ops(dev, NULL);
1996 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
1998 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);