2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/genalloc.h>
16 #include <linux/gfp.h>
17 #include <linux/errno.h>
18 #include <linux/list.h>
19 #include <linux/init.h>
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-contiguous.h>
23 #include <linux/highmem.h>
24 #include <linux/memblock.h>
25 #include <linux/slab.h>
26 #include <linux/iommu.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sizes.h>
30 #include <linux/cma.h>
32 #include <asm/memory.h>
33 #include <asm/highmem.h>
34 #include <asm/cacheflush.h>
35 #include <asm/tlbflush.h>
36 #include <asm/mach/arch.h>
37 #include <asm/dma-iommu.h>
38 #include <asm/mach/map.h>
39 #include <asm/system_info.h>
40 #include <asm/dma-contiguous.h>
45 struct arm_dma_alloc_args {
55 struct arm_dma_free_args {
66 struct arm_dma_allocator {
67 void *(*alloc)(struct arm_dma_alloc_args *args,
68 struct page **ret_page);
69 void (*free)(struct arm_dma_free_args *args);
72 struct arm_dma_buffer {
73 struct list_head list;
75 struct arm_dma_allocator *allocator;
78 static LIST_HEAD(arm_dma_bufs);
79 static DEFINE_SPINLOCK(arm_dma_bufs_lock);
81 static struct arm_dma_buffer *arm_dma_buffer_find(void *virt)
83 struct arm_dma_buffer *buf, *found = NULL;
86 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
87 list_for_each_entry(buf, &arm_dma_bufs, list) {
88 if (buf->virt == virt) {
94 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
99 * The DMA API is built upon the notion of "buffer ownership". A buffer
100 * is either exclusively owned by the CPU (and therefore may be accessed
101 * by it) or exclusively owned by the DMA device. These helper functions
102 * represent the transitions between these two ownership states.
104 * Note, however, that on later ARMs, this notion does not work due to
105 * speculative prefetches. We model our approach on the assumption that
106 * the CPU does do speculative prefetches, which means we clean caches
107 * before transfers and delay cache invalidation until transfer completion.
110 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
111 size_t, enum dma_data_direction);
112 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
113 size_t, enum dma_data_direction);
116 * arm_dma_map_page - map a portion of a page for streaming DMA
117 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
118 * @page: page that buffer resides in
119 * @offset: offset into page for start of buffer
120 * @size: size of buffer to map
121 * @dir: DMA transfer direction
123 * Ensure that any data held in the cache is appropriately discarded
126 * The device owns this memory once this call has completed. The CPU
127 * can regain ownership by calling dma_unmap_page().
129 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
130 unsigned long offset, size_t size, enum dma_data_direction dir,
131 struct dma_attrs *attrs)
133 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
134 __dma_page_cpu_to_dev(page, offset, size, dir);
135 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
138 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
139 unsigned long offset, size_t size, enum dma_data_direction dir,
140 struct dma_attrs *attrs)
142 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
146 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
147 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
148 * @handle: DMA address of buffer
149 * @size: size of buffer (same as passed to dma_map_page)
150 * @dir: DMA transfer direction (same as passed to dma_map_page)
152 * Unmap a page streaming mode DMA translation. The handle and size
153 * must match what was provided in the previous dma_map_page() call.
154 * All other usages are undefined.
156 * After this call, reads by the CPU to the buffer are guaranteed to see
157 * whatever the device wrote there.
159 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
160 size_t size, enum dma_data_direction dir,
161 struct dma_attrs *attrs)
163 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
164 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
165 handle & ~PAGE_MASK, size, dir);
168 static void arm_dma_sync_single_for_cpu(struct device *dev,
169 dma_addr_t handle, size_t size, enum dma_data_direction dir)
171 unsigned int offset = handle & (PAGE_SIZE - 1);
172 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
173 __dma_page_dev_to_cpu(page, offset, size, dir);
176 static void arm_dma_sync_single_for_device(struct device *dev,
177 dma_addr_t handle, size_t size, enum dma_data_direction dir)
179 unsigned int offset = handle & (PAGE_SIZE - 1);
180 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
181 __dma_page_cpu_to_dev(page, offset, size, dir);
184 struct dma_map_ops arm_dma_ops = {
185 .alloc = arm_dma_alloc,
186 .free = arm_dma_free,
187 .mmap = arm_dma_mmap,
188 .get_sgtable = arm_dma_get_sgtable,
189 .map_page = arm_dma_map_page,
190 .unmap_page = arm_dma_unmap_page,
191 .map_sg = arm_dma_map_sg,
192 .unmap_sg = arm_dma_unmap_sg,
193 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
194 .sync_single_for_device = arm_dma_sync_single_for_device,
195 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
196 .sync_sg_for_device = arm_dma_sync_sg_for_device,
198 EXPORT_SYMBOL(arm_dma_ops);
200 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
201 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
202 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
203 dma_addr_t handle, struct dma_attrs *attrs);
204 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
205 void *cpu_addr, dma_addr_t dma_addr, size_t size,
206 struct dma_attrs *attrs);
208 struct dma_map_ops arm_coherent_dma_ops = {
209 .alloc = arm_coherent_dma_alloc,
210 .free = arm_coherent_dma_free,
211 .mmap = arm_coherent_dma_mmap,
212 .get_sgtable = arm_dma_get_sgtable,
213 .map_page = arm_coherent_dma_map_page,
214 .map_sg = arm_dma_map_sg,
216 EXPORT_SYMBOL(arm_coherent_dma_ops);
218 static int __dma_supported(struct device *dev, u64 mask, bool warn)
220 unsigned long max_dma_pfn;
223 * If the mask allows for more memory than we can address,
224 * and we actually have that much memory, then we must
225 * indicate that DMA to this device is not supported.
227 if (sizeof(mask) != sizeof(dma_addr_t) &&
228 mask > (dma_addr_t)~0 &&
229 dma_to_pfn(dev, ~0) < max_pfn - 1) {
231 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
233 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
238 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
241 * Translate the device's DMA mask to a PFN limit. This
242 * PFN number includes the page which we can DMA to.
244 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
246 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
248 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
256 static u64 get_coherent_dma_mask(struct device *dev)
258 u64 mask = (u64)DMA_BIT_MASK(32);
261 mask = dev->coherent_dma_mask;
264 * Sanity check the DMA mask - it must be non-zero, and
265 * must be able to be satisfied by a DMA allocation.
268 dev_warn(dev, "coherent DMA mask is unset\n");
272 if (!__dma_supported(dev, mask, true))
279 static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag)
282 * Ensure that the allocated pages are zeroed, and that any data
283 * lurking in the kernel direct-mapped region is invalidated.
285 if (PageHighMem(page)) {
286 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
287 phys_addr_t end = base + size;
289 void *ptr = kmap_atomic(page);
290 memset(ptr, 0, PAGE_SIZE);
291 if (coherent_flag != COHERENT)
292 dmac_flush_range(ptr, ptr + PAGE_SIZE);
297 if (coherent_flag != COHERENT)
298 outer_flush_range(base, end);
300 void *ptr = page_address(page);
301 memset(ptr, 0, size);
302 if (coherent_flag != COHERENT) {
303 dmac_flush_range(ptr, ptr + size);
304 outer_flush_range(__pa(ptr), __pa(ptr) + size);
310 * Allocate a DMA buffer for 'dev' of size 'size' using the
311 * specified gfp mask. Note that 'size' must be page aligned.
313 static struct page *__dma_alloc_buffer(struct device *dev, size_t size,
314 gfp_t gfp, int coherent_flag)
316 unsigned long order = get_order(size);
317 struct page *page, *p, *e;
319 page = alloc_pages(gfp, order);
324 * Now split the huge page and free the excess pages
326 split_page(page, order);
327 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
330 __dma_clear_buffer(page, size, coherent_flag);
336 * Free a DMA buffer. 'size' must be page aligned.
338 static void __dma_free_buffer(struct page *page, size_t size)
340 struct page *e = page + (size >> PAGE_SHIFT);
350 static void *__alloc_from_contiguous(struct device *dev, size_t size,
351 pgprot_t prot, struct page **ret_page,
352 const void *caller, bool want_vaddr,
355 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
356 pgprot_t prot, struct page **ret_page,
357 const void *caller, bool want_vaddr);
360 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
364 * DMA allocation can be mapped to user space, so lets
365 * set VM_USERMAP flags too.
367 return dma_common_contiguous_remap(page, size,
368 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
372 static void __dma_free_remap(void *cpu_addr, size_t size)
374 dma_common_free_remap(cpu_addr, size,
375 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
378 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
379 static struct gen_pool *atomic_pool;
381 static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
383 static int __init early_coherent_pool(char *p)
385 atomic_pool_size = memparse(p, &p);
388 early_param("coherent_pool", early_coherent_pool);
390 void __init init_dma_coherent_pool_size(unsigned long size)
393 * Catch any attempt to set the pool size too late.
398 * Set architecture specific coherent pool size only if
399 * it has not been changed by kernel command line parameter.
401 if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE)
402 atomic_pool_size = size;
406 * Initialise the coherent pool for atomic allocations.
408 static int __init atomic_pool_init(void)
410 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
411 gfp_t gfp = GFP_KERNEL | GFP_DMA;
415 atomic_pool = gen_pool_create(PAGE_SHIFT, -1);
419 * The atomic pool is only used for non-coherent allocations
420 * so we must pass NORMAL for coherent_flag.
422 if (dev_get_cma_area(NULL))
423 ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot,
424 &page, atomic_pool_init, true, NORMAL);
426 ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot,
427 &page, atomic_pool_init, true);
431 ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr,
433 atomic_pool_size, -1);
435 goto destroy_genpool;
437 gen_pool_set_algo(atomic_pool,
438 gen_pool_first_fit_order_align,
440 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n",
441 atomic_pool_size / 1024);
446 gen_pool_destroy(atomic_pool);
449 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n",
450 atomic_pool_size / 1024);
454 * CMA is activated by core_initcall, so we must be called after it.
456 postcore_initcall(atomic_pool_init);
458 struct dma_contig_early_reserve {
463 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
465 static int dma_mmu_remap_num __initdata;
467 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
469 dma_mmu_remap[dma_mmu_remap_num].base = base;
470 dma_mmu_remap[dma_mmu_remap_num].size = size;
474 void __init dma_contiguous_remap(void)
477 for (i = 0; i < dma_mmu_remap_num; i++) {
478 phys_addr_t start = dma_mmu_remap[i].base;
479 phys_addr_t end = start + dma_mmu_remap[i].size;
483 if (end > arm_lowmem_limit)
484 end = arm_lowmem_limit;
488 map.pfn = __phys_to_pfn(start);
489 map.virtual = __phys_to_virt(start);
490 map.length = end - start;
491 map.type = MT_MEMORY_DMA_READY;
494 * Clear previous low-memory mapping to ensure that the
495 * TLB does not see any conflicting entries, then flush
496 * the TLB of the old entries before creating new mappings.
498 * This ensures that any speculatively loaded TLB entries
499 * (even though they may be rare) can not cause any problems,
500 * and ensures that this code is architecturally compliant.
502 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
504 pmd_clear(pmd_off_k(addr));
506 flush_tlb_kernel_range(__phys_to_virt(start),
507 __phys_to_virt(end));
509 iotable_init(&map, 1);
513 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
516 struct page *page = virt_to_page(addr);
517 pgprot_t prot = *(pgprot_t *)data;
519 set_pte_ext(pte, mk_pte(page, prot), 0);
523 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
525 unsigned long start = (unsigned long) page_address(page);
526 unsigned end = start + size;
528 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
529 flush_tlb_kernel_range(start, end);
532 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
533 pgprot_t prot, struct page **ret_page,
534 const void *caller, bool want_vaddr)
539 * __alloc_remap_buffer is only called when the device is
542 page = __dma_alloc_buffer(dev, size, gfp, NORMAL);
548 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
550 __dma_free_buffer(page, size);
559 static void *__alloc_from_pool(size_t size, struct page **ret_page)
565 WARN(1, "coherent pool not initialised!\n");
569 val = gen_pool_alloc(atomic_pool, size);
571 phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val);
573 *ret_page = phys_to_page(phys);
580 static bool __in_atomic_pool(void *start, size_t size)
582 return addr_in_gen_pool(atomic_pool, (unsigned long)start, size);
585 static int __free_from_pool(void *start, size_t size)
587 if (!__in_atomic_pool(start, size))
590 gen_pool_free(atomic_pool, (unsigned long)start, size);
595 static void *__alloc_from_contiguous(struct device *dev, size_t size,
596 pgprot_t prot, struct page **ret_page,
597 const void *caller, bool want_vaddr,
600 unsigned long order = get_order(size);
601 size_t count = size >> PAGE_SHIFT;
605 page = dma_alloc_from_contiguous(dev, count, order);
609 __dma_clear_buffer(page, size, coherent_flag);
614 if (PageHighMem(page)) {
615 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
617 dma_release_from_contiguous(dev, page, count);
621 __dma_remap(page, size, prot);
622 ptr = page_address(page);
630 static void __free_from_contiguous(struct device *dev, struct page *page,
631 void *cpu_addr, size_t size, bool want_vaddr)
634 if (PageHighMem(page))
635 __dma_free_remap(cpu_addr, size);
637 __dma_remap(page, size, PAGE_KERNEL);
639 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
642 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
644 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
645 pgprot_writecombine(prot) :
646 pgprot_dmacoherent(prot);
652 #else /* !CONFIG_MMU */
656 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
657 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL
658 #define __alloc_from_pool(size, ret_page) NULL
659 #define __alloc_from_contiguous(dev, size, prot, ret, c, wv, coherent_flag) NULL
660 #define __free_from_pool(cpu_addr, size) do { } while (0)
661 #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0)
662 #define __dma_free_remap(cpu_addr, size) do { } while (0)
664 #endif /* CONFIG_MMU */
666 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
667 struct page **ret_page)
670 /* __alloc_simple_buffer is only called when the device is coherent */
671 page = __dma_alloc_buffer(dev, size, gfp, COHERENT);
676 return page_address(page);
679 static void *simple_allocator_alloc(struct arm_dma_alloc_args *args,
680 struct page **ret_page)
682 return __alloc_simple_buffer(args->dev, args->size, args->gfp,
686 static void simple_allocator_free(struct arm_dma_free_args *args)
688 __dma_free_buffer(args->page, args->size);
691 static struct arm_dma_allocator simple_allocator = {
692 .alloc = simple_allocator_alloc,
693 .free = simple_allocator_free,
696 static void *cma_allocator_alloc(struct arm_dma_alloc_args *args,
697 struct page **ret_page)
699 return __alloc_from_contiguous(args->dev, args->size, args->prot,
700 ret_page, args->caller,
701 args->want_vaddr, args->coherent_flag);
704 static void cma_allocator_free(struct arm_dma_free_args *args)
706 __free_from_contiguous(args->dev, args->page, args->cpu_addr,
707 args->size, args->want_vaddr);
710 static struct arm_dma_allocator cma_allocator = {
711 .alloc = cma_allocator_alloc,
712 .free = cma_allocator_free,
715 static void *pool_allocator_alloc(struct arm_dma_alloc_args *args,
716 struct page **ret_page)
718 return __alloc_from_pool(args->size, ret_page);
721 static void pool_allocator_free(struct arm_dma_free_args *args)
723 __free_from_pool(args->cpu_addr, args->size);
726 static struct arm_dma_allocator pool_allocator = {
727 .alloc = pool_allocator_alloc,
728 .free = pool_allocator_free,
731 static void *remap_allocator_alloc(struct arm_dma_alloc_args *args,
732 struct page **ret_page)
734 return __alloc_remap_buffer(args->dev, args->size, args->gfp,
735 args->prot, ret_page, args->caller,
739 static void remap_allocator_free(struct arm_dma_free_args *args)
741 if (args->want_vaddr)
742 __dma_free_remap(args->cpu_addr, args->size);
744 __dma_free_buffer(args->page, args->size);
747 static struct arm_dma_allocator remap_allocator = {
748 .alloc = remap_allocator_alloc,
749 .free = remap_allocator_free,
752 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
753 gfp_t gfp, pgprot_t prot, bool is_coherent,
754 struct dma_attrs *attrs, const void *caller)
756 u64 mask = get_coherent_dma_mask(dev);
757 struct page *page = NULL;
759 bool allowblock, cma;
760 struct arm_dma_buffer *buf;
761 struct arm_dma_alloc_args args = {
763 .size = PAGE_ALIGN(size),
767 .want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs),
768 .coherent_flag = is_coherent ? COHERENT : NORMAL,
771 #ifdef CONFIG_DMA_API_DEBUG
772 u64 limit = (mask + 1) & ~mask;
773 if (limit && size >= limit) {
774 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
783 buf = kzalloc(sizeof(*buf),
784 gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM));
788 if (mask < 0xffffffffULL)
792 * Following is a work-around (a.k.a. hack) to prevent pages
793 * with __GFP_COMP being passed to split_page() which cannot
794 * handle them. The real problem is that this flag probably
795 * should be 0 on ARM as it is not supported on this
796 * platform; see CONFIG_HUGETLBFS.
798 gfp &= ~(__GFP_COMP);
801 *handle = DMA_ERROR_CODE;
802 allowblock = gfpflags_allow_blocking(gfp);
803 cma = allowblock ? dev_get_cma_area(dev) : false;
806 buf->allocator = &cma_allocator;
807 else if (nommu() || is_coherent)
808 buf->allocator = &simple_allocator;
810 buf->allocator = &remap_allocator;
812 buf->allocator = &pool_allocator;
814 addr = buf->allocator->alloc(&args, &page);
819 *handle = pfn_to_dma(dev, page_to_pfn(page));
820 buf->virt = args.want_vaddr ? addr : page;
822 spin_lock_irqsave(&arm_dma_bufs_lock, flags);
823 list_add(&buf->list, &arm_dma_bufs);
824 spin_unlock_irqrestore(&arm_dma_bufs_lock, flags);
829 return args.want_vaddr ? addr : page;
833 * Allocate DMA-coherent memory space and return both the kernel remapped
834 * virtual and bus address for that space.
836 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
837 gfp_t gfp, struct dma_attrs *attrs)
839 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
841 return __dma_alloc(dev, size, handle, gfp, prot, false,
842 attrs, __builtin_return_address(0));
845 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
846 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
848 return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true,
849 attrs, __builtin_return_address(0));
852 static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
853 void *cpu_addr, dma_addr_t dma_addr, size_t size,
854 struct dma_attrs *attrs)
858 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
859 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
860 unsigned long pfn = dma_to_pfn(dev, dma_addr);
861 unsigned long off = vma->vm_pgoff;
863 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
866 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
867 ret = remap_pfn_range(vma, vma->vm_start,
869 vma->vm_end - vma->vm_start,
872 #endif /* CONFIG_MMU */
878 * Create userspace mapping for the DMA-coherent memory.
880 static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma,
881 void *cpu_addr, dma_addr_t dma_addr, size_t size,
882 struct dma_attrs *attrs)
884 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
887 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
888 void *cpu_addr, dma_addr_t dma_addr, size_t size,
889 struct dma_attrs *attrs)
892 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
893 #endif /* CONFIG_MMU */
894 return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
898 * Free a buffer as defined by the above mapping.
900 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
901 dma_addr_t handle, struct dma_attrs *attrs,
904 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
905 struct arm_dma_buffer *buf;
906 struct arm_dma_free_args args = {
908 .size = PAGE_ALIGN(size),
909 .cpu_addr = cpu_addr,
911 .want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs),
914 buf = arm_dma_buffer_find(cpu_addr);
915 if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr))
918 buf->allocator->free(&args);
922 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
923 dma_addr_t handle, struct dma_attrs *attrs)
925 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
928 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
929 dma_addr_t handle, struct dma_attrs *attrs)
931 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
934 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
935 void *cpu_addr, dma_addr_t handle, size_t size,
936 struct dma_attrs *attrs)
938 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
941 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
945 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
949 static void dma_cache_maint_page(struct page *page, unsigned long offset,
950 size_t size, enum dma_data_direction dir,
951 void (*op)(const void *, size_t, int))
956 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
960 * A single sg entry may refer to multiple physically contiguous
961 * pages. But we still need to process highmem pages individually.
962 * If highmem is not configured then the bulk of this loop gets
969 page = pfn_to_page(pfn);
971 if (PageHighMem(page)) {
972 if (len + offset > PAGE_SIZE)
973 len = PAGE_SIZE - offset;
975 if (cache_is_vipt_nonaliasing()) {
976 vaddr = kmap_atomic(page);
977 op(vaddr + offset, len, dir);
978 kunmap_atomic(vaddr);
980 vaddr = kmap_high_get(page);
982 op(vaddr + offset, len, dir);
987 vaddr = page_address(page) + offset;
997 * Make an area consistent for devices.
998 * Note: Drivers should NOT use this function directly, as it will break
999 * platforms with CONFIG_DMABOUNCE.
1000 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
1002 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
1003 size_t size, enum dma_data_direction dir)
1007 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
1009 paddr = page_to_phys(page) + off;
1010 if (dir == DMA_FROM_DEVICE) {
1011 outer_inv_range(paddr, paddr + size);
1013 outer_clean_range(paddr, paddr + size);
1015 /* FIXME: non-speculating: flush on bidirectional mappings? */
1018 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
1019 size_t size, enum dma_data_direction dir)
1021 phys_addr_t paddr = page_to_phys(page) + off;
1023 /* FIXME: non-speculating: not required */
1024 /* in any case, don't bother invalidating if DMA to device */
1025 if (dir != DMA_TO_DEVICE) {
1026 outer_inv_range(paddr, paddr + size);
1028 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
1032 * Mark the D-cache clean for these pages to avoid extra flushing.
1034 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
1038 pfn = page_to_pfn(page) + off / PAGE_SIZE;
1042 left -= PAGE_SIZE - off;
1044 while (left >= PAGE_SIZE) {
1045 page = pfn_to_page(pfn++);
1046 set_bit(PG_dcache_clean, &page->flags);
1053 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
1054 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1055 * @sg: list of buffers
1056 * @nents: number of buffers to map
1057 * @dir: DMA transfer direction
1059 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1060 * This is the scatter-gather version of the dma_map_single interface.
1061 * Here the scatter gather list elements are each tagged with the
1062 * appropriate dma address and length. They are obtained via
1063 * sg_dma_{address,length}.
1065 * Device ownership issues as mentioned for dma_map_single are the same
1068 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1069 enum dma_data_direction dir, struct dma_attrs *attrs)
1071 struct dma_map_ops *ops = get_dma_ops(dev);
1072 struct scatterlist *s;
1075 for_each_sg(sg, s, nents, i) {
1076 #ifdef CONFIG_NEED_SG_DMA_LENGTH
1077 s->dma_length = s->length;
1079 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
1080 s->length, dir, attrs);
1081 if (dma_mapping_error(dev, s->dma_address))
1087 for_each_sg(sg, s, i, j)
1088 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1093 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1094 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1095 * @sg: list of buffers
1096 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1097 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1099 * Unmap a set of streaming mode DMA translations. Again, CPU access
1100 * rules concerning calls here are the same as for dma_unmap_single().
1102 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1103 enum dma_data_direction dir, struct dma_attrs *attrs)
1105 struct dma_map_ops *ops = get_dma_ops(dev);
1106 struct scatterlist *s;
1110 for_each_sg(sg, s, nents, i)
1111 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
1115 * arm_dma_sync_sg_for_cpu
1116 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1117 * @sg: list of buffers
1118 * @nents: number of buffers to map (returned from dma_map_sg)
1119 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1121 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1122 int nents, enum dma_data_direction dir)
1124 struct dma_map_ops *ops = get_dma_ops(dev);
1125 struct scatterlist *s;
1128 for_each_sg(sg, s, nents, i)
1129 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1134 * arm_dma_sync_sg_for_device
1135 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1136 * @sg: list of buffers
1137 * @nents: number of buffers to map (returned from dma_map_sg)
1138 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1140 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1141 int nents, enum dma_data_direction dir)
1143 struct dma_map_ops *ops = get_dma_ops(dev);
1144 struct scatterlist *s;
1147 for_each_sg(sg, s, nents, i)
1148 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1153 * Return whether the given device DMA address mask can be supported
1154 * properly. For example, if your device can only drive the low 24-bits
1155 * during bus mastering, then you would pass 0x00ffffff as the mask
1158 int dma_supported(struct device *dev, u64 mask)
1160 return __dma_supported(dev, mask, false);
1162 EXPORT_SYMBOL(dma_supported);
1164 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1166 static int __init dma_debug_do_init(void)
1168 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1171 fs_initcall(dma_debug_do_init);
1173 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1177 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1179 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1182 unsigned int order = get_order(size);
1183 unsigned int align = 0;
1184 unsigned int count, start;
1185 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1186 unsigned long flags;
1190 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1191 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1193 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1194 align = (1 << order) - 1;
1196 spin_lock_irqsave(&mapping->lock, flags);
1197 for (i = 0; i < mapping->nr_bitmaps; i++) {
1198 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1199 mapping->bits, 0, count, align);
1201 if (start > mapping->bits)
1204 bitmap_set(mapping->bitmaps[i], start, count);
1209 * No unused range found. Try to extend the existing mapping
1210 * and perform a second attempt to reserve an IO virtual
1211 * address range of size bytes.
1213 if (i == mapping->nr_bitmaps) {
1214 if (extend_iommu_mapping(mapping)) {
1215 spin_unlock_irqrestore(&mapping->lock, flags);
1216 return DMA_ERROR_CODE;
1219 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1220 mapping->bits, 0, count, align);
1222 if (start > mapping->bits) {
1223 spin_unlock_irqrestore(&mapping->lock, flags);
1224 return DMA_ERROR_CODE;
1227 bitmap_set(mapping->bitmaps[i], start, count);
1229 spin_unlock_irqrestore(&mapping->lock, flags);
1231 iova = mapping->base + (mapping_size * i);
1232 iova += start << PAGE_SHIFT;
1237 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1238 dma_addr_t addr, size_t size)
1240 unsigned int start, count;
1241 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1242 unsigned long flags;
1243 dma_addr_t bitmap_base;
1249 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1250 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1252 bitmap_base = mapping->base + mapping_size * bitmap_index;
1254 start = (addr - bitmap_base) >> PAGE_SHIFT;
1256 if (addr + size > bitmap_base + mapping_size) {
1258 * The address range to be freed reaches into the iova
1259 * range of the next bitmap. This should not happen as
1260 * we don't allow this in __alloc_iova (at the
1265 count = size >> PAGE_SHIFT;
1267 spin_lock_irqsave(&mapping->lock, flags);
1268 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1269 spin_unlock_irqrestore(&mapping->lock, flags);
1272 /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */
1273 static const int iommu_order_array[] = { 9, 8, 4, 0 };
1275 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1276 gfp_t gfp, struct dma_attrs *attrs,
1279 struct page **pages;
1280 int count = size >> PAGE_SHIFT;
1281 int array_size = count * sizeof(struct page *);
1285 if (array_size <= PAGE_SIZE)
1286 pages = kzalloc(array_size, GFP_KERNEL);
1288 pages = vzalloc(array_size);
1292 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1294 unsigned long order = get_order(size);
1297 page = dma_alloc_from_contiguous(dev, count, order);
1301 __dma_clear_buffer(page, size, coherent_flag);
1303 for (i = 0; i < count; i++)
1304 pages[i] = page + i;
1309 /* Go straight to 4K chunks if caller says it's OK. */
1310 if (dma_get_attr(DMA_ATTR_ALLOC_SINGLE_PAGES, attrs))
1311 order_idx = ARRAY_SIZE(iommu_order_array) - 1;
1314 * IOMMU can map any pages, so himem can also be used here
1316 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1321 order = iommu_order_array[order_idx];
1323 /* Drop down when we get small */
1324 if (__fls(count) < order) {
1330 /* See if it's easy to allocate a high-order chunk */
1331 pages[i] = alloc_pages(gfp | __GFP_NORETRY, order);
1333 /* Go down a notch at first sign of pressure */
1339 pages[i] = alloc_pages(gfp, 0);
1345 split_page(pages[i], order);
1348 pages[i + j] = pages[i] + j;
1351 __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag);
1353 count -= 1 << order;
1360 __free_pages(pages[i], 0);
1365 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1366 size_t size, struct dma_attrs *attrs)
1368 int count = size >> PAGE_SHIFT;
1371 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1372 dma_release_from_contiguous(dev, pages[0], count);
1374 for (i = 0; i < count; i++)
1376 __free_pages(pages[i], 0);
1384 * Create a CPU mapping for a specified pages
1387 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1390 return dma_common_pages_remap(pages, size,
1391 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1395 * Create a mapping in device IO address space for specified pages
1398 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1400 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1401 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1402 dma_addr_t dma_addr, iova;
1405 dma_addr = __alloc_iova(mapping, size);
1406 if (dma_addr == DMA_ERROR_CODE)
1410 for (i = 0; i < count; ) {
1413 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1414 phys_addr_t phys = page_to_phys(pages[i]);
1415 unsigned int len, j;
1417 for (j = i + 1; j < count; j++, next_pfn++)
1418 if (page_to_pfn(pages[j]) != next_pfn)
1421 len = (j - i) << PAGE_SHIFT;
1422 ret = iommu_map(mapping->domain, iova, phys, len,
1423 IOMMU_READ|IOMMU_WRITE);
1431 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1432 __free_iova(mapping, dma_addr, size);
1433 return DMA_ERROR_CODE;
1436 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1438 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1441 * add optional in-page offset from iova to size and align
1442 * result to page size
1444 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1447 iommu_unmap(mapping->domain, iova, size);
1448 __free_iova(mapping, iova, size);
1452 static struct page **__atomic_get_pages(void *addr)
1457 phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr);
1458 page = phys_to_page(phys);
1460 return (struct page **)page;
1463 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1465 struct vm_struct *area;
1467 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1468 return __atomic_get_pages(cpu_addr);
1470 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1473 area = find_vm_area(cpu_addr);
1474 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1479 static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp,
1480 dma_addr_t *handle, int coherent_flag)
1485 if (coherent_flag == COHERENT)
1486 addr = __alloc_simple_buffer(dev, size, gfp, &page);
1488 addr = __alloc_from_pool(size, &page);
1492 *handle = __iommu_create_mapping(dev, &page, size);
1493 if (*handle == DMA_ERROR_CODE)
1499 __free_from_pool(addr, size);
1503 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1504 dma_addr_t handle, size_t size, int coherent_flag)
1506 __iommu_remove_mapping(dev, handle, size);
1507 if (coherent_flag == COHERENT)
1508 __dma_free_buffer(virt_to_page(cpu_addr), size);
1510 __free_from_pool(cpu_addr, size);
1513 static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size,
1514 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs,
1517 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1518 struct page **pages;
1521 *handle = DMA_ERROR_CODE;
1522 size = PAGE_ALIGN(size);
1524 if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp))
1525 return __iommu_alloc_simple(dev, size, gfp, handle,
1529 * Following is a work-around (a.k.a. hack) to prevent pages
1530 * with __GFP_COMP being passed to split_page() which cannot
1531 * handle them. The real problem is that this flag probably
1532 * should be 0 on ARM as it is not supported on this
1533 * platform; see CONFIG_HUGETLBFS.
1535 gfp &= ~(__GFP_COMP);
1537 pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag);
1541 *handle = __iommu_create_mapping(dev, pages, size);
1542 if (*handle == DMA_ERROR_CODE)
1545 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1548 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1549 __builtin_return_address(0));
1556 __iommu_remove_mapping(dev, *handle, size);
1558 __iommu_free_buffer(dev, pages, size, attrs);
1562 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1563 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1565 return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, NORMAL);
1568 static void *arm_coherent_iommu_alloc_attrs(struct device *dev, size_t size,
1569 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1571 return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, COHERENT);
1574 static int __arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1575 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1576 struct dma_attrs *attrs)
1578 unsigned long uaddr = vma->vm_start;
1579 unsigned long usize = vma->vm_end - vma->vm_start;
1580 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1581 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
1582 unsigned long off = vma->vm_pgoff;
1587 if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off)
1593 int ret = vm_insert_page(vma, uaddr, *pages++);
1595 pr_err("Remapping memory failed: %d\n", ret);
1600 } while (usize > 0);
1604 static int arm_iommu_mmap_attrs(struct device *dev,
1605 struct vm_area_struct *vma, void *cpu_addr,
1606 dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs)
1608 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1610 return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs);
1613 static int arm_coherent_iommu_mmap_attrs(struct device *dev,
1614 struct vm_area_struct *vma, void *cpu_addr,
1615 dma_addr_t dma_addr, size_t size, struct dma_attrs *attrs)
1617 return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs);
1621 * free a page as defined by the above mapping.
1622 * Must not be called with IRQs disabled.
1624 void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1625 dma_addr_t handle, struct dma_attrs *attrs, int coherent_flag)
1627 struct page **pages;
1628 size = PAGE_ALIGN(size);
1630 if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) {
1631 __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag);
1635 pages = __iommu_get_pages(cpu_addr, attrs);
1637 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1641 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1642 dma_common_free_remap(cpu_addr, size,
1643 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1646 __iommu_remove_mapping(dev, handle, size);
1647 __iommu_free_buffer(dev, pages, size, attrs);
1650 void arm_iommu_free_attrs(struct device *dev, size_t size,
1651 void *cpu_addr, dma_addr_t handle, struct dma_attrs *attrs)
1653 __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL);
1656 void arm_coherent_iommu_free_attrs(struct device *dev, size_t size,
1657 void *cpu_addr, dma_addr_t handle, struct dma_attrs *attrs)
1659 __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT);
1662 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1663 void *cpu_addr, dma_addr_t dma_addr,
1664 size_t size, struct dma_attrs *attrs)
1666 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1667 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1672 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1676 static int __dma_direction_to_prot(enum dma_data_direction dir)
1681 case DMA_BIDIRECTIONAL:
1682 prot = IOMMU_READ | IOMMU_WRITE;
1687 case DMA_FROM_DEVICE:
1698 * Map a part of the scatter-gather list into contiguous io address space
1700 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1701 size_t size, dma_addr_t *handle,
1702 enum dma_data_direction dir, struct dma_attrs *attrs,
1705 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1706 dma_addr_t iova, iova_base;
1709 struct scatterlist *s;
1712 size = PAGE_ALIGN(size);
1713 *handle = DMA_ERROR_CODE;
1715 iova_base = iova = __alloc_iova(mapping, size);
1716 if (iova == DMA_ERROR_CODE)
1719 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1720 phys_addr_t phys = page_to_phys(sg_page(s));
1721 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1724 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1725 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1727 prot = __dma_direction_to_prot(dir);
1729 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1732 count += len >> PAGE_SHIFT;
1735 *handle = iova_base;
1739 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1740 __free_iova(mapping, iova_base, size);
1744 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1745 enum dma_data_direction dir, struct dma_attrs *attrs,
1748 struct scatterlist *s = sg, *dma = sg, *start = sg;
1750 unsigned int offset = s->offset;
1751 unsigned int size = s->offset + s->length;
1752 unsigned int max = dma_get_max_seg_size(dev);
1754 for (i = 1; i < nents; i++) {
1757 s->dma_address = DMA_ERROR_CODE;
1760 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1761 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1762 dir, attrs, is_coherent) < 0)
1765 dma->dma_address += offset;
1766 dma->dma_length = size - offset;
1768 size = offset = s->offset;
1775 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1779 dma->dma_address += offset;
1780 dma->dma_length = size - offset;
1785 for_each_sg(sg, s, count, i)
1786 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1791 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1792 * @dev: valid struct device pointer
1793 * @sg: list of buffers
1794 * @nents: number of buffers to map
1795 * @dir: DMA transfer direction
1797 * Map a set of i/o coherent buffers described by scatterlist in streaming
1798 * mode for DMA. The scatter gather list elements are merged together (if
1799 * possible) and tagged with the appropriate dma address and length. They are
1800 * obtained via sg_dma_{address,length}.
1802 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1803 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1805 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1809 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1810 * @dev: valid struct device pointer
1811 * @sg: list of buffers
1812 * @nents: number of buffers to map
1813 * @dir: DMA transfer direction
1815 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1816 * The scatter gather list elements are merged together (if possible) and
1817 * tagged with the appropriate dma address and length. They are obtained via
1818 * sg_dma_{address,length}.
1820 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1821 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1823 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1826 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1827 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1830 struct scatterlist *s;
1833 for_each_sg(sg, s, nents, i) {
1835 __iommu_remove_mapping(dev, sg_dma_address(s),
1838 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1839 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1845 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1846 * @dev: valid struct device pointer
1847 * @sg: list of buffers
1848 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1849 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1851 * Unmap a set of streaming mode DMA translations. Again, CPU access
1852 * rules concerning calls here are the same as for dma_unmap_single().
1854 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1855 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1857 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1861 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1862 * @dev: valid struct device pointer
1863 * @sg: list of buffers
1864 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1865 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1867 * Unmap a set of streaming mode DMA translations. Again, CPU access
1868 * rules concerning calls here are the same as for dma_unmap_single().
1870 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1871 enum dma_data_direction dir, struct dma_attrs *attrs)
1873 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1877 * arm_iommu_sync_sg_for_cpu
1878 * @dev: valid struct device pointer
1879 * @sg: list of buffers
1880 * @nents: number of buffers to map (returned from dma_map_sg)
1881 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1883 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1884 int nents, enum dma_data_direction dir)
1886 struct scatterlist *s;
1889 for_each_sg(sg, s, nents, i)
1890 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1895 * arm_iommu_sync_sg_for_device
1896 * @dev: valid struct device pointer
1897 * @sg: list of buffers
1898 * @nents: number of buffers to map (returned from dma_map_sg)
1899 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1901 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1902 int nents, enum dma_data_direction dir)
1904 struct scatterlist *s;
1907 for_each_sg(sg, s, nents, i)
1908 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1913 * arm_coherent_iommu_map_page
1914 * @dev: valid struct device pointer
1915 * @page: page that buffer resides in
1916 * @offset: offset into page for start of buffer
1917 * @size: size of buffer to map
1918 * @dir: DMA transfer direction
1920 * Coherent IOMMU aware version of arm_dma_map_page()
1922 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1923 unsigned long offset, size_t size, enum dma_data_direction dir,
1924 struct dma_attrs *attrs)
1926 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1927 dma_addr_t dma_addr;
1928 int ret, prot, len = PAGE_ALIGN(size + offset);
1930 dma_addr = __alloc_iova(mapping, len);
1931 if (dma_addr == DMA_ERROR_CODE)
1934 prot = __dma_direction_to_prot(dir);
1936 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1940 return dma_addr + offset;
1942 __free_iova(mapping, dma_addr, len);
1943 return DMA_ERROR_CODE;
1947 * arm_iommu_map_page
1948 * @dev: valid struct device pointer
1949 * @page: page that buffer resides in
1950 * @offset: offset into page for start of buffer
1951 * @size: size of buffer to map
1952 * @dir: DMA transfer direction
1954 * IOMMU aware version of arm_dma_map_page()
1956 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1957 unsigned long offset, size_t size, enum dma_data_direction dir,
1958 struct dma_attrs *attrs)
1960 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1961 __dma_page_cpu_to_dev(page, offset, size, dir);
1963 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1967 * arm_coherent_iommu_unmap_page
1968 * @dev: valid struct device pointer
1969 * @handle: DMA address of buffer
1970 * @size: size of buffer (same as passed to dma_map_page)
1971 * @dir: DMA transfer direction (same as passed to dma_map_page)
1973 * Coherent IOMMU aware version of arm_dma_unmap_page()
1975 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1976 size_t size, enum dma_data_direction dir,
1977 struct dma_attrs *attrs)
1979 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
1980 dma_addr_t iova = handle & PAGE_MASK;
1981 int offset = handle & ~PAGE_MASK;
1982 int len = PAGE_ALIGN(size + offset);
1987 iommu_unmap(mapping->domain, iova, len);
1988 __free_iova(mapping, iova, len);
1992 * arm_iommu_unmap_page
1993 * @dev: valid struct device pointer
1994 * @handle: DMA address of buffer
1995 * @size: size of buffer (same as passed to dma_map_page)
1996 * @dir: DMA transfer direction (same as passed to dma_map_page)
1998 * IOMMU aware version of arm_dma_unmap_page()
2000 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
2001 size_t size, enum dma_data_direction dir,
2002 struct dma_attrs *attrs)
2004 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2005 dma_addr_t iova = handle & PAGE_MASK;
2006 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2007 int offset = handle & ~PAGE_MASK;
2008 int len = PAGE_ALIGN(size + offset);
2013 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
2014 __dma_page_dev_to_cpu(page, offset, size, dir);
2016 iommu_unmap(mapping->domain, iova, len);
2017 __free_iova(mapping, iova, len);
2020 static void arm_iommu_sync_single_for_cpu(struct device *dev,
2021 dma_addr_t handle, size_t size, enum dma_data_direction dir)
2023 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2024 dma_addr_t iova = handle & PAGE_MASK;
2025 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2026 unsigned int offset = handle & ~PAGE_MASK;
2031 __dma_page_dev_to_cpu(page, offset, size, dir);
2034 static void arm_iommu_sync_single_for_device(struct device *dev,
2035 dma_addr_t handle, size_t size, enum dma_data_direction dir)
2037 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2038 dma_addr_t iova = handle & PAGE_MASK;
2039 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
2040 unsigned int offset = handle & ~PAGE_MASK;
2045 __dma_page_cpu_to_dev(page, offset, size, dir);
2048 struct dma_map_ops iommu_ops = {
2049 .alloc = arm_iommu_alloc_attrs,
2050 .free = arm_iommu_free_attrs,
2051 .mmap = arm_iommu_mmap_attrs,
2052 .get_sgtable = arm_iommu_get_sgtable,
2054 .map_page = arm_iommu_map_page,
2055 .unmap_page = arm_iommu_unmap_page,
2056 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
2057 .sync_single_for_device = arm_iommu_sync_single_for_device,
2059 .map_sg = arm_iommu_map_sg,
2060 .unmap_sg = arm_iommu_unmap_sg,
2061 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
2062 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
2065 struct dma_map_ops iommu_coherent_ops = {
2066 .alloc = arm_coherent_iommu_alloc_attrs,
2067 .free = arm_coherent_iommu_free_attrs,
2068 .mmap = arm_coherent_iommu_mmap_attrs,
2069 .get_sgtable = arm_iommu_get_sgtable,
2071 .map_page = arm_coherent_iommu_map_page,
2072 .unmap_page = arm_coherent_iommu_unmap_page,
2074 .map_sg = arm_coherent_iommu_map_sg,
2075 .unmap_sg = arm_coherent_iommu_unmap_sg,
2079 * arm_iommu_create_mapping
2080 * @bus: pointer to the bus holding the client device (for IOMMU calls)
2081 * @base: start address of the valid IO address space
2082 * @size: maximum size of the valid IO address space
2084 * Creates a mapping structure which holds information about used/unused
2085 * IO address ranges, which is required to perform memory allocation and
2086 * mapping with IOMMU aware functions.
2088 * The client device need to be attached to the mapping with
2089 * arm_iommu_attach_device function.
2091 struct dma_iommu_mapping *
2092 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size)
2094 unsigned int bits = size >> PAGE_SHIFT;
2095 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
2096 struct dma_iommu_mapping *mapping;
2100 /* currently only 32-bit DMA address space is supported */
2101 if (size > DMA_BIT_MASK(32) + 1)
2102 return ERR_PTR(-ERANGE);
2105 return ERR_PTR(-EINVAL);
2107 if (bitmap_size > PAGE_SIZE) {
2108 extensions = bitmap_size / PAGE_SIZE;
2109 bitmap_size = PAGE_SIZE;
2112 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
2116 mapping->bitmap_size = bitmap_size;
2117 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
2119 if (!mapping->bitmaps)
2122 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
2123 if (!mapping->bitmaps[0])
2126 mapping->nr_bitmaps = 1;
2127 mapping->extensions = extensions;
2128 mapping->base = base;
2129 mapping->bits = BITS_PER_BYTE * bitmap_size;
2131 spin_lock_init(&mapping->lock);
2133 mapping->domain = iommu_domain_alloc(bus);
2134 if (!mapping->domain)
2137 kref_init(&mapping->kref);
2140 kfree(mapping->bitmaps[0]);
2142 kfree(mapping->bitmaps);
2146 return ERR_PTR(err);
2148 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
2150 static void release_iommu_mapping(struct kref *kref)
2153 struct dma_iommu_mapping *mapping =
2154 container_of(kref, struct dma_iommu_mapping, kref);
2156 iommu_domain_free(mapping->domain);
2157 for (i = 0; i < mapping->nr_bitmaps; i++)
2158 kfree(mapping->bitmaps[i]);
2159 kfree(mapping->bitmaps);
2163 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
2167 if (mapping->nr_bitmaps >= mapping->extensions)
2170 next_bitmap = mapping->nr_bitmaps;
2171 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
2173 if (!mapping->bitmaps[next_bitmap])
2176 mapping->nr_bitmaps++;
2181 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
2184 kref_put(&mapping->kref, release_iommu_mapping);
2186 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
2188 static int __arm_iommu_attach_device(struct device *dev,
2189 struct dma_iommu_mapping *mapping)
2193 err = iommu_attach_device(mapping->domain, dev);
2197 kref_get(&mapping->kref);
2198 to_dma_iommu_mapping(dev) = mapping;
2200 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2205 * arm_iommu_attach_device
2206 * @dev: valid struct device pointer
2207 * @mapping: io address space mapping structure (returned from
2208 * arm_iommu_create_mapping)
2210 * Attaches specified io address space mapping to the provided device.
2211 * This replaces the dma operations (dma_map_ops pointer) with the
2212 * IOMMU aware version.
2214 * More than one client might be attached to the same io address space
2217 int arm_iommu_attach_device(struct device *dev,
2218 struct dma_iommu_mapping *mapping)
2222 err = __arm_iommu_attach_device(dev, mapping);
2226 set_dma_ops(dev, &iommu_ops);
2229 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2231 static void __arm_iommu_detach_device(struct device *dev)
2233 struct dma_iommu_mapping *mapping;
2235 mapping = to_dma_iommu_mapping(dev);
2237 dev_warn(dev, "Not attached\n");
2241 iommu_detach_device(mapping->domain, dev);
2242 kref_put(&mapping->kref, release_iommu_mapping);
2243 to_dma_iommu_mapping(dev) = NULL;
2245 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2249 * arm_iommu_detach_device
2250 * @dev: valid struct device pointer
2252 * Detaches the provided device from a previously attached map.
2253 * This voids the dma operations (dma_map_ops pointer)
2255 void arm_iommu_detach_device(struct device *dev)
2257 __arm_iommu_detach_device(dev);
2258 set_dma_ops(dev, NULL);
2260 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
2262 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
2264 return coherent ? &iommu_coherent_ops : &iommu_ops;
2267 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2268 const struct iommu_ops *iommu)
2270 struct dma_iommu_mapping *mapping;
2275 mapping = arm_iommu_create_mapping(dev->bus, dma_base, size);
2276 if (IS_ERR(mapping)) {
2277 pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n",
2278 size, dev_name(dev));
2282 if (__arm_iommu_attach_device(dev, mapping)) {
2283 pr_warn("Failed to attached device %s to IOMMU_mapping\n",
2285 arm_iommu_release_mapping(mapping);
2292 static void arm_teardown_iommu_dma_ops(struct device *dev)
2294 struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev);
2299 __arm_iommu_detach_device(dev);
2300 arm_iommu_release_mapping(mapping);
2305 static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size,
2306 const struct iommu_ops *iommu)
2311 static void arm_teardown_iommu_dma_ops(struct device *dev) { }
2313 #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops
2315 #endif /* CONFIG_ARM_DMA_USE_IOMMU */
2317 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent)
2319 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops;
2322 void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
2323 const struct iommu_ops *iommu, bool coherent)
2325 struct dma_map_ops *dma_ops;
2327 dev->archdata.dma_coherent = coherent;
2328 if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu))
2329 dma_ops = arm_get_iommu_dma_map_ops(coherent);
2331 dma_ops = arm_get_dma_map_ops(coherent);
2333 set_dma_ops(dev, dma_ops);
2336 void arch_teardown_dma_ops(struct device *dev)
2338 arm_teardown_iommu_dma_ops(dev);