1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
7 * This is the "shell" of the ARMv6 processor support.
9 #include <linux/linkage.h>
10 #include <linux/init.h>
11 #include <asm/assembler.h>
12 #include <asm/errno.h>
13 #include <asm/unwind.h>
15 #include "proc-macros.S"
18 #define CACHE_LINE_SIZE 32
19 #define D_CACHE_LINE_SIZE 32
20 #define BTB_FLUSH_SIZE 8
25 * v6_flush_icache_all()
27 * Flush the whole I-cache.
29 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
30 * This erratum is present in 1136, 1156 and 1176. It does not affect the
37 ENTRY(v6_flush_icache_all)
39 #ifdef CONFIG_ARM_ERRATA_411920
41 cpsid ifa @ disable interrupts
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 msr cpsr_cx, r1 @ restore interrupts
47 .rept 11 @ ARM Ltd recommends at least
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
54 ENDPROC(v6_flush_icache_all)
57 * v6_flush_cache_all()
59 * Flush the entire cache.
63 ENTRY(v6_flush_kern_cache_all)
66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
67 #ifndef CONFIG_ARM_ERRATA_411920
68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
78 * v6_flush_cache_all()
80 * Flush all TLB entries in a particular address space
82 * - mm - mm_struct describing address space
84 ENTRY(v6_flush_user_cache_all)
88 * v6_flush_cache_range(start, end, flags)
90 * Flush a range of TLB entries in the specified address space.
92 * - start - start address (may not be aligned)
93 * - end - end address (exclusive, may not be aligned)
94 * - flags - vm_area_struct flags describing address space
97 * - we have a VIPT cache.
99 ENTRY(v6_flush_user_cache_range)
103 * v6_coherent_kern_range(start,end)
105 * Ensure that the I and D caches are coherent within specified
106 * region. This is typically used when code has been written to
107 * a memory region, and will be executed.
109 * - start - virtual start address of region
110 * - end - virtual end address of region
112 * It is assumed that:
113 * - the Icache does not read data from the write buffer
115 ENTRY(v6_coherent_kern_range)
119 * v6_coherent_user_range(start,end)
121 * Ensure that the I and D caches are coherent within specified
122 * region. This is typically used when code has been written to
123 * a memory region, and will be executed.
125 * - start - virtual start address of region
126 * - end - virtual end address of region
128 * It is assumed that:
129 * - the Icache does not read data from the write buffer
131 ENTRY(v6_coherent_user_range)
134 bic r0, r0, #CACHE_LINE_SIZE - 1
136 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
137 add r0, r0, #CACHE_LINE_SIZE
143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
144 #ifndef CONFIG_ARM_ERRATA_411920
145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
147 b v6_flush_icache_all
150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
155 * Fault handling for the cache operation above. If the virtual address in r0
156 * isn't mapped, fail with -EFAULT.
162 ENDPROC(v6_coherent_user_range)
163 ENDPROC(v6_coherent_kern_range)
166 * v6_flush_kern_dcache_area(void *addr, size_t size)
168 * Ensure that the data held in the page kaddr is written back
169 * to the page in question.
171 * - addr - kernel address
172 * - size - region size
174 ENTRY(v6_flush_kern_dcache_area)
176 bic r0, r0, #D_CACHE_LINE_SIZE - 1
179 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
181 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
183 add r0, r0, #D_CACHE_LINE_SIZE
188 mcr p15, 0, r0, c7, c10, 4
194 * v6_dma_inv_range(start,end)
196 * Invalidate the data cache within the specified region; we will
197 * be performing a DMA operation in this region and we want to
198 * purge old data in the cache.
200 * - start - virtual start address of region
201 * - end - virtual end address of region
204 #ifdef CONFIG_DMA_CACHE_RWFO
205 ldrb r2, [r0] @ read for ownership
206 strb r2, [r0] @ write for ownership
208 tst r0, #D_CACHE_LINE_SIZE - 1
209 bic r0, r0, #D_CACHE_LINE_SIZE - 1
211 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
213 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
215 tst r1, #D_CACHE_LINE_SIZE - 1
216 #ifdef CONFIG_DMA_CACHE_RWFO
217 ldrbne r2, [r1, #-1] @ read for ownership
218 strbne r2, [r1, #-1] @ write for ownership
220 bic r1, r1, #D_CACHE_LINE_SIZE - 1
222 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
224 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
228 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
230 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
232 add r0, r0, #D_CACHE_LINE_SIZE
234 #ifdef CONFIG_DMA_CACHE_RWFO
235 ldrlo r2, [r0] @ read for ownership
236 strlo r2, [r0] @ write for ownership
240 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
244 * v6_dma_clean_range(start,end)
245 * - start - virtual start address of region
246 * - end - virtual end address of region
249 bic r0, r0, #D_CACHE_LINE_SIZE - 1
251 #ifdef CONFIG_DMA_CACHE_RWFO
252 ldr r2, [r0] @ read for ownership
255 mcr p15, 0, r0, c7, c10, 1 @ clean D line
257 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
259 add r0, r0, #D_CACHE_LINE_SIZE
263 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
267 * v6_dma_flush_range(start,end)
268 * - start - virtual start address of region
269 * - end - virtual end address of region
271 ENTRY(v6_dma_flush_range)
272 #ifdef CONFIG_DMA_CACHE_RWFO
273 ldrb r2, [r0] @ read for ownership
274 strb r2, [r0] @ write for ownership
276 bic r0, r0, #D_CACHE_LINE_SIZE - 1
279 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
281 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
283 add r0, r0, #D_CACHE_LINE_SIZE
285 #ifdef CONFIG_DMA_CACHE_RWFO
286 ldrblo r2, [r0] @ read for ownership
287 strblo r2, [r0] @ write for ownership
291 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
295 * dma_map_area(start, size, dir)
296 * - start - kernel virtual start address
297 * - size - size of region
298 * - dir - DMA direction
300 ENTRY(v6_dma_map_area)
302 teq r2, #DMA_FROM_DEVICE
304 #ifndef CONFIG_DMA_CACHE_RWFO
307 teq r2, #DMA_TO_DEVICE
308 beq v6_dma_clean_range
311 ENDPROC(v6_dma_map_area)
314 * dma_unmap_area(start, size, dir)
315 * - start - kernel virtual start address
316 * - size - size of region
317 * - dir - DMA direction
319 ENTRY(v6_dma_unmap_area)
320 #ifndef CONFIG_DMA_CACHE_RWFO
322 teq r2, #DMA_TO_DEVICE
326 ENDPROC(v6_dma_unmap_area)
328 .globl v6_flush_kern_cache_louis
329 .equ v6_flush_kern_cache_louis, v6_flush_kern_cache_all
333 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
334 define_cache_functions v6