1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/cache-v6.S
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
7 * This is the "shell" of the ARMv6 processor support.
9 #include <linux/linkage.h>
10 #include <linux/init.h>
11 #include <asm/assembler.h>
12 #include <asm/errno.h>
13 #include <asm/unwind.h>
15 #include "proc-macros.S"
18 #define CACHE_LINE_SIZE 32
19 #define D_CACHE_LINE_SIZE 32
20 #define BTB_FLUSH_SIZE 8
23 * v6_flush_icache_all()
25 * Flush the whole I-cache.
27 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
28 * This erratum is present in 1136, 1156 and 1176. It does not affect the
35 ENTRY(v6_flush_icache_all)
37 #ifdef CONFIG_ARM_ERRATA_411920
39 cpsid ifa @ disable interrupts
40 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
41 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 msr cpsr_cx, r1 @ restore interrupts
45 .rept 11 @ ARM Ltd recommends at least
49 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
52 ENDPROC(v6_flush_icache_all)
55 * v6_flush_cache_all()
57 * Flush the entire cache.
61 ENTRY(v6_flush_kern_cache_all)
64 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
65 #ifndef CONFIG_ARM_ERRATA_411920
66 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
76 * v6_flush_cache_all()
78 * Flush all TLB entries in a particular address space
80 * - mm - mm_struct describing address space
82 ENTRY(v6_flush_user_cache_all)
86 * v6_flush_cache_range(start, end, flags)
88 * Flush a range of TLB entries in the specified address space.
90 * - start - start address (may not be aligned)
91 * - end - end address (exclusive, may not be aligned)
92 * - flags - vm_area_struct flags describing address space
95 * - we have a VIPT cache.
97 ENTRY(v6_flush_user_cache_range)
101 * v6_coherent_kern_range(start,end)
103 * Ensure that the I and D caches are coherent within specified
104 * region. This is typically used when code has been written to
105 * a memory region, and will be executed.
107 * - start - virtual start address of region
108 * - end - virtual end address of region
110 * It is assumed that:
111 * - the Icache does not read data from the write buffer
113 ENTRY(v6_coherent_kern_range)
117 * v6_coherent_user_range(start,end)
119 * Ensure that the I and D caches are coherent within specified
120 * region. This is typically used when code has been written to
121 * a memory region, and will be executed.
123 * - start - virtual start address of region
124 * - end - virtual end address of region
126 * It is assumed that:
127 * - the Icache does not read data from the write buffer
129 ENTRY(v6_coherent_user_range)
132 bic r0, r0, #CACHE_LINE_SIZE - 1
134 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
135 add r0, r0, #CACHE_LINE_SIZE
141 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
142 #ifndef CONFIG_ARM_ERRATA_411920
143 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
145 b v6_flush_icache_all
148 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
153 * Fault handling for the cache operation above. If the virtual address in r0
154 * isn't mapped, fail with -EFAULT.
160 ENDPROC(v6_coherent_user_range)
161 ENDPROC(v6_coherent_kern_range)
164 * v6_flush_kern_dcache_area(void *addr, size_t size)
166 * Ensure that the data held in the page kaddr is written back
167 * to the page in question.
169 * - addr - kernel address
170 * - size - region size
172 ENTRY(v6_flush_kern_dcache_area)
174 bic r0, r0, #D_CACHE_LINE_SIZE - 1
177 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
179 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
181 add r0, r0, #D_CACHE_LINE_SIZE
186 mcr p15, 0, r0, c7, c10, 4
192 * v6_dma_inv_range(start,end)
194 * Invalidate the data cache within the specified region; we will
195 * be performing a DMA operation in this region and we want to
196 * purge old data in the cache.
198 * - start - virtual start address of region
199 * - end - virtual end address of region
201 ENTRY(v6_dma_inv_range)
202 #ifdef CONFIG_DMA_CACHE_RWFO
203 ldrb r2, [r0] @ read for ownership
204 strb r2, [r0] @ write for ownership
206 tst r0, #D_CACHE_LINE_SIZE - 1
207 bic r0, r0, #D_CACHE_LINE_SIZE - 1
209 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
211 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
213 tst r1, #D_CACHE_LINE_SIZE - 1
214 #ifdef CONFIG_DMA_CACHE_RWFO
215 ldrbne r2, [r1, #-1] @ read for ownership
216 strbne r2, [r1, #-1] @ write for ownership
218 bic r1, r1, #D_CACHE_LINE_SIZE - 1
220 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
226 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
228 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
230 add r0, r0, #D_CACHE_LINE_SIZE
232 #ifdef CONFIG_DMA_CACHE_RWFO
233 ldrlo r2, [r0] @ read for ownership
234 strlo r2, [r0] @ write for ownership
238 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
242 * v6_dma_clean_range(start,end)
243 * - start - virtual start address of region
244 * - end - virtual end address of region
246 ENTRY(v6_dma_clean_range)
247 bic r0, r0, #D_CACHE_LINE_SIZE - 1
249 #ifdef CONFIG_DMA_CACHE_RWFO
250 ldr r2, [r0] @ read for ownership
253 mcr p15, 0, r0, c7, c10, 1 @ clean D line
255 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
257 add r0, r0, #D_CACHE_LINE_SIZE
261 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
265 * v6_dma_flush_range(start,end)
266 * - start - virtual start address of region
267 * - end - virtual end address of region
269 ENTRY(v6_dma_flush_range)
270 #ifdef CONFIG_DMA_CACHE_RWFO
271 ldrb r2, [r0] @ read for ownership
272 strb r2, [r0] @ write for ownership
274 bic r0, r0, #D_CACHE_LINE_SIZE - 1
277 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
279 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
281 add r0, r0, #D_CACHE_LINE_SIZE
283 #ifdef CONFIG_DMA_CACHE_RWFO
284 ldrblo r2, [r0] @ read for ownership
285 strblo r2, [r0] @ write for ownership
289 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
293 * dma_map_area(start, size, dir)
294 * - start - kernel virtual start address
295 * - size - size of region
296 * - dir - DMA direction
298 ENTRY(v6_dma_map_area)
300 teq r2, #DMA_FROM_DEVICE
302 #ifndef CONFIG_DMA_CACHE_RWFO
305 teq r2, #DMA_TO_DEVICE
306 beq v6_dma_clean_range
309 ENDPROC(v6_dma_map_area)
312 * dma_unmap_area(start, size, dir)
313 * - start - kernel virtual start address
314 * - size - size of region
315 * - dir - DMA direction
317 ENTRY(v6_dma_unmap_area)
318 #ifndef CONFIG_DMA_CACHE_RWFO
320 teq r2, #DMA_TO_DEVICE
324 ENDPROC(v6_dma_unmap_area)
326 .globl v6_flush_kern_cache_louis
327 .equ v6_flush_kern_cache_louis, v6_flush_kern_cache_all
331 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
332 define_cache_functions v6