arch/arm/mach-zynqmp/mp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <michal.simek@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <log.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <linux/delay.h>
  14
  15 #define LOCK            0
  16 #define SPLIT           1
  17
  18 #define HALT            0
  19 #define RELEASE         1
  20
  21 #define ZYNQMP_BOOTADDR_HIGH_MASK               0xFFFFFFFF
  22 #define ZYNQMP_R5_HIVEC_ADDR                    0xFFFF0000
  23 #define ZYNQMP_R5_LOVEC_ADDR                    0x0
  24 #define ZYNQMP_RPU_CFG_CPU_HALT_MASK            0x01
  25 #define ZYNQMP_RPU_CFG_HIVEC_MASK               0x04
  26 #define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK    0x08
  27 #define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK      0x40
  28 #define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK       0x10
  29
  30 #define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK     0x04
  31 #define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK      0x01
  32 #define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK      0x02
  33 #define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK   0x1000000
  34
  35 #define ZYNQMP_TCM_START_ADDRESS                0xFFE00000
  36 #define ZYNQMP_TCM_BOTH_SIZE                    0x40000
  37
  38 #define ZYNQMP_CORE_APU0        0
  39 #define ZYNQMP_CORE_APU3        3
  40 #define ZYNQMP_CORE_RPU0        4
  41 #define ZYNQMP_CORE_RPU1        5
  42
  43 #define ZYNQMP_MAX_CORES        6
  44
  45 #define ZYNQMP_RPU0_USE_MASK BIT(1)
  46 #define ZYNQMP_RPU1_USE_MASK BIT(2)
  47
  48 int is_core_valid(unsigned int core)
  49 {
  50         if (core < ZYNQMP_MAX_CORES)
  51                 return 1;
  52
  53         return 0;
  54 }
  55
  56 int cpu_reset(u32 nr)
  57 {
  58         puts("Feature is not implemented.\n");
  59         return 0;
  60 }
  61
  62 static void set_r5_halt_mode(u32 nr, u8 halt, u8 mode)
  63 {
  64         u32 tmp;
  65
  66         if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) {
  67                 tmp = readl(&rpu_base->rpu0_cfg);
  68                 if (halt == HALT)
  69                         tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  70                 else
  71                         tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  72                 writel(tmp, &rpu_base->rpu0_cfg);
  73         }
  74
  75         if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) {
  76                 tmp = readl(&rpu_base->rpu1_cfg);
  77                 if (halt == HALT)
  78                         tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  79                 else
  80                         tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
  81                 writel(tmp, &rpu_base->rpu1_cfg);
  82         }
  83 }
  84
  85 static void set_r5_tcm_mode(u8 mode)
  86 {
  87         u32 tmp;
  88
  89         tmp = readl(&rpu_base->rpu_glbl_ctrl);
  90         if (mode == LOCK) {
  91                 tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  92                 tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  93                        ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
  94         } else {
  95                 tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  96                 tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
  97                        ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
  98         }
  99
 100         writel(tmp, &rpu_base->rpu_glbl_ctrl);
 101 }
 102
 103 static void set_r5_reset(u32 nr, u8 mode)
 104 {
 105         u32 tmp;
 106
 107         tmp = readl(&crlapb_base->rst_lpd_top);
 108         if (mode == LOCK) {
 109                 tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 110                         ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK |
 111                         ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
 112         } else {
 113                 if (nr == ZYNQMP_CORE_RPU0) {
 114                         tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK;
 115                         if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK)
 116                                 tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
 117                 } else {
 118                         tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
 119                         if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK)
 120                                 tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK;
 121                 }
 122         }
 123
 124         writel(tmp, &crlapb_base->rst_lpd_top);
 125 }
 126
 127 static void release_r5_reset(u32 nr, u8 mode)
 128 {
 129         u32 tmp;
 130
 131         tmp = readl(&crlapb_base->rst_lpd_top);
 132         if (mode == LOCK || nr == ZYNQMP_CORE_RPU0)
 133                 tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 134                          ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
 135
 136         if (mode == LOCK || nr == ZYNQMP_CORE_RPU1)
 137                 tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
 138                          ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK);
 139
 140         writel(tmp, &crlapb_base->rst_lpd_top);
 141 }
 142
 143 static void enable_clock_r5(void)
 144 {
 145         u32 tmp;
 146
 147         tmp = readl(&crlapb_base->cpu_r5_ctrl);
 148         tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
 149         writel(tmp, &crlapb_base->cpu_r5_ctrl);
 150
 151         /* Give some delay for clock
 152          * to propagate */
 153         udelay(0x500);
 154 }
 155
 156 static int check_r5_mode(void)
 157 {
 158         u32 tmp;
 159
 160         tmp = readl(&rpu_base->rpu_glbl_ctrl);
 161         if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK)
 162                 return SPLIT;
 163
 164         return LOCK;
 165 }
 166
 167 int cpu_disable(u32 nr)
 168 {
 169         if (nr <= ZYNQMP_CORE_APU3) {
 170                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 171                 val |= 1 << nr;
 172                 writel(val, &crfapb_base->rst_fpd_apu);
 173         } else {
 174                 set_r5_reset(nr, check_r5_mode());
 175         }
 176
 177         return 0;
 178 }
 179
 180 int cpu_status(u32 nr)
 181 {
 182         if (nr <= ZYNQMP_CORE_APU3) {
 183                 u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
 184                 u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
 185                                       nr * 8);
 186                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 187                 val &= 1 << nr;
 188                 printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
 189                        nr, val ? "OFF" : "ON" , addr_high, addr_low);
 190         } else {
 191                 u32 val = readl(&crlapb_base->rst_lpd_top);
 192                 val &= 1 << (nr - 4);
 193                 printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
 194         }
 195
 196         return 0;
 197 }
 198
 199 static void set_r5_start(u8 high)
 200 {
 201         u32 tmp;
 202
 203         tmp = readl(&rpu_base->rpu0_cfg);
 204         if (high)
 205                 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
 206         else
 207                 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
 208         writel(tmp, &rpu_base->rpu0_cfg);
 209
 210         tmp = readl(&rpu_base->rpu1_cfg);
 211         if (high)
 212                 tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
 213         else
 214                 tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
 215         writel(tmp, &rpu_base->rpu1_cfg);
 216 }
 217
 218 static void write_tcm_boot_trampoline(u32 boot_addr)
 219 {
 220         if (boot_addr) {
 221                 /*
 222                  * Boot trampoline is simple ASM code below.
 223                  *
 224                  *              b over;
 225                  *      label:
 226                  *      .word   0
 227                  *      over:   ldr     r0, =label
 228                  *              ldr     r1, [r0]
 229                  *              bx      r1
 230                  */
 231                 debug("Write boot trampoline for %x\n", boot_addr);
 232                 writel(0xea000000, ZYNQMP_TCM_START_ADDRESS);
 233                 writel(boot_addr, ZYNQMP_TCM_START_ADDRESS + 0x4);
 234                 writel(0xe59f0004, ZYNQMP_TCM_START_ADDRESS + 0x8);
 235                 writel(0xe5901000, ZYNQMP_TCM_START_ADDRESS + 0xc);
 236                 writel(0xe12fff11, ZYNQMP_TCM_START_ADDRESS + 0x10);
 237                 writel(0x00000004, ZYNQMP_TCM_START_ADDRESS + 0x14); // address for
 238         }
 239 }
 240
 241 void initialize_tcm(bool mode)
 242 {
 243         if (!mode) {
 244                 set_r5_tcm_mode(LOCK);
 245                 set_r5_halt_mode(ZYNQMP_CORE_RPU0, HALT, LOCK);
 246                 enable_clock_r5();
 247                 release_r5_reset(ZYNQMP_CORE_RPU0, LOCK);
 248         } else {
 249                 set_r5_tcm_mode(SPLIT);
 250                 set_r5_halt_mode(ZYNQMP_CORE_RPU1, HALT, SPLIT);
 251                 enable_clock_r5();
 252                 release_r5_reset(ZYNQMP_CORE_RPU1, SPLIT);
 253         }
 254 }
 255
 256 static void mark_r5_used(u32 nr, u8 mode)
 257 {
 258         u32 mask = 0;
 259
 260         if (mode == LOCK) {
 261                 mask = ZYNQMP_RPU0_USE_MASK | ZYNQMP_RPU1_USE_MASK;
 262         } else {
 263                 switch (nr) {
 264                 case ZYNQMP_CORE_RPU0:
 265                         mask = ZYNQMP_RPU0_USE_MASK;
 266                         break;
 267                 case ZYNQMP_CORE_RPU1:
 268                         mask = ZYNQMP_RPU1_USE_MASK;
 269                         break;
 270                 default:
 271                         return;
 272                 }
 273         }
 274         zynqmp_mmio_write((ulong)&pmu_base->gen_storage4, mask, mask);
 275 }
 276
 277 int cpu_release(u32 nr, int argc, char *const argv[])
 278 {
 279         if (nr <= ZYNQMP_CORE_APU3) {
 280                 u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
 281                 /* HIGH */
 282                 writel((u32)(boot_addr >> 32),
 283                        ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
 284                 /* LOW */
 285                 writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
 286                        ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
 287
 288                 u32 val = readl(&crfapb_base->rst_fpd_apu);
 289                 val &= ~(1 << nr);
 290                 writel(val, &crfapb_base->rst_fpd_apu);
 291         } else {
 292                 if (argc != 2) {
 293                         printf("Invalid number of arguments to release.\n");
 294                         printf("<addr> <mode>-Start addr lockstep or split\n");
 295                         return 1;
 296                 }
 297
 298                 u32 boot_addr = hextoul(argv[0], NULL);
 299                 u32 boot_addr_uniq = 0;
 300                 if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
 301                       boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
 302                         printf("Using TCM jump trampoline for address 0x%x\n",
 303                                boot_addr);
 304                         /* Save boot address for later usage */
 305                         boot_addr_uniq = boot_addr;
 306                         /*
 307                          * R5 needs to start from LOVEC at TCM
 308                          * OCM will be probably occupied by ATF
 309                          */
 310                         boot_addr = ZYNQMP_R5_LOVEC_ADDR;
 311                 }
 312
 313                 /*
 314                  * Since we don't know where the user may have loaded the image
 315                  * for an R5 we have to flush all the data cache to ensure
 316                  * the R5 sees it.
 317                  */
 318                 flush_dcache_all();
 319
 320                 if (!strncmp(argv[1], "lockstep", 8)) {
 321                         printf("R5 lockstep mode\n");
 322                         set_r5_reset(nr, LOCK);
 323                         set_r5_tcm_mode(LOCK);
 324                         set_r5_halt_mode(nr, HALT, LOCK);
 325                         set_r5_start(boot_addr);
 326                         enable_clock_r5();
 327                         release_r5_reset(nr, LOCK);
 328                         dcache_disable();
 329                         write_tcm_boot_trampoline(boot_addr_uniq);
 330                         dcache_enable();
 331                         set_r5_halt_mode(nr, RELEASE, LOCK);
 332                         mark_r5_used(nr, LOCK);
 333                 } else if (!strncmp(argv[1], "split", 5)) {
 334                         printf("R5 split mode\n");
 335                         set_r5_reset(nr, SPLIT);
 336                         set_r5_tcm_mode(SPLIT);
 337                         set_r5_halt_mode(nr, HALT, SPLIT);
 338                         set_r5_start(boot_addr);
 339                         enable_clock_r5();
 340                         release_r5_reset(nr, SPLIT);
 341                         dcache_disable();
 342                         write_tcm_boot_trampoline(boot_addr_uniq);
 343                         dcache_enable();
 344                         set_r5_halt_mode(nr, RELEASE, SPLIT);
 345                         mark_r5_used(nr, SPLIT);
 346                 } else {
 347                         printf("Unsupported mode\n");
 348                         return 1;
 349                 }
 350         }
 351
 352         return 0;
 353 }