1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@amd.com>
7 #ifndef _ASM_ARCH_SYS_PROTO_H
8 #define _ASM_ARCH_SYS_PROTO_H
10 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF
11 #define KEY_PTR_LEN 32
13 #define RSA_KEY_SIZE 512
14 #define MODULUS_LEN 512
15 #define PRIV_EXPO_LEN 512
16 #define PUB_EXPO_LEN 4
18 #define ZYNQMP_SHA3_INIT 1
19 #define ZYNQMP_SHA3_UPDATE 2
20 #define ZYNQMP_SHA3_FINAL 4
21 #define ZYNQMP_SHA3_SIZE 48
23 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1
24 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2
25 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
26 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
27 #define ZYNQMP_FPGA_BIT_NS 5
29 #define ZYNQMP_FPGA_AUTH_DDR 1
49 unsigned int zynqmp_get_silicon_version(void);
51 void initialize_tcm(bool mode);
52 void mem_map_fill(void);
53 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
54 void tcm_init(u8 mode);
57 #endif /* _ASM_ARCH_SYS_PROTO_H */