1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
7 #ifndef _ASM_ARCH_SYS_PROTO_H
8 #define _ASM_ARCH_SYS_PROTO_H
10 #define ZYNQMP_CSU_SILICON_VER_MASK 0xF
11 #define KEY_PTR_LEN 32
13 #define ZYNQMP_FPGA_BIT_AUTH_DDR 1
14 #define ZYNQMP_FPGA_BIT_AUTH_OCM 2
15 #define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
16 #define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
17 #define ZYNQMP_FPGA_BIT_NS 5
19 #define ZYNQMP_FPGA_AUTH_DDR 1
39 struct zynqmp_ipi_msg {
44 int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
45 unsigned int zynqmp_get_silicon_version(void);
47 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
48 int zynqmp_mmio_read(const u32 address, u32 *value);
50 void initialize_tcm(bool mode);
51 void mem_map_fill(void);
52 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
53 void tcm_init(u8 mode);
56 #endif /* _ASM_ARCH_SYS_PROTO_H */