1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
7 #ifndef _ASM_ARCH_HARDWARE_H
8 #define _ASM_ARCH_HARDWARE_H
11 #include <linux/bitops.h>
14 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000
15 #define ZYNQMP_TCM_SIZE 0x40000
17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
19 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
20 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
22 #define PS_MODE0 BIT(0)
23 #define PS_MODE1 BIT(1)
24 #define PS_MODE2 BIT(2)
25 #define PS_MODE3 BIT(3)
27 #define RESET_REASON_DEBUG_SYS BIT(6)
28 #define RESET_REASON_SOFT BIT(5)
29 #define RESET_REASON_SRST BIT(4)
30 #define RESET_REASON_PSONLY BIT(3)
31 #define RESET_REASON_PMU BIT(2)
32 #define RESET_REASON_INTERNAL BIT(1)
33 #define RESET_REASON_EXTERNAL BIT(0)
37 u32 cpu_r5_ctrl; /* 0x90 */
39 u32 timestamp_ref_ctrl; /* 0x128 */
41 u32 boot_mode; /* 0x200 */
43 u32 reset_reason; /* 0x220 */
45 u32 rst_lpd_top; /* 0x23C */
47 u32 boot_pin_ctrl; /* 0x250 */
51 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
53 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
54 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
55 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
57 struct iou_scntr_secure {
58 u32 counter_control_register;
60 u32 base_frequency_id_register;
63 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE)
65 /* Bootmode setting values */
66 #define BOOT_MODES_MASK 0x0000000F
67 #define QSPI_MODE_24BIT 0x00000001
68 #define QSPI_MODE_32BIT 0x00000002
69 #define SD_MODE 0x00000003 /* sd 0 */
70 #define SD_MODE1 0x00000005 /* sd 1 */
71 #define NAND_MODE 0x00000004
72 #define EMMC_MODE 0x00000006
73 #define USB_MODE 0x00000007
74 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */
75 #define JTAG_MODE 0x00000000
76 #define BOOT_MODE_USE_ALT 0x100
77 #define BOOT_MODE_ALT_SHIFT 12
78 /* SW secondary boot modes 0xa - 0xd */
79 #define SW_USBHOST_MODE 0x0000000A
80 #define SW_SATA_MODE 0x0000000B
82 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
84 struct iou_slcr_regs {
89 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
91 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
96 u32 rpu0_cfg; /* 0x100 */
98 u32 rpu1_cfg; /* 0x200 */
101 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
103 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
107 u32 rst_fpd_apu; /* 0x104 */
111 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
113 #define ZYNQMP_APU_BASEADDR 0xFD5C0000
117 u32 rvbar_addr0_l; /* 0x40 */
118 u32 rvbar_addr0_h; /* 0x44 */
122 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
124 /* Board version value */
125 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000
126 #define ZYNQMP_CSU_VERSION_SILICON 0x0
127 #define ZYNQMP_CSU_VERSION_QEMU 0x3
129 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20
131 #define ZYNQMP_SILICON_VER_MASK 0xF000
132 #define ZYNQMP_SILICON_VER_SHIFT 12
142 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR)
144 #define ZYNQMP_PMU_BASEADDR 0xFFD80000
148 u32 gen_storage6; /* 0x48 */
151 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
153 #endif /* _ASM_ARCH_HARDWARE_H */