1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
8 #include <asm/arch/hardware.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/armv8/mmu.h>
12 #include <zynqmp_firmware.h>
14 #define ZYNQ_SILICON_VER_MASK 0xF000
15 #define ZYNQ_SILICON_VER_SHIFT 12
17 DECLARE_GLOBAL_DATA_PTR;
20 * Number of filled static entries and also the first empty
21 * slot in zynqmp_mem_map.
23 #define ZYNQMP_MEM_MAP_USED 4
25 #if !defined(CONFIG_ZYNQMP_NO_DDR)
26 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
31 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
37 /* +1 is end of list which needs to be empty */
38 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
40 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
54 PTE_BLOCK_PXN | PTE_BLOCK_UXN
56 .virt = 0x400000000UL,
57 .phys = 0x400000000UL,
58 .size = 0x400000000UL,
59 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
61 PTE_BLOCK_PXN | PTE_BLOCK_UXN
63 .virt = 0x1000000000UL,
64 .phys = 0x1000000000UL,
65 .size = 0xf000000000UL,
66 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
68 PTE_BLOCK_PXN | PTE_BLOCK_UXN
72 void mem_map_fill(void)
74 int banks = ZYNQMP_MEM_MAP_USED;
76 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
77 zynqmp_mem_map[banks].virt = 0xffe00000UL;
78 zynqmp_mem_map[banks].phys = 0xffe00000UL;
79 zynqmp_mem_map[banks].size = 0x00200000UL;
80 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
81 PTE_BLOCK_INNER_SHARE;
85 #if !defined(CONFIG_ZYNQMP_NO_DDR)
86 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
87 /* Zero size means no more DDR that's this is end */
88 if (!gd->bd->bi_dram[i].size)
91 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
92 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
93 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
94 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
95 PTE_BLOCK_INNER_SHARE;
101 struct mm_region *mem_map = zynqmp_mem_map;
103 u64 get_page_table_size(void)
108 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
109 void tcm_init(u8 mode)
111 puts("WARNING: Initializing TCM overwrites TCM content\n");
112 initialize_tcm(mode);
113 memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
117 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
118 int reserve_mmu(void)
121 gd->arch.tlb_size = PGTABLE_SIZE;
122 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
128 static unsigned int zynqmp_get_silicon_version_secure(void)
132 ver = readl(&csu_base->version);
133 ver &= ZYNQMP_SILICON_VER_MASK;
134 ver >>= ZYNQMP_SILICON_VER_SHIFT;
139 unsigned int zynqmp_get_silicon_version(void)
141 if (current_el() == 3)
142 return zynqmp_get_silicon_version_secure();
144 gd->cpu_clk = get_tbclk();
146 switch (gd->cpu_clk) {
148 return ZYNQMP_CSU_VERSION_QEMU;
151 return ZYNQMP_CSU_VERSION_SILICON;
154 #define ZYNQMP_MMIO_READ 0xC2000014
155 #define ZYNQMP_MMIO_WRITE 0xC2000013
157 int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
158 u32 arg3, u32 *ret_payload)
161 * Added SIP service call Function Identifier
162 * Make sure to stay in x0 register
166 regs.regs[0] = pm_api_id;
167 regs.regs[1] = ((u64)arg1 << 32) | arg0;
168 regs.regs[2] = ((u64)arg3 << 32) | arg2;
172 if (ret_payload != NULL) {
173 ret_payload[0] = (u32)regs.regs[0];
174 ret_payload[1] = upper_32_bits(regs.regs[0]);
175 ret_payload[2] = (u32)regs.regs[1];
176 ret_payload[3] = upper_32_bits(regs.regs[1]);
177 ret_payload[4] = (u32)regs.regs[2];
183 static int zynqmp_mmio_rawwrite(const u32 address,
188 u32 value_local = value;
191 ret = zynqmp_mmio_read(address, &data);
198 writel(value_local, (ulong)address);
202 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
204 *value = readl((ulong)address);
208 int zynqmp_mmio_write(const u32 address,
212 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
213 return zynqmp_mmio_rawwrite(address, mask, value);
215 return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
221 int zynqmp_mmio_read(const u32 address, u32 *value)
223 u32 ret_payload[PAYLOAD_ARG_CNT];
229 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
230 ret = zynqmp_mmio_rawread(address, value);
232 ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
234 *value = ret_payload[1];