1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/armv8/mmu.h>
13 #include <asm/cache.h>
15 #include <zynqmp_firmware.h>
16 #include <asm/cache.h>
18 #define ZYNQ_SILICON_VER_MASK 0xF000
19 #define ZYNQ_SILICON_VER_SHIFT 12
21 DECLARE_GLOBAL_DATA_PTR;
24 * Number of filled static entries and also the first empty
25 * slot in zynqmp_mem_map.
27 #define ZYNQMP_MEM_MAP_USED 4
29 #if !defined(CONFIG_ZYNQMP_NO_DDR)
30 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS
35 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
41 /* +1 is end of list which needs to be empty */
42 #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
44 static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
49 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
51 PTE_BLOCK_PXN | PTE_BLOCK_UXN
56 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 PTE_BLOCK_PXN | PTE_BLOCK_UXN
60 .virt = 0x400000000UL,
61 .phys = 0x400000000UL,
62 .size = 0x400000000UL,
63 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 PTE_BLOCK_PXN | PTE_BLOCK_UXN
67 .virt = 0x1000000000UL,
68 .phys = 0x1000000000UL,
69 .size = 0xf000000000UL,
70 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
72 PTE_BLOCK_PXN | PTE_BLOCK_UXN
76 void mem_map_fill(void)
78 int banks = ZYNQMP_MEM_MAP_USED;
80 #if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
81 zynqmp_mem_map[banks].virt = 0xffe00000UL;
82 zynqmp_mem_map[banks].phys = 0xffe00000UL;
83 zynqmp_mem_map[banks].size = 0x00200000UL;
84 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
85 PTE_BLOCK_INNER_SHARE;
89 #if !defined(CONFIG_ZYNQMP_NO_DDR)
90 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
91 /* Zero size means no more DDR that's this is end */
92 if (!gd->bd->bi_dram[i].size)
95 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
96 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
97 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
98 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
99 PTE_BLOCK_INNER_SHARE;
105 struct mm_region *mem_map = zynqmp_mem_map;
107 u64 get_page_table_size(void)
112 #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
113 void tcm_init(u8 mode)
115 puts("WARNING: Initializing TCM overwrites TCM content\n");
116 initialize_tcm(mode);
117 memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
121 #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
122 int arm_reserve_mmu(void)
125 gd->arch.tlb_size = PGTABLE_SIZE;
126 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
132 static unsigned int zynqmp_get_silicon_version_secure(void)
136 ver = readl(&csu_base->version);
137 ver &= ZYNQMP_SILICON_VER_MASK;
138 ver >>= ZYNQMP_SILICON_VER_SHIFT;
143 unsigned int zynqmp_get_silicon_version(void)
145 if (current_el() == 3)
146 return zynqmp_get_silicon_version_secure();
148 gd->cpu_clk = get_tbclk();
150 switch (gd->cpu_clk) {
152 return ZYNQMP_CSU_VERSION_QEMU;
155 return ZYNQMP_CSU_VERSION_SILICON;
158 static int zynqmp_mmio_rawwrite(const u32 address,
163 u32 value_local = value;
166 ret = zynqmp_mmio_read(address, &data);
173 writel(value_local, (ulong)address);
177 static int zynqmp_mmio_rawread(const u32 address, u32 *value)
179 *value = readl((ulong)address);
183 int zynqmp_mmio_write(const u32 address,
187 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
188 return zynqmp_mmio_rawwrite(address, mask, value);
189 #if defined(CONFIG_ZYNQMP_FIRMWARE)
191 return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
198 int zynqmp_mmio_read(const u32 address, u32 *value)
205 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
206 ret = zynqmp_mmio_rawread(address, value);
208 #if defined(CONFIG_ZYNQMP_FIRMWARE)
210 u32 ret_payload[PAYLOAD_ARG_CNT];
212 ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
214 *value = ret_payload[1];