arch/arm/mach-zynq/timer.c

   1 /*
   2  * This file contains driver for the Xilinx PS Timer Counter IP.
   3  *
   4  *  Copyright (C) 2011 Xilinx
   5  *
   6  * based on arch/mips/kernel/time.c timer driver
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/irq.h>
  22 #include <linux/types.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/clockchips.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/zynq_soc.h>
  28 #include "common.h"
  29
  30 #define IRQ_TIMERCOUNTER0       42
  31
  32 /*
  33  * This driver configures the 2 16-bit count-up timers as follows:
  34  *
  35  * T1: Timer 1, clocksource for generic timekeeping
  36  * T2: Timer 2, clockevent source for hrtimers
  37  * T3: Timer 3, <unused>
  38  *
  39  * The input frequency to the timer module for emulation is 2.5MHz which is
  40  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
  41  * the timers are clocked at 78.125KHz (12.8 us resolution).
  42  *
  43  * The input frequency to the timer module in silicon will be 200MHz. With the
  44  * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
  45  */
  46 #define XTTCPSS_CLOCKSOURCE     0       /* Timer 1 as a generic timekeeping */
  47 #define XTTCPSS_CLOCKEVENT      1       /* Timer 2 as a clock event */
  48
  49 #define XTTCPSS_TIMER_BASE              TTC0_BASE
  50 #define XTTCPCC_EVENT_TIMER_IRQ         (IRQ_TIMERCOUNTER0 + 1)
  51 /*
  52  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  53  * and use same offsets for Timer 2
  54  */
  55 #define XTTCPSS_CLK_CNTRL_OFFSET        0x00 /* Clock Control Reg, RW */
  56 #define XTTCPSS_CNT_CNTRL_OFFSET        0x0C /* Counter Control Reg, RW */
  57 #define XTTCPSS_COUNT_VAL_OFFSET        0x18 /* Counter Value Reg, RO */
  58 #define XTTCPSS_INTR_VAL_OFFSET         0x24 /* Interval Count Reg, RW */
  59 #define XTTCPSS_MATCH_1_OFFSET          0x30 /* Match 1 Value Reg, RW */
  60 #define XTTCPSS_MATCH_2_OFFSET          0x3C /* Match 2 Value Reg, RW */
  61 #define XTTCPSS_MATCH_3_OFFSET          0x48 /* Match 3 Value Reg, RW */
  62 #define XTTCPSS_ISR_OFFSET              0x54 /* Interrupt Status Reg, RO */
  63 #define XTTCPSS_IER_OFFSET              0x60 /* Interrupt Enable Reg, RW */
  64
  65 #define XTTCPSS_CNT_CNTRL_DISABLE_MASK  0x1
  66
  67 /* Setup the timers to use pre-scaling */
  68
  69 #define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
  70
  71 /**
  72  * struct xttcpss_timer - This definition defines local timer structure
  73  *
  74  * @base_addr:  Base address of timer
  75  **/
  76 struct xttcpss_timer {
  77         void __iomem *base_addr;
  78 };
  79
  80 static struct xttcpss_timer timers[2];
  81 static struct clock_event_device xttcpss_clockevent;
  82
  83 /**
  84  * xttcpss_set_interval - Set the timer interval value
  85  *
  86  * @timer:      Pointer to the timer instance
  87  * @cycles:     Timer interval ticks
  88  **/
  89 static void xttcpss_set_interval(struct xttcpss_timer *timer,
  90                                         unsigned long cycles)
  91 {
  92         u32 ctrl_reg;
  93
  94         /* Disable the counter, set the counter value  and re-enable counter */
  95         ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
  96         ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
  97         __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
  98
  99         __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
 100
 101         /* Reset the counter (0x10) so that it starts from 0, one-shot
 102            mode makes this needed for timing to be right. */
 103         ctrl_reg |= 0x10;
 104         ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 105         __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 106 }
 107
 108 /**
 109  * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
 110  *
 111  * @irq:        IRQ number of the Timer
 112  * @dev_id:     void pointer to the xttcpss_timer instance
 113  *
 114  * returns: Always IRQ_HANDLED - success
 115  **/
 116 static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
 117 {
 118         struct clock_event_device *evt = &xttcpss_clockevent;
 119         struct xttcpss_timer *timer = dev_id;
 120
 121         /* Acknowledge the interrupt and call event handler */
 122         __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
 123                         timer->base_addr + XTTCPSS_ISR_OFFSET);
 124
 125         evt->event_handler(evt);
 126
 127         return IRQ_HANDLED;
 128 }
 129
 130 static struct irqaction event_timer_irq = {
 131         .name   = "xttcpss clockevent",
 132         .flags  = IRQF_DISABLED | IRQF_TIMER,
 133         .handler = xttcpss_clock_event_interrupt,
 134 };
 135
 136 /**
 137  * xttcpss_timer_hardware_init - Initialize the timer hardware
 138  *
 139  * Initialize the hardware to start the clock source, get the clock
 140  * event timer ready to use, and hook up the interrupt.
 141  **/
 142 static void __init xttcpss_timer_hardware_init(void)
 143 {
 144         /* Setup the clock source counter to be an incrementing counter
 145          * with no interrupt and it rolls over at 0xFFFF. Pre-scale
 146            it by 32 also. Let it start running now.
 147          */
 148         timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
 149
 150         __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
 151                                 XTTCPSS_IER_OFFSET);
 152         __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
 153                                 XTTCPSS_CLK_CNTRL_OFFSET);
 154         __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
 155                                 XTTCPSS_CNT_CNTRL_OFFSET);
 156
 157         /* Setup the clock event timer to be an interval timer which
 158          * is prescaled by 32 using the interval interrupt. Leave it
 159          * disabled for now.
 160          */
 161
 162         timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
 163
 164         __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
 165                         XTTCPSS_CNT_CNTRL_OFFSET);
 166         __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
 167                         XTTCPSS_CLK_CNTRL_OFFSET);
 168         __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
 169                         XTTCPSS_IER_OFFSET);
 170
 171         /* Setup IRQ the clock event timer */
 172         event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
 173         setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
 174 }
 175
 176 /**
 177  * __raw_readl_cycles - Reads the timer counter register
 178  *
 179  * returns: Current timer counter register value
 180  **/
 181 static cycle_t __raw_readl_cycles(struct clocksource *cs)
 182 {
 183         struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
 184
 185         return (cycle_t)__raw_readl(timer->base_addr +
 186                                 XTTCPSS_COUNT_VAL_OFFSET);
 187 }
 188
 189
 190 /*
 191  * Instantiate and initialize the clock source structure
 192  */
 193 static struct clocksource clocksource_xttcpss = {
 194         .name           = "xttcpss_timer1",
 195         .rating         = 200,                  /* Reasonable clock source */
 196         .read           = __raw_readl_cycles,
 197         .mask           = CLOCKSOURCE_MASK(16),
 198         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 199 };
 200
 201
 202 /**
 203  * xttcpss_set_next_event - Sets the time interval for next event
 204  *
 205  * @cycles:     Timer interval ticks
 206  * @evt:        Address of clock event instance
 207  *
 208  * returns: Always 0 - success
 209  **/
 210 static int xttcpss_set_next_event(unsigned long cycles,
 211                                         struct clock_event_device *evt)
 212 {
 213         struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
 214
 215         xttcpss_set_interval(timer, cycles);
 216         return 0;
 217 }
 218
 219 /**
 220  * xttcpss_set_mode - Sets the mode of timer
 221  *
 222  * @mode:       Mode to be set
 223  * @evt:        Address of clock event instance
 224  **/
 225 static void xttcpss_set_mode(enum clock_event_mode mode,
 226                                         struct clock_event_device *evt)
 227 {
 228         struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
 229         u32 ctrl_reg;
 230
 231         switch (mode) {
 232         case CLOCK_EVT_MODE_PERIODIC:
 233                 xttcpss_set_interval(timer, TIMER_RATE / HZ);
 234                 break;
 235         case CLOCK_EVT_MODE_ONESHOT:
 236         case CLOCK_EVT_MODE_UNUSED:
 237         case CLOCK_EVT_MODE_SHUTDOWN:
 238                 ctrl_reg = __raw_readl(timer->base_addr +
 239                                         XTTCPSS_CNT_CNTRL_OFFSET);
 240                 ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 241                 __raw_writel(ctrl_reg,
 242                                 timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 243                 break;
 244         case CLOCK_EVT_MODE_RESUME:
 245                 ctrl_reg = __raw_readl(timer->base_addr +
 246                                         XTTCPSS_CNT_CNTRL_OFFSET);
 247                 ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
 248                 __raw_writel(ctrl_reg,
 249                                 timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
 250                 break;
 251         }
 252 }
 253
 254 /*
 255  * Instantiate and initialize the clock event structure
 256  */
 257 static struct clock_event_device xttcpss_clockevent = {
 258         .name           = "xttcpss_timer2",
 259         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 260         .set_next_event = xttcpss_set_next_event,
 261         .set_mode       = xttcpss_set_mode,
 262         .rating         = 200,
 263 };
 264
 265 /**
 266  * xttcpss_timer_init - Initialize the timer
 267  *
 268  * Initializes the timer hardware and register the clock source and clock event
 269  * timers with Linux kernal timer framework
 270  **/
 271 void __init xttcpss_timer_init(void)
 272 {
 273         xttcpss_timer_hardware_init();
 274         clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
 275
 276         /* Calculate the parameters to allow the clockevent to operate using
 277            integer math
 278         */
 279         clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
 280
 281         xttcpss_clockevent.max_delta_ns =
 282                 clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
 283         xttcpss_clockevent.min_delta_ns =
 284                 clockevent_delta2ns(1, &xttcpss_clockevent);
 285
 286         /* Indicate that clock event is on 1st CPU as SMP boot needs it */
 287
 288         xttcpss_clockevent.cpumask = cpumask_of(0);
 289         clockevents_register_device(&xttcpss_clockevent);
 290 }