arch/arm/mach-versal/mp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * (C) Copyright 2019 Xilinx, Inc.
   4  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/global_data.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/hardware.h>
  11 #include <asm/arch/sys_proto.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 #define HALT            0
  16 #define RELEASE         1
  17
  18 #define VERSAL_RPU_CFG_CPU_HALT_MASK            0x01
  19 #define VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK    0x08
  20 #define VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK      0x40
  21 #define VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK       0x10
  22
  23 #define VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK     0x04
  24 #define VERSAL_CRLAPB_RST_LPD_R50_RST_MASK      0x01
  25 #define VERSAL_CRLAPB_RST_LPD_R51_RST_MASK      0x02
  26 #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK    0x10
  27 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK   0x1000000
  28
  29 void set_r5_halt_mode(u8 halt, u8 mode)
  30 {
  31         u32 tmp;
  32
  33         tmp = readl(&rpu_base->rpu0_cfg);
  34         if (halt == HALT)
  35                 tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
  36         else
  37                 tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
  38         writel(tmp, &rpu_base->rpu0_cfg);
  39
  40         if (mode == TCM_LOCK) {
  41                 tmp = readl(&rpu_base->rpu1_cfg);
  42                 if (halt == HALT)
  43                         tmp &= ~VERSAL_RPU_CFG_CPU_HALT_MASK;
  44                 else
  45                         tmp |= VERSAL_RPU_CFG_CPU_HALT_MASK;
  46                 writel(tmp, &rpu_base->rpu1_cfg);
  47         }
  48 }
  49
  50 void set_r5_tcm_mode(u8 mode)
  51 {
  52         u32 tmp;
  53
  54         tmp = readl(&rpu_base->rpu_glbl_ctrl);
  55         if (mode == TCM_LOCK) {
  56                 tmp &= ~VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  57                 tmp |= VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
  58                        VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK;
  59         } else {
  60                 tmp |= VERSAL_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
  61                 tmp &= ~(VERSAL_RPU_GLBL_CTRL_TCM_COMB_MASK |
  62                        VERSAL_RPU_GLBL_CTRL_SLCLAMP_MASK);
  63         }
  64
  65         writel(tmp, &rpu_base->rpu_glbl_ctrl);
  66 }
  67
  68 void release_r5_reset(u8 mode)
  69 {
  70         u32 tmp;
  71
  72         tmp = readl(&crlapb_base->rst_cpu_r5);
  73         tmp &= ~(VERSAL_CRLAPB_RST_LPD_AMBA_RST_MASK |
  74                VERSAL_CRLAPB_RST_LPD_R50_RST_MASK |
  75                VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK);
  76
  77         if (mode == TCM_LOCK)
  78                 tmp &= ~VERSAL_CRLAPB_RST_LPD_R51_RST_MASK;
  79
  80         writel(tmp, &crlapb_base->rst_cpu_r5);
  81 }
  82
  83 void enable_clock_r5(void)
  84 {
  85         u32 tmp;
  86
  87         tmp = readl(&crlapb_base->cpu_r5_ctrl);
  88         tmp |= VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
  89         writel(tmp, &crlapb_base->cpu_r5_ctrl);
  90 }
  91
  92 void initialize_tcm(bool mode)
  93 {
  94         if (!mode) {
  95                 set_r5_tcm_mode(TCM_LOCK);
  96                 set_r5_halt_mode(HALT, TCM_LOCK);
  97                 enable_clock_r5();
  98                 release_r5_reset(TCM_LOCK);
  99         } else {
 100                 set_r5_tcm_mode(TCM_SPLIT);
 101                 set_r5_halt_mode(HALT, TCM_SPLIT);
 102                 enable_clock_r5();
 103                 release_r5_reset(TCM_SPLIT);
 104         }
 105 }
 106
 107 void tcm_init(u8 mode)
 108 {
 109         puts("WARNING: Initializing TCM overwrites TCM content\n");
 110         initialize_tcm(mode);
 111         memset((void *)VERSAL_TCM_BASE_ADDR, 0, VERSAL_TCM_SIZE);
 112 }