1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016 - 2018 Xilinx, Inc.
6 #define VERSAL_CRL_APB_BASEADDR 0xFF5E0000
8 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
10 #define IOU_SWITCH_CTRL_CLKACT_BIT BIT(25)
11 #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
17 u32 iou_switch_ctrl; /* 0x114 */
19 u32 timestamp_ref_ctrl; /* 0x14c */
23 u32 rst_timestamp; /* 0x348 */
26 #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
28 #define VERSAL_IOU_SCNTR_SECURE 0xFF140000
30 #define IOU_SCNTRS_CONTROL_EN 1
32 struct iou_scntrs_regs {
33 u32 counter_control_register; /* 0x0 */
35 u32 base_frequency_id_register; /* 0x20 */
38 #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)
40 #define VERSAL_TCM_BASE_ADDR 0xFFE00000
41 #define VERSAL_TCM_SIZE 0x40000
43 #define VERSAL_RPU_BASEADDR 0xFF9A0000
48 u32 rpu0_cfg; /* 0x100 */
50 u32 rpu1_cfg; /* 0x200 */
53 #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR)