arch/arm/mach-versal/include/mach/hardware.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2016 - 2018 Xilinx, Inc.
   4  */
   5
   6 #define VERSAL_CRL_APB_BASEADDR 0xFF5E0000
   7
   8 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT   BIT(25)
   9
  10 #define IOU_SWITCH_CTRL_CLKACT_BIT      BIT(25)
  11 #define IOU_SWITCH_CTRL_DIVISOR0_SHIFT  8
  12
  13 struct crlapb_regs {
  14         u32 reserved0[69];
  15         u32 iou_switch_ctrl; /* 0x114 */
  16         u32 reserved1[13];
  17         u32 timestamp_ref_ctrl; /* 0x14c */
  18         u32 reserved2[126];
  19         u32 rst_timestamp; /* 0x348 */
  20 };
  21
  22 #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
  23
  24 #define VERSAL_IOU_SCNTR_SECURE 0xFF140000
  25
  26 #define IOU_SCNTRS_CONTROL_EN   1
  27
  28 struct iou_scntrs_regs {
  29         u32 counter_control_register; /* 0x0 */
  30         u32 reserved0[7];
  31         u32 base_frequency_id_register; /* 0x20 */
  32 };
  33
  34 #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)