arch/arm/mach-ux500/board-mop500-pins.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/bug.h>
  10 #include <linux/string.h>
  11 #include <linux/pinctrl/machine.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13 #include <linux/platform_data/pinctrl-nomadik.h>
  14
  15 #include <asm/mach-types.h>
  16
  17 #include "board-mop500.h"
  18
  19 enum custom_pin_cfg_t {
  20         PINS_FOR_DEFAULT,
  21         PINS_FOR_U9500,
  22 };
  23
  24 static enum custom_pin_cfg_t pinsfor;
  25
  26 /* These simply sets bias for pins */
  27 #define BIAS(a,b) static unsigned long a[] = { b }
  28
  29 BIAS(pd, PIN_PULL_DOWN);
  30 BIAS(in_nopull, PIN_INPUT_NOPULL);
  31 BIAS(in_pu, PIN_INPUT_PULLUP);
  32 BIAS(in_pd, PIN_INPUT_PULLDOWN);
  33 BIAS(out_lo, PIN_OUTPUT_LOW);
  34
  35 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
  36 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
  37 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
  38
  39 /* These also force them into GPIO mode */
  40 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
  41 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
  42 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  43 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  44 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
  45 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
  46 /* Sleep modes */
  47 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  48         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  49 BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  50         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  51 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
  52         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
  53 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  54         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  55 BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
  56         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  57
  58 /* We use these to define hog settings that are always done on boot */
  59 #define DB8500_MUX_HOG(group,func) \
  60         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
  61 #define DB8500_PIN_HOG(pin,conf) \
  62         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
  63
  64 /* These are default states associated with device and changed runtime */
  65 #define DB8500_MUX(group,func,dev) \
  66         PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
  67 #define DB8500_PIN(pin,conf,dev) \
  68         PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
  69 #define DB8500_PIN_IDLE(pin, conf, dev) \
  70         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
  71                             pin, conf)
  72 #define DB8500_PIN_SLEEP(pin, conf, dev) \
  73         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
  74                             pin, conf)
  75 #define DB8500_MUX_STATE(group, func, dev, state) \
  76         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
  77 #define DB8500_PIN_STATE(pin, conf, dev, state) \
  78         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
  79
  80 #define AB8500_MUX_HOG(group, func) \
  81         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
  82 #define AB8500_PIN_HOG(pin, conf) \
  83         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
  84
  85 #define AB8500_MUX_STATE(group, func, dev, state) \
  86         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
  87 #define AB8500_PIN_STATE(pin, conf, dev, state) \
  88         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
  89
  90 #define AB8505_MUX_HOG(group, func) \
  91         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
  92 #define AB8505_PIN_HOG(pin, conf) \
  93         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
  94
  95 #define AB8505_MUX_STATE(group, func, dev, state) \
  96         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
  97 #define AB8505_PIN_STATE(pin, conf, dev, state) \
  98         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
  99
 100 static struct pinctrl_map __initdata ab8500_pinmap[] = {
 101         /* Sysclkreq2 */
 102         AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
 103         AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
 104         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 105         AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
 106         AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
 107
 108         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 109         AB8500_MUX_HOG("gpio2_a_1", "gpio"),
 110         AB8500_PIN_HOG("GPIO2_T9", in_pd),
 111
 112         /* Sysclkreq4 */
 113         AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 114         AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 115         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 116         AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 117         AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 118
 119         /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
 120         AB8500_MUX_HOG("gpio4_a_1", "gpio"),
 121         AB8500_PIN_HOG("GPIO4_W2", in_pd),
 122
 123         /*
 124          * pins 6,7,8 and 9 are muxed in YCBCR0123
 125          * configured in INPUT PULL UP
 126          */
 127         AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
 128         AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
 129         AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
 130         AB8500_PIN_HOG("GPIO8_W18", in_nopull),
 131         AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
 132
 133         /*
 134          * pins 10,11,12 and 13 are muxed in GPIO
 135          * configured in INPUT PULL DOWN
 136          */
 137         AB8500_MUX_HOG("gpio10_d_1", "gpio"),
 138         AB8500_PIN_HOG("GPIO10_U17", in_pd),
 139
 140         AB8500_MUX_HOG("gpio11_d_1", "gpio"),
 141         AB8500_PIN_HOG("GPIO11_AA18", in_pd),
 142
 143         AB8500_MUX_HOG("gpio12_d_1", "gpio"),
 144         AB8500_PIN_HOG("GPIO12_U16", in_pd),
 145
 146         AB8500_MUX_HOG("gpio13_d_1", "gpio"),
 147         AB8500_PIN_HOG("GPIO13_W17", in_pd),
 148
 149         /*
 150          * pins 14,15 are muxed in PWM1 and PWM2
 151          * configured in INPUT PULL DOWN
 152          */
 153         AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
 154         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 155
 156         AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
 157         AB8500_PIN_HOG("GPIO15_B17", in_pd),
 158
 159         /*
 160          * pins 16 is muxed in GPIO
 161          * configured in INPUT PULL DOWN
 162          */
 163         AB8500_MUX_HOG("gpio16_a_1", "gpio"),
 164         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 165
 166         /*
 167          * pins 17,18,19 and 20 are muxed in AUDIO interface 1
 168          * configured in INPUT PULL DOWN
 169          */
 170         AB8500_MUX_HOG("adi1_d_1", "adi1"),
 171         AB8500_PIN_HOG("GPIO17_P5", in_pd),
 172         AB8500_PIN_HOG("GPIO18_R5", in_pd),
 173         AB8500_PIN_HOG("GPIO19_U5", in_pd),
 174         AB8500_PIN_HOG("GPIO20_T5", in_pd),
 175
 176         /*
 177          * pins 21,22 and 23 are muxed in USB UICC
 178          * configured in INPUT PULL DOWN
 179          */
 180         AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
 181         AB8500_PIN_HOG("GPIO21_H19", in_pd),
 182         AB8500_PIN_HOG("GPIO22_G20", in_pd),
 183         AB8500_PIN_HOG("GPIO23_G19", in_pd),
 184
 185         /*
 186          * pins 24,25 are muxed in GPIO
 187          * configured in INPUT PULL DOWN
 188          */
 189         AB8500_MUX_HOG("gpio24_a_1", "gpio"),
 190         AB8500_PIN_HOG("GPIO24_T14", in_pd),
 191
 192         AB8500_MUX_HOG("gpio25_a_1", "gpio"),
 193         AB8500_PIN_HOG("GPIO25_R16", in_pd),
 194
 195         /*
 196          * pins 26 is muxed in GPIO
 197          * configured in OUTPUT LOW
 198          */
 199         AB8500_MUX_HOG("gpio26_d_1", "gpio"),
 200         AB8500_PIN_HOG("GPIO26_M16", out_lo),
 201
 202         /*
 203          * pins 27,28 are muxed in DMIC12
 204          * configured in INPUT PULL DOWN
 205          */
 206         AB8500_MUX_HOG("dmic12_d_1", "dmic"),
 207         AB8500_PIN_HOG("GPIO27_J6", in_pd),
 208         AB8500_PIN_HOG("GPIO28_K6", in_pd),
 209
 210         /*
 211          * pins 29,30 are muxed in DMIC34
 212          * configured in INPUT PULL DOWN
 213          */
 214         AB8500_MUX_HOG("dmic34_d_1", "dmic"),
 215         AB8500_PIN_HOG("GPIO29_G6", in_pd),
 216         AB8500_PIN_HOG("GPIO30_H6", in_pd),
 217
 218         /*
 219          * pins 31,32 are muxed in DMIC56
 220          * configured in INPUT PULL DOWN
 221          */
 222         AB8500_MUX_HOG("dmic56_d_1", "dmic"),
 223         AB8500_PIN_HOG("GPIO31_F5", in_pd),
 224         AB8500_PIN_HOG("GPIO32_G5", in_pd),
 225
 226         /*
 227          * pins 34 is muxed in EXTCPENA
 228          * configured INPUT PULL DOWN
 229          */
 230         AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
 231         AB8500_PIN_HOG("GPIO34_R17", in_pd),
 232
 233         /*
 234          * pins 35 is muxed in GPIO
 235          * configured in OUTPUT LOW
 236          */
 237         AB8500_MUX_HOG("gpio35_d_1", "gpio"),
 238         AB8500_PIN_HOG("GPIO35_W15", in_pd),
 239
 240         /*
 241          * pins 36,37,38 and 39 are muxed in GPIO
 242          * configured in INPUT PULL DOWN
 243          */
 244         AB8500_MUX_HOG("gpio36_a_1", "gpio"),
 245         AB8500_PIN_HOG("GPIO36_A17", in_pd),
 246
 247         AB8500_MUX_HOG("gpio37_a_1", "gpio"),
 248         AB8500_PIN_HOG("GPIO37_E15", in_pd),
 249
 250         AB8500_MUX_HOG("gpio38_a_1", "gpio"),
 251         AB8500_PIN_HOG("GPIO38_C17", in_pd),
 252
 253         AB8500_MUX_HOG("gpio39_a_1", "gpio"),
 254         AB8500_PIN_HOG("GPIO39_E16", in_pd),
 255
 256         /*
 257          * pins 40 and 41 are muxed in MODCSLSDA
 258          * configured INPUT PULL DOWN
 259          */
 260         AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
 261         AB8500_PIN_HOG("GPIO40_T19", in_pd),
 262         AB8500_PIN_HOG("GPIO41_U19", in_pd),
 263
 264         /*
 265          * pins 42 is muxed in GPIO
 266          * configured INPUT PULL DOWN
 267          */
 268         AB8500_MUX_HOG("gpio42_a_1", "gpio"),
 269         AB8500_PIN_HOG("GPIO42_U2", in_pd),
 270 };
 271
 272 static struct pinctrl_map __initdata ab8505_pinmap[] = {
 273         /* Sysclkreq2 */
 274         AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 275         AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 276         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 277         AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 278         AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 279
 280         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 281         AB8505_MUX_HOG("gpio2_a_1", "gpio"),
 282         AB8505_PIN_HOG("GPIO2_R5", in_pd),
 283
 284         /* Sysclkreq4 */
 285         AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
 286         AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
 287         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 288         AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
 289         AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
 290
 291         AB8505_MUX_HOG("gpio10_d_1", "gpio"),
 292         AB8505_PIN_HOG("GPIO10_B16", in_pd),
 293
 294         AB8505_MUX_HOG("gpio11_d_1", "gpio"),
 295         AB8505_PIN_HOG("GPIO11_B17", in_pd),
 296
 297         AB8505_MUX_HOG("gpio13_d_1", "gpio"),
 298         AB8505_PIN_HOG("GPIO13_D17", in_nopull),
 299
 300         AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
 301         AB8505_PIN_HOG("GPIO14_C16", in_pd),
 302
 303         AB8505_MUX_HOG("adi2_d_1", "adi2"),
 304         AB8505_PIN_HOG("GPIO17_P2", in_pd),
 305         AB8505_PIN_HOG("GPIO18_N3", in_pd),
 306         AB8505_PIN_HOG("GPIO19_T1", in_pd),
 307         AB8505_PIN_HOG("GPIO20_P3", in_pd),
 308
 309         AB8505_MUX_HOG("gpio34_a_1", "gpio"),
 310         AB8505_PIN_HOG("GPIO34_H14", in_pd),
 311
 312         AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
 313         AB8505_PIN_HOG("GPIO40_J15", in_pd),
 314         AB8505_PIN_HOG("GPIO41_J14", in_pd),
 315
 316         AB8505_MUX_HOG("gpio50_d_1", "gpio"),
 317         AB8505_PIN_HOG("GPIO50_L4", in_nopull),
 318
 319         AB8505_MUX_HOG("resethw_d_1", "resethw"),
 320         AB8505_PIN_HOG("GPIO52_D16", in_pd),
 321
 322         AB8505_MUX_HOG("service_d_1", "service"),
 323         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 324 };
 325
 326 /* Pin control settings */
 327 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 328         /*
 329          * LCD, set TE0 (using LCD VSI0) and D14 (touch screen interrupt) to
 330          * pull-up
 331          * TODO: is this really correct? Snowball doesn't have a LCD.
 332          */
 333         DB8500_MUX_HOG("lcdvsi0_a_1", "lcd"),
 334         DB8500_PIN_HOG("GPIO68_E1", in_pu),
 335         DB8500_PIN_HOG("GPIO84_C2", gpio_in_pu),
 336         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
 337         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
 338         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
 339         /* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
 340         DB8500_MUX("lcdvsi1_a_1", "lcd", "0-0070"),
 341         DB8500_PIN("GPIO69_E2", in_pu, "0-0070"),
 342         /* LCD VSI1 sleep state */
 343         DB8500_PIN_SLEEP("GPIO69_E2", slpm_in_wkup_pdis, "0-0070"),
 344
 345         /* ske default state */
 346         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 347         DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
 348         DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
 349         DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
 350         DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
 351         DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
 352         DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
 353         DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
 354         DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
 355         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 356         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 357         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 358         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 359         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 360         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 361         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 362         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 363         /* ske sleep state */
 364         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 365         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 366         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 367         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 368         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 369         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 370         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 371         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 372         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 373         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 374         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 375         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 376         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 377         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 378         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 379         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 380
 381         /* STM APE pins states */
 382         DB8500_MUX_STATE("stmape_c_1", "stmape",
 383                 "stm", "ape_mipi34"),
 384         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 385                 "stm", "ape_mipi34"), /* clk */
 386         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 387                 "stm", "ape_mipi34"), /* dat3 */
 388         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 389                 "stm", "ape_mipi34"), /* dat2 */
 390         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 391                 "stm", "ape_mipi34"), /* dat1 */
 392         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 393                 "stm", "ape_mipi34"), /* dat0 */
 394
 395         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 396                 "stm", "ape_mipi34_sleep"), /* clk */
 397         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 398                 "stm", "ape_mipi34_sleep"), /* dat3 */
 399         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 400                 "stm", "ape_mipi34_sleep"), /* dat2 */
 401         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 402                 "stm", "ape_mipi34_sleep"), /* dat1 */
 403         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 404                 "stm", "ape_mipi34_sleep"), /* dat0 */
 405
 406         DB8500_MUX_STATE("stmape_oc1_1", "stmape",
 407                 "stm", "ape_microsd"),
 408         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 409                 "stm", "ape_microsd"), /* clk */
 410         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 411                 "stm", "ape_microsd"), /* dat0 */
 412         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 413                 "stm", "ape_microsd"), /* dat1 */
 414         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 415                 "stm", "ape_microsd"), /* dat2 */
 416         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 417                 "stm", "ape_microsd"), /* dat3 */
 418
 419         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 420                 "stm", "ape_microsd_sleep"), /* clk */
 421         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 422                 "stm", "ape_microsd_sleep"), /* dat0 */
 423         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 424                 "stm", "ape_microsd_sleep"), /* dat1 */
 425         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 426                 "stm", "ape_microsd_sleep"), /* dat2 */
 427         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 428                 "stm", "ape_microsd_sleep"), /* dat3 */
 429
 430         /*  STM Modem pins states */
 431         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 432                 "stm", "mod_mipi34"),
 433         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 434                 "stm", "mod_mipi34"),
 435         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 436                 "stm", "mod_mipi34"),
 437         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 438                 "stm", "mod_mipi34"), /* clk */
 439         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 440                 "stm", "mod_mipi34"), /* dat3 */
 441         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 442                 "stm", "mod_mipi34"), /* dat2 */
 443         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 444                 "stm", "mod_mipi34"), /* dat1 */
 445         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 446                 "stm", "mod_mipi34"), /* dat0 */
 447         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 448                 "stm", "mod_mipi34"), /* uartmod rx */
 449         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 450                 "stm", "mod_mipi34"), /* uartmod tx */
 451
 452         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 453                 "stm", "mod_mipi34_sleep"), /* clk */
 454         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 455                 "stm", "mod_mipi34_sleep"), /* dat3 */
 456         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 457                 "stm", "mod_mipi34_sleep"), /* dat2 */
 458         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 459                 "stm", "mod_mipi34_sleep"), /* dat1 */
 460         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 461                 "stm", "mod_mipi34_sleep"), /* dat0 */
 462         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 463                 "stm", "mod_mipi34_sleep"), /* uartmod rx */
 464         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 465                 "stm", "mod_mipi34_sleep"), /* uartmod tx */
 466
 467         DB8500_MUX_STATE("stmmod_b_1", "stmmod",
 468                 "stm", "mod_microsd"),
 469         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 470                 "stm", "mod_microsd"),
 471         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 472                 "stm", "mod_microsd"),
 473         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 474                 "stm", "mod_microsd"), /* clk */
 475         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 476                 "stm", "mod_microsd"), /* dat0 */
 477         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 478                 "stm", "mod_microsd"), /* dat1 */
 479         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 480                 "stm", "mod_microsd"), /* dat2 */
 481         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 482                 "stm", "mod_microsd"), /* dat3 */
 483         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 484                 "stm", "mod_microsd"), /* uartmod rx */
 485         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 486                 "stm", "mod_microsd"), /* uartmod tx */
 487
 488         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 489                 "stm", "mod_microsd_sleep"), /* clk */
 490         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 491                 "stm", "mod_microsd_sleep"), /* dat0 */
 492         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 493                 "stm", "mod_microsd_sleep"), /* dat1 */
 494         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 495                 "stm", "mod_microsd_sleep"), /* dat2 */
 496         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 497                 "stm", "mod_microsd_sleep"), /* dat3 */
 498         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 499                 "stm", "mod_microsd_sleep"), /* uartmod rx */
 500         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 501                 "stm", "mod_microsd_sleep"), /* uartmod tx */
 502
 503         /*  STM dual Modem/APE pins state */
 504         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 505                 "stm", "mod_mipi34_ape_mipi60"),
 506         DB8500_MUX_STATE("stmape_c_2", "stmape",
 507                 "stm", "mod_mipi34_ape_mipi60"),
 508         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 509                 "stm", "mod_mipi34_ape_mipi60"),
 510         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 511                 "stm", "mod_mipi34_ape_mipi60"),
 512         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 513                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 514         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 515                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 516         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 517                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 518         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 519                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 520         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 521                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 522         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 523                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
 524         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 525                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
 526         DB8500_PIN_STATE("GPIO155_C19", in_nopull,
 527                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 528         DB8500_PIN_STATE("GPIO156_C17", in_nopull,
 529                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 530         DB8500_PIN_STATE("GPIO157_A18", in_nopull,
 531                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 532         DB8500_PIN_STATE("GPIO158_C18", in_nopull,
 533                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 534         DB8500_PIN_STATE("GPIO159_B19", in_nopull,
 535                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 536
 537         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 538                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 539         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 540                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 541         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 542                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 543         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 544                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 545         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 546                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 547         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 548                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
 549         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 550                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
 551         DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
 552                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 553         DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
 554                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 555         DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
 556                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 557         DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
 558                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 559         DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
 560                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 561 };
 562
 563 /*
 564  * These are specifically for the MOP500 and HREFP (pre-v60) version of the
 565  * board, which utilized a TC35892 GPIO expander instead of using a lot of
 566  * on-chip pins as the HREFv60 and later does.
 567  */
 568 static struct pinctrl_map __initdata mop500_pinmap[] = {
 569         /*
 570          * XENON Flashgun on image processor GPIO (controlled from image
 571          * processor firmware), mux in these image processor GPIO lines 0
 572          * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
 573          * the pins.
 574          */
 575         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 576         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 577         DB8500_PIN_HOG("GPIO6_AF6", in_pu),
 578         DB8500_PIN_HOG("GPIO7_AG5", in_pu),
 579         /*
 580          * Runtime stuff: make it possible to mux in the SKE keypad
 581          * and bias the pins
 582          */
 583         /* ske default state */
 584         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 585         DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
 586         DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
 587         DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
 588         DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
 589         DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
 590         DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
 591         DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
 592         DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
 593         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 594         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 595         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 596         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 597         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 598         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 599         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 600         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 601         /* ske sleep state */
 602         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 603         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 604         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 605         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 606         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 607         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 608         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 609         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 610         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 611         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 612         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 613         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 614         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 615         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 616         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 617         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 618 };
 619
 620 /*
 621  * The HREFv60 series of platforms is using available pins on the DB8500
 622  * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
 623  * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
 624  */
 625 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
 626         /* Drive WLAN_ENA low */
 627         DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
 628         /*
 629          * XENON Flashgun on image processor GPIO (controlled from image
 630          * processor firmware), mux in these image processor GPIO lines 0
 631          * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
 632          * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
 633          * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
 634          */
 635         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 636         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 637         DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
 638         DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
 639         DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
 640         DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
 641         DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
 642         /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
 643         DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
 644         DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
 645         /*
 646          * Display Interface 1 uses GPIO 65 for RST (reset).
 647          * Display Interface 2 uses GPIO 66 for RST (reset).
 648          * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
 649          */
 650         DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
 651         DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
 652         /*
 653          * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
 654          * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
 655          * reset signals low.
 656          */
 657         DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
 658         DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
 659         DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
 660         /*
 661          * Drive D19-D23 for the ETM PTM trace interface low,
 662          * (presumably pins are unconnected therefore grounded here,
 663          * the "other alt C1" setting enables these pins)
 664          */
 665         DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
 666         DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
 667         DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
 668         DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
 669         DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
 670         /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
 671         DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
 672         DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
 673         /* NFC ENA and RESET to low, pulldown IRQ line */
 674         DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
 675         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
 676         DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
 677         /*
 678          * SKE keyboard partly on alt A and partly on "Other alt C1"
 679          * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
 680          * rows of 6 keys, then pull up force sensing interrup and
 681          * drive reset and force sensing WU low.
 682          */
 683         DB8500_MUX_HOG("kp_a_1", "kp"),
 684         DB8500_MUX_HOG("kp_oc1_1", "kp"),
 685         DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
 686         DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
 687         DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
 688         DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
 689         DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
 690         DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
 691         DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
 692         DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
 693         DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
 694         DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
 695         DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
 696         /* DiPro Sensor interrupt */
 697         DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
 698         /* Audio Amplifier HF enable */
 699         DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
 700         /* GBF interface, pull low to reset state */
 701         DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
 702         /* MSP : HDTV INTERFACE GPIO line */
 703         DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
 704         /* Accelerometer interrupt lines */
 705         DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
 706         DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
 707         /*
 708          * Runtime stuff
 709          * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
 710          * etc.
 711          */
 712         DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 713         DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
 714         DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 715 };
 716
 717 static struct pinctrl_map __initdata u9500_pinmap[] = {
 718         /* WLAN_IRQ line */
 719         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
 720         /* HSI */
 721         DB8500_MUX_HOG("hsir_a_1", "hsi"),
 722         DB8500_MUX_HOG("hsit_a_2", "hsi"),
 723         DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
 724         DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
 725         DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
 726         DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
 727         DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
 728         DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
 729         DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
 730         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 731 };
 732
 733 static struct pinctrl_map __initdata u8500_pinmap[] = {
 734         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
 735         DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
 736 };
 737
 738 static struct pinctrl_map __initdata snowball_pinmap[] = {
 739         /* Mux in SSP0 connected to AB8500, pull down RXD pin */
 740         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
 741         DB8500_PIN_HOG("GPIO145_C13", pd),
 742         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
 743         DB8500_MUX_HOG("sm_b_1", "sm"),
 744         /* User LED */
 745         DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
 746         /* Drive RSTn_LAN high */
 747         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
 748         /*  Accelerometer/Magnetometer */
 749         DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
 750         DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
 751         DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
 752         /* WLAN/GBF */
 753         DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
 754         DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
 755         DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
 756         DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
 757 };
 758
 759 /*
 760  * passing "pinsfor=" in kernel cmdline allows for custom
 761  * configuration of GPIOs on u8500 derived boards.
 762  */
 763 static int __init early_pinsfor(char *p)
 764 {
 765         pinsfor = PINS_FOR_DEFAULT;
 766
 767         if (strcmp(p, "u9500-21") == 0)
 768                 pinsfor = PINS_FOR_U9500;
 769
 770         return 0;
 771 }
 772 early_param("pinsfor", early_pinsfor);
 773
 774 int pins_for_u9500(void)
 775 {
 776         if (pinsfor == PINS_FOR_U9500)
 777                 return 1;
 778
 779         return 0;
 780 }
 781
 782 static void __init mop500_href_family_pinmaps_init(void)
 783 {
 784         switch (pinsfor) {
 785         case PINS_FOR_U9500:
 786                 pinctrl_register_mappings(u9500_pinmap,
 787                                           ARRAY_SIZE(u9500_pinmap));
 788                 break;
 789         case PINS_FOR_DEFAULT:
 790                 pinctrl_register_mappings(u8500_pinmap,
 791                                           ARRAY_SIZE(u8500_pinmap));
 792         default:
 793                 break;
 794         }
 795 }
 796
 797 void __init mop500_pinmaps_init(void)
 798 {
 799         pinctrl_register_mappings(mop500_family_pinmap,
 800                                   ARRAY_SIZE(mop500_family_pinmap));
 801         pinctrl_register_mappings(mop500_pinmap,
 802                                   ARRAY_SIZE(mop500_pinmap));
 803         mop500_href_family_pinmaps_init();
 804         if (machine_is_u8520())
 805                 pinctrl_register_mappings(ab8505_pinmap,
 806                                           ARRAY_SIZE(ab8505_pinmap));
 807         else
 808                 pinctrl_register_mappings(ab8500_pinmap,
 809                                           ARRAY_SIZE(ab8500_pinmap));
 810 }
 811
 812 void __init snowball_pinmaps_init(void)
 813 {
 814         pinctrl_register_mappings(mop500_family_pinmap,
 815                                   ARRAY_SIZE(mop500_family_pinmap));
 816         pinctrl_register_mappings(snowball_pinmap,
 817                                   ARRAY_SIZE(snowball_pinmap));
 818         pinctrl_register_mappings(u8500_pinmap,
 819                                   ARRAY_SIZE(u8500_pinmap));
 820         pinctrl_register_mappings(ab8500_pinmap,
 821                                   ARRAY_SIZE(ab8500_pinmap));
 822 }
 823
 824 void __init hrefv60_pinmaps_init(void)
 825 {
 826         pinctrl_register_mappings(mop500_family_pinmap,
 827                                   ARRAY_SIZE(mop500_family_pinmap));
 828         pinctrl_register_mappings(hrefv60_pinmap,
 829                                   ARRAY_SIZE(hrefv60_pinmap));
 830         mop500_href_family_pinmaps_init();
 831         pinctrl_register_mappings(ab8500_pinmap,
 832                                   ARRAY_SIZE(ab8500_pinmap));
 833 }