2 * Copyright (C) ST-Ericsson SA 2010
4 * License terms: GNU General Public License (GPL) version 2
7 #include <linux/kernel.h>
8 #include <linux/init.h>
10 #include <linux/string.h>
11 #include <linux/pinctrl/machine.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/platform_data/pinctrl-nomadik.h>
15 #include <asm/mach-types.h>
17 #include "board-mop500.h"
19 /* These simply sets bias for pins */
20 #define BIAS(a,b) static unsigned long a[] = { b }
22 BIAS(pd, PIN_PULL_DOWN);
24 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
25 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
26 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
28 /* These also force them into GPIO mode */
29 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
30 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
31 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
33 /* We use these to define hog settings that are always done on boot */
34 #define DB8500_MUX_HOG(group,func) \
35 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
36 #define DB8500_PIN_HOG(pin,conf) \
37 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
39 /* These are default states associated with device and changed runtime */
40 #define DB8500_MUX(group,func,dev) \
41 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
42 #define DB8500_PIN(pin,conf,dev) \
43 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
44 #define DB8500_PIN_IDLE(pin, conf, dev) \
45 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \
47 #define DB8500_PIN_SLEEP(pin, conf, dev) \
48 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
50 #define DB8500_MUX_STATE(group, func, dev, state) \
51 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
52 #define DB8500_PIN_STATE(pin, conf, dev, state) \
53 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
55 #define AB8500_MUX_HOG(group, func) \
56 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
57 #define AB8500_PIN_HOG(pin, conf) \
58 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
60 #define AB8500_MUX_STATE(group, func, dev, state) \
61 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
62 #define AB8500_PIN_STATE(pin, conf, dev, state) \
63 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
65 #define AB8505_MUX_HOG(group, func) \
66 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
67 #define AB8505_PIN_HOG(pin, conf) \
68 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
70 #define AB8505_MUX_STATE(group, func, dev, state) \
71 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
72 #define AB8505_PIN_STATE(pin, conf, dev, state) \
73 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
75 static struct pinctrl_map __initdata ab8500_pinmap[] = {
77 AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
78 AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
79 /* sysclkreq2 disable, mux in gpio configured in input pulldown */
80 AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
81 AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
83 /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
84 AB8500_MUX_HOG("gpio2_a_1", "gpio"),
85 AB8500_PIN_HOG("GPIO2_T9", in_pd),
88 AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
89 AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
90 /* sysclkreq4 disable, mux in gpio configured in input pulldown */
91 AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
92 AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
94 /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
95 AB8500_MUX_HOG("gpio4_a_1", "gpio"),
96 AB8500_PIN_HOG("GPIO4_W2", in_pd),
99 * pins 6,7,8 and 9 are muxed in YCBCR0123
100 * configured in INPUT PULL UP
102 AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
103 AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
104 AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
105 AB8500_PIN_HOG("GPIO8_W18", in_nopull),
106 AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
109 * pins 10,11,12 and 13 are muxed in GPIO
110 * configured in INPUT PULL DOWN
112 AB8500_MUX_HOG("gpio10_d_1", "gpio"),
113 AB8500_PIN_HOG("GPIO10_U17", in_pd),
115 AB8500_MUX_HOG("gpio11_d_1", "gpio"),
116 AB8500_PIN_HOG("GPIO11_AA18", in_pd),
118 AB8500_MUX_HOG("gpio12_d_1", "gpio"),
119 AB8500_PIN_HOG("GPIO12_U16", in_pd),
121 AB8500_MUX_HOG("gpio13_d_1", "gpio"),
122 AB8500_PIN_HOG("GPIO13_W17", in_pd),
125 * pins 14,15 are muxed in PWM1 and PWM2
126 * configured in INPUT PULL DOWN
128 AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
129 AB8500_PIN_HOG("GPIO14_F14", in_pd),
131 AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
132 AB8500_PIN_HOG("GPIO15_B17", in_pd),
135 * pins 16 is muxed in GPIO
136 * configured in INPUT PULL DOWN
138 AB8500_MUX_HOG("gpio16_a_1", "gpio"),
139 AB8500_PIN_HOG("GPIO14_F14", in_pd),
142 * pins 17,18,19 and 20 are muxed in AUDIO interface 1
143 * configured in INPUT PULL DOWN
145 AB8500_MUX_HOG("adi1_d_1", "adi1"),
146 AB8500_PIN_HOG("GPIO17_P5", in_pd),
147 AB8500_PIN_HOG("GPIO18_R5", in_pd),
148 AB8500_PIN_HOG("GPIO19_U5", in_pd),
149 AB8500_PIN_HOG("GPIO20_T5", in_pd),
152 * pins 21,22 and 23 are muxed in USB UICC
153 * configured in INPUT PULL DOWN
155 AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
156 AB8500_PIN_HOG("GPIO21_H19", in_pd),
157 AB8500_PIN_HOG("GPIO22_G20", in_pd),
158 AB8500_PIN_HOG("GPIO23_G19", in_pd),
161 * pins 24,25 are muxed in GPIO
162 * configured in INPUT PULL DOWN
164 AB8500_MUX_HOG("gpio24_a_1", "gpio"),
165 AB8500_PIN_HOG("GPIO24_T14", in_pd),
167 AB8500_MUX_HOG("gpio25_a_1", "gpio"),
168 AB8500_PIN_HOG("GPIO25_R16", in_pd),
171 * pins 26 is muxed in GPIO
172 * configured in OUTPUT LOW
174 AB8500_MUX_HOG("gpio26_d_1", "gpio"),
175 AB8500_PIN_HOG("GPIO26_M16", out_lo),
178 * pins 27,28 are muxed in DMIC12
179 * configured in INPUT PULL DOWN
181 AB8500_MUX_HOG("dmic12_d_1", "dmic"),
182 AB8500_PIN_HOG("GPIO27_J6", in_pd),
183 AB8500_PIN_HOG("GPIO28_K6", in_pd),
186 * pins 29,30 are muxed in DMIC34
187 * configured in INPUT PULL DOWN
189 AB8500_MUX_HOG("dmic34_d_1", "dmic"),
190 AB8500_PIN_HOG("GPIO29_G6", in_pd),
191 AB8500_PIN_HOG("GPIO30_H6", in_pd),
194 * pins 31,32 are muxed in DMIC56
195 * configured in INPUT PULL DOWN
197 AB8500_MUX_HOG("dmic56_d_1", "dmic"),
198 AB8500_PIN_HOG("GPIO31_F5", in_pd),
199 AB8500_PIN_HOG("GPIO32_G5", in_pd),
202 * pins 34 is muxed in EXTCPENA
203 * configured INPUT PULL DOWN
205 AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
206 AB8500_PIN_HOG("GPIO34_R17", in_pd),
209 * pins 35 is muxed in GPIO
210 * configured in OUTPUT LOW
212 AB8500_MUX_HOG("gpio35_d_1", "gpio"),
213 AB8500_PIN_HOG("GPIO35_W15", in_pd),
216 * pins 36,37,38 and 39 are muxed in GPIO
217 * configured in INPUT PULL DOWN
219 AB8500_MUX_HOG("gpio36_a_1", "gpio"),
220 AB8500_PIN_HOG("GPIO36_A17", in_pd),
222 AB8500_MUX_HOG("gpio37_a_1", "gpio"),
223 AB8500_PIN_HOG("GPIO37_E15", in_pd),
225 AB8500_MUX_HOG("gpio38_a_1", "gpio"),
226 AB8500_PIN_HOG("GPIO38_C17", in_pd),
228 AB8500_MUX_HOG("gpio39_a_1", "gpio"),
229 AB8500_PIN_HOG("GPIO39_E16", in_pd),
232 * pins 40 and 41 are muxed in MODCSLSDA
233 * configured INPUT PULL DOWN
235 AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
236 AB8500_PIN_HOG("GPIO40_T19", in_pd),
237 AB8500_PIN_HOG("GPIO41_U19", in_pd),
240 * pins 42 is muxed in GPIO
241 * configured INPUT PULL DOWN
243 AB8500_MUX_HOG("gpio42_a_1", "gpio"),
244 AB8500_PIN_HOG("GPIO42_U2", in_pd),
247 static struct pinctrl_map __initdata ab8505_pinmap[] = {
249 AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
250 AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
251 /* sysclkreq2 disable, mux in gpio configured in input pulldown */
252 AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
253 AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
255 /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
256 AB8505_MUX_HOG("gpio2_a_1", "gpio"),
257 AB8505_PIN_HOG("GPIO2_R5", in_pd),
260 AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
261 AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
262 /* sysclkreq4 disable, mux in gpio configured in input pulldown */
263 AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
264 AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
266 AB8505_MUX_HOG("gpio10_d_1", "gpio"),
267 AB8505_PIN_HOG("GPIO10_B16", in_pd),
269 AB8505_MUX_HOG("gpio11_d_1", "gpio"),
270 AB8505_PIN_HOG("GPIO11_B17", in_pd),
272 AB8505_MUX_HOG("gpio13_d_1", "gpio"),
273 AB8505_PIN_HOG("GPIO13_D17", in_nopull),
275 AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
276 AB8505_PIN_HOG("GPIO14_C16", in_pd),
278 AB8505_MUX_HOG("adi2_d_1", "adi2"),
279 AB8505_PIN_HOG("GPIO17_P2", in_pd),
280 AB8505_PIN_HOG("GPIO18_N3", in_pd),
281 AB8505_PIN_HOG("GPIO19_T1", in_pd),
282 AB8505_PIN_HOG("GPIO20_P3", in_pd),
284 AB8505_MUX_HOG("gpio34_a_1", "gpio"),
285 AB8505_PIN_HOG("GPIO34_H14", in_pd),
287 AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
288 AB8505_PIN_HOG("GPIO40_J15", in_pd),
289 AB8505_PIN_HOG("GPIO41_J14", in_pd),
291 AB8505_MUX_HOG("gpio50_d_1", "gpio"),
292 AB8505_PIN_HOG("GPIO50_L4", in_nopull),
294 AB8505_MUX_HOG("resethw_d_1", "resethw"),
295 AB8505_PIN_HOG("GPIO52_D16", in_pd),
297 AB8505_MUX_HOG("service_d_1", "service"),
298 AB8505_PIN_HOG("GPIO53_D15", in_pd),
301 static struct pinctrl_map __initdata snowball_pinmap[] = {
302 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
303 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
304 DB8500_PIN_HOG("GPIO145_C13", pd),
306 DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
307 /* Accelerometer/Magnetometer */
308 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
309 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
310 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
312 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
313 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
314 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
315 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
318 void __init mop500_pinmaps_init(void)
320 if (machine_is_u8520())
321 pinctrl_register_mappings(ab8505_pinmap,
322 ARRAY_SIZE(ab8505_pinmap));
324 pinctrl_register_mappings(ab8500_pinmap,
325 ARRAY_SIZE(ab8500_pinmap));
328 void __init snowball_pinmaps_init(void)
330 pinctrl_register_mappings(snowball_pinmap,
331 ARRAY_SIZE(snowball_pinmap));
332 pinctrl_register_mappings(ab8500_pinmap,
333 ARRAY_SIZE(ab8500_pinmap));
336 void __init hrefv60_pinmaps_init(void)
338 pinctrl_register_mappings(ab8500_pinmap,
339 ARRAY_SIZE(ab8500_pinmap));