arch/arm/mach-ux500/board-mop500-pins.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2010
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/bug.h>
  10 #include <linux/string.h>
  11 #include <linux/pinctrl/machine.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13 #include <linux/platform_data/pinctrl-nomadik.h>
  14
  15 #include <asm/mach-types.h>
  16
  17 #include "board-mop500.h"
  18
  19 enum custom_pin_cfg_t {
  20         PINS_FOR_DEFAULT,
  21         PINS_FOR_U9500,
  22 };
  23
  24 static enum custom_pin_cfg_t pinsfor;
  25
  26 /* These simply sets bias for pins */
  27 #define BIAS(a,b) static unsigned long a[] = { b }
  28
  29 BIAS(pd, PIN_PULL_DOWN);
  30 BIAS(in_nopull, PIN_INPUT_NOPULL);
  31 BIAS(in_pu, PIN_INPUT_PULLUP);
  32 BIAS(in_pd, PIN_INPUT_PULLDOWN);
  33 BIAS(out_lo, PIN_OUTPUT_LOW);
  34
  35 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
  36 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
  37 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
  38
  39 /* These also force them into GPIO mode */
  40 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
  41 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
  42 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  43 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
  44 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
  45 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
  46 /* Sleep modes */
  47 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  48         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  49 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
  50         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
  51 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
  52         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
  53 BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
  54         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
  55
  56 /* We use these to define hog settings that are always done on boot */
  57 #define DB8500_MUX_HOG(group,func) \
  58         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
  59 #define DB8500_PIN_HOG(pin,conf) \
  60         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
  61
  62 /* These are default states associated with device and changed runtime */
  63 #define DB8500_MUX(group,func,dev) \
  64         PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
  65 #define DB8500_PIN(pin,conf,dev) \
  66         PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
  67 #define DB8500_PIN_IDLE(pin, conf, dev) \
  68         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500",  \
  69                             pin, conf)
  70 #define DB8500_PIN_SLEEP(pin, conf, dev) \
  71         PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
  72                             pin, conf)
  73 #define DB8500_MUX_STATE(group, func, dev, state) \
  74         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
  75 #define DB8500_PIN_STATE(pin, conf, dev, state) \
  76         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
  77
  78 #define AB8500_MUX_HOG(group, func) \
  79         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
  80 #define AB8500_PIN_HOG(pin, conf) \
  81         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
  82
  83 #define AB8500_MUX_STATE(group, func, dev, state) \
  84         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
  85 #define AB8500_PIN_STATE(pin, conf, dev, state) \
  86         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
  87
  88 #define AB8505_MUX_HOG(group, func) \
  89         PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
  90 #define AB8505_PIN_HOG(pin, conf) \
  91         PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
  92
  93 #define AB8505_MUX_STATE(group, func, dev, state) \
  94         PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
  95 #define AB8505_PIN_STATE(pin, conf, dev, state) \
  96         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
  97
  98 static struct pinctrl_map __initdata ab8500_pinmap[] = {
  99         /* Sysclkreq2 */
 100         AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
 101         AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
 102         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 103         AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
 104         AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
 105
 106         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 107         AB8500_MUX_HOG("gpio2_a_1", "gpio"),
 108         AB8500_PIN_HOG("GPIO2_T9", in_pd),
 109
 110         /* Sysclkreq4 */
 111         AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 112         AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 113         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 114         AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 115         AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 116
 117         /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
 118         AB8500_MUX_HOG("gpio4_a_1", "gpio"),
 119         AB8500_PIN_HOG("GPIO4_W2", in_pd),
 120
 121         /*
 122          * pins 6,7,8 and 9 are muxed in YCBCR0123
 123          * configured in INPUT PULL UP
 124          */
 125         AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
 126         AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
 127         AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
 128         AB8500_PIN_HOG("GPIO8_W18", in_nopull),
 129         AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
 130
 131         /*
 132          * pins 10,11,12 and 13 are muxed in GPIO
 133          * configured in INPUT PULL DOWN
 134          */
 135         AB8500_MUX_HOG("gpio10_d_1", "gpio"),
 136         AB8500_PIN_HOG("GPIO10_U17", in_pd),
 137
 138         AB8500_MUX_HOG("gpio11_d_1", "gpio"),
 139         AB8500_PIN_HOG("GPIO11_AA18", in_pd),
 140
 141         AB8500_MUX_HOG("gpio12_d_1", "gpio"),
 142         AB8500_PIN_HOG("GPIO12_U16", in_pd),
 143
 144         AB8500_MUX_HOG("gpio13_d_1", "gpio"),
 145         AB8500_PIN_HOG("GPIO13_W17", in_pd),
 146
 147         /*
 148          * pins 14,15 are muxed in PWM1 and PWM2
 149          * configured in INPUT PULL DOWN
 150          */
 151         AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
 152         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 153
 154         AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
 155         AB8500_PIN_HOG("GPIO15_B17", in_pd),
 156
 157         /*
 158          * pins 16 is muxed in GPIO
 159          * configured in INPUT PULL DOWN
 160          */
 161         AB8500_MUX_HOG("gpio16_a_1", "gpio"),
 162         AB8500_PIN_HOG("GPIO14_F14", in_pd),
 163
 164         /*
 165          * pins 17,18,19 and 20 are muxed in AUDIO interface 1
 166          * configured in INPUT PULL DOWN
 167          */
 168         AB8500_MUX_HOG("adi1_d_1", "adi1"),
 169         AB8500_PIN_HOG("GPIO17_P5", in_pd),
 170         AB8500_PIN_HOG("GPIO18_R5", in_pd),
 171         AB8500_PIN_HOG("GPIO19_U5", in_pd),
 172         AB8500_PIN_HOG("GPIO20_T5", in_pd),
 173
 174         /*
 175          * pins 21,22 and 23 are muxed in USB UICC
 176          * configured in INPUT PULL DOWN
 177          */
 178         AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
 179         AB8500_PIN_HOG("GPIO21_H19", in_pd),
 180         AB8500_PIN_HOG("GPIO22_G20", in_pd),
 181         AB8500_PIN_HOG("GPIO23_G19", in_pd),
 182
 183         /*
 184          * pins 24,25 are muxed in GPIO
 185          * configured in INPUT PULL DOWN
 186          */
 187         AB8500_MUX_HOG("gpio24_a_1", "gpio"),
 188         AB8500_PIN_HOG("GPIO24_T14", in_pd),
 189
 190         AB8500_MUX_HOG("gpio25_a_1", "gpio"),
 191         AB8500_PIN_HOG("GPIO25_R16", in_pd),
 192
 193         /*
 194          * pins 26 is muxed in GPIO
 195          * configured in OUTPUT LOW
 196          */
 197         AB8500_MUX_HOG("gpio26_d_1", "gpio"),
 198         AB8500_PIN_HOG("GPIO26_M16", out_lo),
 199
 200         /*
 201          * pins 27,28 are muxed in DMIC12
 202          * configured in INPUT PULL DOWN
 203          */
 204         AB8500_MUX_HOG("dmic12_d_1", "dmic"),
 205         AB8500_PIN_HOG("GPIO27_J6", in_pd),
 206         AB8500_PIN_HOG("GPIO28_K6", in_pd),
 207
 208         /*
 209          * pins 29,30 are muxed in DMIC34
 210          * configured in INPUT PULL DOWN
 211          */
 212         AB8500_MUX_HOG("dmic34_d_1", "dmic"),
 213         AB8500_PIN_HOG("GPIO29_G6", in_pd),
 214         AB8500_PIN_HOG("GPIO30_H6", in_pd),
 215
 216         /*
 217          * pins 31,32 are muxed in DMIC56
 218          * configured in INPUT PULL DOWN
 219          */
 220         AB8500_MUX_HOG("dmic56_d_1", "dmic"),
 221         AB8500_PIN_HOG("GPIO31_F5", in_pd),
 222         AB8500_PIN_HOG("GPIO32_G5", in_pd),
 223
 224         /*
 225          * pins 34 is muxed in EXTCPENA
 226          * configured INPUT PULL DOWN
 227          */
 228         AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
 229         AB8500_PIN_HOG("GPIO34_R17", in_pd),
 230
 231         /*
 232          * pins 35 is muxed in GPIO
 233          * configured in OUTPUT LOW
 234          */
 235         AB8500_MUX_HOG("gpio35_d_1", "gpio"),
 236         AB8500_PIN_HOG("GPIO35_W15", in_pd),
 237
 238         /*
 239          * pins 36,37,38 and 39 are muxed in GPIO
 240          * configured in INPUT PULL DOWN
 241          */
 242         AB8500_MUX_HOG("gpio36_a_1", "gpio"),
 243         AB8500_PIN_HOG("GPIO36_A17", in_pd),
 244
 245         AB8500_MUX_HOG("gpio37_a_1", "gpio"),
 246         AB8500_PIN_HOG("GPIO37_E15", in_pd),
 247
 248         AB8500_MUX_HOG("gpio38_a_1", "gpio"),
 249         AB8500_PIN_HOG("GPIO38_C17", in_pd),
 250
 251         AB8500_MUX_HOG("gpio39_a_1", "gpio"),
 252         AB8500_PIN_HOG("GPIO39_E16", in_pd),
 253
 254         /*
 255          * pins 40 and 41 are muxed in MODCSLSDA
 256          * configured INPUT PULL DOWN
 257          */
 258         AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
 259         AB8500_PIN_HOG("GPIO40_T19", in_pd),
 260         AB8500_PIN_HOG("GPIO41_U19", in_pd),
 261
 262         /*
 263          * pins 42 is muxed in GPIO
 264          * configured INPUT PULL DOWN
 265          */
 266         AB8500_MUX_HOG("gpio42_a_1", "gpio"),
 267         AB8500_PIN_HOG("GPIO42_U2", in_pd),
 268 };
 269
 270 static struct pinctrl_map __initdata ab8505_pinmap[] = {
 271         /* Sysclkreq2 */
 272         AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
 273         AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
 274         /* sysclkreq2 disable, mux in gpio configured in input pulldown */
 275         AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
 276         AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
 277
 278         /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
 279         AB8505_MUX_HOG("gpio2_a_1", "gpio"),
 280         AB8505_PIN_HOG("GPIO2_R5", in_pd),
 281
 282         /* Sysclkreq4 */
 283         AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
 284         AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
 285         /* sysclkreq4 disable, mux in gpio configured in input pulldown */
 286         AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
 287         AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
 288
 289         AB8505_MUX_HOG("gpio10_d_1", "gpio"),
 290         AB8505_PIN_HOG("GPIO10_B16", in_pd),
 291
 292         AB8505_MUX_HOG("gpio11_d_1", "gpio"),
 293         AB8505_PIN_HOG("GPIO11_B17", in_pd),
 294
 295         AB8505_MUX_HOG("gpio13_d_1", "gpio"),
 296         AB8505_PIN_HOG("GPIO13_D17", in_nopull),
 297
 298         AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
 299         AB8505_PIN_HOG("GPIO14_C16", in_pd),
 300
 301         AB8505_MUX_HOG("adi2_d_1", "adi2"),
 302         AB8505_PIN_HOG("GPIO17_P2", in_pd),
 303         AB8505_PIN_HOG("GPIO18_N3", in_pd),
 304         AB8505_PIN_HOG("GPIO19_T1", in_pd),
 305         AB8505_PIN_HOG("GPIO20_P3", in_pd),
 306
 307         AB8505_MUX_HOG("gpio34_a_1", "gpio"),
 308         AB8505_PIN_HOG("GPIO34_H14", in_pd),
 309
 310         AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
 311         AB8505_PIN_HOG("GPIO40_J15", in_pd),
 312         AB8505_PIN_HOG("GPIO41_J14", in_pd),
 313
 314         AB8505_MUX_HOG("gpio50_d_1", "gpio"),
 315         AB8505_PIN_HOG("GPIO50_L4", in_nopull),
 316
 317         AB8505_MUX_HOG("resethw_d_1", "resethw"),
 318         AB8505_PIN_HOG("GPIO52_D16", in_pd),
 319
 320         AB8505_MUX_HOG("service_d_1", "service"),
 321         AB8505_PIN_HOG("GPIO53_D15", in_pd),
 322 };
 323
 324 /* Pin control settings */
 325 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
 326         /* ske default state */
 327         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 328         DB8500_PIN("GPIO153_B17", in_pd, "nmk-ske-keypad"), /* I7 */
 329         DB8500_PIN("GPIO154_C16", in_pd, "nmk-ske-keypad"), /* I6 */
 330         DB8500_PIN("GPIO155_C19", in_pd, "nmk-ske-keypad"), /* I5 */
 331         DB8500_PIN("GPIO156_C17", in_pd, "nmk-ske-keypad"), /* I4 */
 332         DB8500_PIN("GPIO161_D21", in_pd, "nmk-ske-keypad"), /* I3 */
 333         DB8500_PIN("GPIO162_D20", in_pd, "nmk-ske-keypad"), /* I2 */
 334         DB8500_PIN("GPIO163_C20", in_pd, "nmk-ske-keypad"), /* I1 */
 335         DB8500_PIN("GPIO164_B21", in_pd, "nmk-ske-keypad"), /* I0 */
 336         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 337         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 338         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 339         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 340         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 341         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 342         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 343         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 344         /* ske sleep state */
 345         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 346         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 347         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 348         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 349         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 350         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 351         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 352         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 353         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 354         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 355         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 356         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 357         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 358         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 359         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 360         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 361
 362         /* STM APE pins states */
 363         DB8500_MUX_STATE("stmape_c_1", "stmape",
 364                 "stm", "ape_mipi34"),
 365         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 366                 "stm", "ape_mipi34"), /* clk */
 367         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 368                 "stm", "ape_mipi34"), /* dat3 */
 369         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 370                 "stm", "ape_mipi34"), /* dat2 */
 371         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 372                 "stm", "ape_mipi34"), /* dat1 */
 373         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 374                 "stm", "ape_mipi34"), /* dat0 */
 375
 376         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 377                 "stm", "ape_mipi34_sleep"), /* clk */
 378         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 379                 "stm", "ape_mipi34_sleep"), /* dat3 */
 380         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 381                 "stm", "ape_mipi34_sleep"), /* dat2 */
 382         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 383                 "stm", "ape_mipi34_sleep"), /* dat1 */
 384         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 385                 "stm", "ape_mipi34_sleep"), /* dat0 */
 386
 387         DB8500_MUX_STATE("stmape_oc1_1", "stmape",
 388                 "stm", "ape_microsd"),
 389         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 390                 "stm", "ape_microsd"), /* clk */
 391         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 392                 "stm", "ape_microsd"), /* dat0 */
 393         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 394                 "stm", "ape_microsd"), /* dat1 */
 395         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 396                 "stm", "ape_microsd"), /* dat2 */
 397         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 398                 "stm", "ape_microsd"), /* dat3 */
 399
 400         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 401                 "stm", "ape_microsd_sleep"), /* clk */
 402         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 403                 "stm", "ape_microsd_sleep"), /* dat0 */
 404         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 405                 "stm", "ape_microsd_sleep"), /* dat1 */
 406         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 407                 "stm", "ape_microsd_sleep"), /* dat2 */
 408         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 409                 "stm", "ape_microsd_sleep"), /* dat3 */
 410
 411         /*  STM Modem pins states */
 412         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 413                 "stm", "mod_mipi34"),
 414         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 415                 "stm", "mod_mipi34"),
 416         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 417                 "stm", "mod_mipi34"),
 418         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 419                 "stm", "mod_mipi34"), /* clk */
 420         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 421                 "stm", "mod_mipi34"), /* dat3 */
 422         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 423                 "stm", "mod_mipi34"), /* dat2 */
 424         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 425                 "stm", "mod_mipi34"), /* dat1 */
 426         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 427                 "stm", "mod_mipi34"), /* dat0 */
 428         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 429                 "stm", "mod_mipi34"), /* uartmod rx */
 430         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 431                 "stm", "mod_mipi34"), /* uartmod tx */
 432
 433         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 434                 "stm", "mod_mipi34_sleep"), /* clk */
 435         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 436                 "stm", "mod_mipi34_sleep"), /* dat3 */
 437         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 438                 "stm", "mod_mipi34_sleep"), /* dat2 */
 439         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 440                 "stm", "mod_mipi34_sleep"), /* dat1 */
 441         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 442                 "stm", "mod_mipi34_sleep"), /* dat0 */
 443         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 444                 "stm", "mod_mipi34_sleep"), /* uartmod rx */
 445         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 446                 "stm", "mod_mipi34_sleep"), /* uartmod tx */
 447
 448         DB8500_MUX_STATE("stmmod_b_1", "stmmod",
 449                 "stm", "mod_microsd"),
 450         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 451                 "stm", "mod_microsd"),
 452         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 453                 "stm", "mod_microsd"),
 454         DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
 455                 "stm", "mod_microsd"), /* clk */
 456         DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
 457                 "stm", "mod_microsd"), /* dat0 */
 458         DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
 459                 "stm", "mod_microsd"), /* dat1 */
 460         DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
 461                 "stm", "mod_microsd"), /* dat2 */
 462         DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
 463                 "stm", "mod_microsd"), /* dat3 */
 464         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 465                 "stm", "mod_microsd"), /* uartmod rx */
 466         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 467                 "stm", "mod_microsd"), /* uartmod tx */
 468
 469         DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
 470                 "stm", "mod_microsd_sleep"), /* clk */
 471         DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
 472                 "stm", "mod_microsd_sleep"), /* dat0 */
 473         DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
 474                 "stm", "mod_microsd_sleep"), /* dat1 */
 475         DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
 476                 "stm", "mod_microsd_sleep"), /* dat2 */
 477         DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
 478                 "stm", "mod_microsd_sleep"), /* dat3 */
 479         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 480                 "stm", "mod_microsd_sleep"), /* uartmod rx */
 481         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 482                 "stm", "mod_microsd_sleep"), /* uartmod tx */
 483
 484         /*  STM dual Modem/APE pins state */
 485         DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
 486                 "stm", "mod_mipi34_ape_mipi60"),
 487         DB8500_MUX_STATE("stmape_c_2", "stmape",
 488                 "stm", "mod_mipi34_ape_mipi60"),
 489         DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
 490                 "stm", "mod_mipi34_ape_mipi60"),
 491         DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
 492                 "stm", "mod_mipi34_ape_mipi60"),
 493         DB8500_PIN_STATE("GPIO70_G5", in_nopull,
 494                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 495         DB8500_PIN_STATE("GPIO71_G4", in_nopull,
 496                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 497         DB8500_PIN_STATE("GPIO72_H4", in_nopull,
 498                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 499         DB8500_PIN_STATE("GPIO73_H3", in_nopull,
 500                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 501         DB8500_PIN_STATE("GPIO74_J3", in_nopull,
 502                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 503         DB8500_PIN_STATE("GPIO75_H2", in_pu,
 504                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
 505         DB8500_PIN_STATE("GPIO76_J2", out_lo,
 506                 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
 507         DB8500_PIN_STATE("GPIO155_C19", in_nopull,
 508                 "stm", "mod_mipi34_ape_mipi60"), /* clk */
 509         DB8500_PIN_STATE("GPIO156_C17", in_nopull,
 510                 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
 511         DB8500_PIN_STATE("GPIO157_A18", in_nopull,
 512                 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
 513         DB8500_PIN_STATE("GPIO158_C18", in_nopull,
 514                 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
 515         DB8500_PIN_STATE("GPIO159_B19", in_nopull,
 516                 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
 517
 518         DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
 519                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 520         DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
 521                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 522         DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
 523                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 524         DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
 525                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 526         DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
 527                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 528         DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
 529                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
 530         DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
 531                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
 532         DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
 533                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
 534         DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
 535                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
 536         DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
 537                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
 538         DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
 539                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
 540         DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
 541                 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
 542 };
 543
 544 /*
 545  * These are specifically for the MOP500 and HREFP (pre-v60) version of the
 546  * board, which utilized a TC35892 GPIO expander instead of using a lot of
 547  * on-chip pins as the HREFv60 and later does.
 548  */
 549 static struct pinctrl_map __initdata mop500_pinmap[] = {
 550         /*
 551          * XENON Flashgun on image processor GPIO (controlled from image
 552          * processor firmware), mux in these image processor GPIO lines 0
 553          * (XENON_FLASH_ID) and 1 (XENON_READY) on altfunction C and pull up
 554          * the pins.
 555          */
 556         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 557         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 558         DB8500_PIN_HOG("GPIO6_AF6", in_pu),
 559         DB8500_PIN_HOG("GPIO7_AG5", in_pu),
 560         /*
 561          * Runtime stuff: make it possible to mux in the SKE keypad
 562          * and bias the pins
 563          */
 564         /* ske default state */
 565         DB8500_MUX("kp_a_2", "kp", "nmk-ske-keypad"),
 566         DB8500_PIN("GPIO153_B17", in_pu, "nmk-ske-keypad"), /* I7 */
 567         DB8500_PIN("GPIO154_C16", in_pu, "nmk-ske-keypad"), /* I6 */
 568         DB8500_PIN("GPIO155_C19", in_pu, "nmk-ske-keypad"), /* I5 */
 569         DB8500_PIN("GPIO156_C17", in_pu, "nmk-ske-keypad"), /* I4 */
 570         DB8500_PIN("GPIO161_D21", in_pu, "nmk-ske-keypad"), /* I3 */
 571         DB8500_PIN("GPIO162_D20", in_pu, "nmk-ske-keypad"), /* I2 */
 572         DB8500_PIN("GPIO163_C20", in_pu, "nmk-ske-keypad"), /* I1 */
 573         DB8500_PIN("GPIO164_B21", in_pu, "nmk-ske-keypad"), /* I0 */
 574         DB8500_PIN("GPIO157_A18", out_lo, "nmk-ske-keypad"), /* O7 */
 575         DB8500_PIN("GPIO158_C18", out_lo, "nmk-ske-keypad"), /* O6 */
 576         DB8500_PIN("GPIO159_B19", out_lo, "nmk-ske-keypad"), /* O5 */
 577         DB8500_PIN("GPIO160_B20", out_lo, "nmk-ske-keypad"), /* O4 */
 578         DB8500_PIN("GPIO165_C21", out_lo, "nmk-ske-keypad"), /* O3 */
 579         DB8500_PIN("GPIO166_A22", out_lo, "nmk-ske-keypad"), /* O2 */
 580         DB8500_PIN("GPIO167_B24", out_lo, "nmk-ske-keypad"), /* O1 */
 581         DB8500_PIN("GPIO168_C22", out_lo, "nmk-ske-keypad"), /* O0 */
 582         /* ske sleep state */
 583         DB8500_PIN_SLEEP("GPIO153_B17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I7 */
 584         DB8500_PIN_SLEEP("GPIO154_C16", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I6 */
 585         DB8500_PIN_SLEEP("GPIO155_C19", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I5 */
 586         DB8500_PIN_SLEEP("GPIO156_C17", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I4 */
 587         DB8500_PIN_SLEEP("GPIO161_D21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I3 */
 588         DB8500_PIN_SLEEP("GPIO162_D20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I2 */
 589         DB8500_PIN_SLEEP("GPIO163_C20", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I1 */
 590         DB8500_PIN_SLEEP("GPIO164_B21", slpm_in_pu_wkup_pdis_en, "nmk-ske-keypad"), /* I0 */
 591         DB8500_PIN_SLEEP("GPIO157_A18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O7 */
 592         DB8500_PIN_SLEEP("GPIO158_C18", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O6 */
 593         DB8500_PIN_SLEEP("GPIO159_B19", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O5 */
 594         DB8500_PIN_SLEEP("GPIO160_B20", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O4 */
 595         DB8500_PIN_SLEEP("GPIO165_C21", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O3 */
 596         DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */
 597         DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */
 598         DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */
 599 };
 600
 601 /*
 602  * The HREFv60 series of platforms is using available pins on the DB8500
 603  * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
 604  * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
 605  */
 606 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
 607         /* Drive WLAN_ENA low */
 608         DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
 609         /*
 610          * XENON Flashgun on image processor GPIO (controlled from image
 611          * processor firmware), mux in these image processor GPIO lines 0
 612          * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
 613          * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
 614          * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
 615          */
 616         DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
 617         DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
 618         DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
 619         DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
 620         DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
 621         DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
 622         DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
 623         /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
 624         DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
 625         DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
 626         /*
 627          * Display Interface 1 uses GPIO 65 for RST (reset).
 628          * Display Interface 2 uses GPIO 66 for RST (reset).
 629          * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
 630          */
 631         DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
 632         DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
 633         /*
 634          * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
 635          * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
 636          * reset signals low.
 637          */
 638         DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
 639         DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
 640         DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
 641         /*
 642          * Drive D19-D23 for the ETM PTM trace interface low,
 643          * (presumably pins are unconnected therefore grounded here,
 644          * the "other alt C1" setting enables these pins)
 645          */
 646         DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
 647         DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
 648         DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
 649         DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
 650         DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
 651         /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
 652         DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
 653         DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
 654         /* NFC ENA and RESET to low, pulldown IRQ line */
 655         DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
 656         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
 657         DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
 658         /*
 659          * SKE keyboard partly on alt A and partly on "Other alt C1"
 660          * Driver KP_O1,2,3,6,7 low and pull up KP_I 0,2,3 for three
 661          * rows of 6 keys, then pull up force sensing interrup and
 662          * drive reset and force sensing WU low.
 663          */
 664         DB8500_MUX_HOG("kp_a_1", "kp"),
 665         DB8500_MUX_HOG("kp_oc1_1", "kp"),
 666         DB8500_PIN_HOG("GPIO90_A3", out_lo), /* KP_O1 */
 667         DB8500_PIN_HOG("GPIO87_B3", out_lo), /* KP_O2 */
 668         DB8500_PIN_HOG("GPIO86_C6", out_lo), /* KP_O3 */
 669         DB8500_PIN_HOG("GPIO96_D8", out_lo), /* KP_O6 */
 670         DB8500_PIN_HOG("GPIO94_D7", out_lo), /* KP_O7 */
 671         DB8500_PIN_HOG("GPIO93_B7", in_pu), /* KP_I0 */
 672         DB8500_PIN_HOG("GPIO89_E6", in_pu), /* KP_I2 */
 673         DB8500_PIN_HOG("GPIO88_C4", in_pu), /* KP_I3 */
 674         DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
 675         DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
 676         DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
 677         /* DiPro Sensor interrupt */
 678         DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
 679         /* Audio Amplifier HF enable */
 680         DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
 681         /* GBF interface, pull low to reset state */
 682         DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
 683         /* MSP : HDTV INTERFACE GPIO line */
 684         DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
 685         /* Accelerometer interrupt lines */
 686         DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
 687         DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
 688         /*
 689          * Runtime stuff
 690          * Pull up/down of some sensor GPIO pins, for proximity, HAL sensor
 691          * etc.
 692          */
 693         DB8500_PIN("GPIO217_AH12", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 694         DB8500_PIN("GPIO145_C13", gpio_in_pd_slpm_gpio_nopull, "gpio-keys.0"),
 695         DB8500_PIN("GPIO139_C9", gpio_in_pu_slpm_gpio_nopull, "gpio-keys.0"),
 696 };
 697
 698 static struct pinctrl_map __initdata u9500_pinmap[] = {
 699         /* WLAN_IRQ line */
 700         DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
 701         /* HSI */
 702         DB8500_MUX_HOG("hsir_a_1", "hsi"),
 703         DB8500_MUX_HOG("hsit_a_2", "hsi"),
 704         DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
 705         DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
 706         DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
 707         DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
 708         DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
 709         DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
 710         DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
 711         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
 712 };
 713
 714 static struct pinctrl_map __initdata u8500_pinmap[] = {
 715         DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
 716         DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
 717 };
 718
 719 static struct pinctrl_map __initdata snowball_pinmap[] = {
 720         /* Mux in SSP0 connected to AB8500, pull down RXD pin */
 721         DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
 722         DB8500_PIN_HOG("GPIO145_C13", pd),
 723         /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
 724         DB8500_MUX_HOG("sm_b_1", "sm"),
 725         /* User LED */
 726         DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
 727         /* Drive RSTn_LAN high */
 728         DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
 729         /*  Accelerometer/Magnetometer */
 730         DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
 731         DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
 732         DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
 733         /* WLAN/GBF */
 734         DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
 735         DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
 736         DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
 737         DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
 738 };
 739
 740 /*
 741  * passing "pinsfor=" in kernel cmdline allows for custom
 742  * configuration of GPIOs on u8500 derived boards.
 743  */
 744 static int __init early_pinsfor(char *p)
 745 {
 746         pinsfor = PINS_FOR_DEFAULT;
 747
 748         if (strcmp(p, "u9500-21") == 0)
 749                 pinsfor = PINS_FOR_U9500;
 750
 751         return 0;
 752 }
 753 early_param("pinsfor", early_pinsfor);
 754
 755 int pins_for_u9500(void)
 756 {
 757         if (pinsfor == PINS_FOR_U9500)
 758                 return 1;
 759
 760         return 0;
 761 }
 762
 763 static void __init mop500_href_family_pinmaps_init(void)
 764 {
 765         switch (pinsfor) {
 766         case PINS_FOR_U9500:
 767                 pinctrl_register_mappings(u9500_pinmap,
 768                                           ARRAY_SIZE(u9500_pinmap));
 769                 break;
 770         case PINS_FOR_DEFAULT:
 771                 pinctrl_register_mappings(u8500_pinmap,
 772                                           ARRAY_SIZE(u8500_pinmap));
 773         default:
 774                 break;
 775         }
 776 }
 777
 778 void __init mop500_pinmaps_init(void)
 779 {
 780         pinctrl_register_mappings(mop500_family_pinmap,
 781                                   ARRAY_SIZE(mop500_family_pinmap));
 782         pinctrl_register_mappings(mop500_pinmap,
 783                                   ARRAY_SIZE(mop500_pinmap));
 784         mop500_href_family_pinmaps_init();
 785         if (machine_is_u8520())
 786                 pinctrl_register_mappings(ab8505_pinmap,
 787                                           ARRAY_SIZE(ab8505_pinmap));
 788         else
 789                 pinctrl_register_mappings(ab8500_pinmap,
 790                                           ARRAY_SIZE(ab8500_pinmap));
 791 }
 792
 793 void __init snowball_pinmaps_init(void)
 794 {
 795         pinctrl_register_mappings(mop500_family_pinmap,
 796                                   ARRAY_SIZE(mop500_family_pinmap));
 797         pinctrl_register_mappings(snowball_pinmap,
 798                                   ARRAY_SIZE(snowball_pinmap));
 799         pinctrl_register_mappings(u8500_pinmap,
 800                                   ARRAY_SIZE(u8500_pinmap));
 801         pinctrl_register_mappings(ab8500_pinmap,
 802                                   ARRAY_SIZE(ab8500_pinmap));
 803 }
 804
 805 void __init hrefv60_pinmaps_init(void)
 806 {
 807         pinctrl_register_mappings(mop500_family_pinmap,
 808                                   ARRAY_SIZE(mop500_family_pinmap));
 809         pinctrl_register_mappings(hrefv60_pinmap,
 810                                   ARRAY_SIZE(hrefv60_pinmap));
 811         mop500_href_family_pinmaps_init();
 812         pinctrl_register_mappings(ab8500_pinmap,
 813                                   ARRAY_SIZE(ab8500_pinmap));
 814 }