2 * Copyright (C) ST-Ericsson SA 2010
4 * License terms: GNU General Public License (GPL) version 2
7 #include <linux/kernel.h>
8 #include <linux/init.h>
10 #include <linux/string.h>
11 #include <linux/pinctrl/machine.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/platform_data/pinctrl-nomadik.h>
15 #include <asm/mach-types.h>
17 #include "board-mop500.h"
19 enum custom_pin_cfg_t {
24 static enum custom_pin_cfg_t pinsfor;
26 /* These simply sets bias for pins */
27 #define BIAS(a,b) static unsigned long a[] = { b }
29 BIAS(pd, PIN_PULL_DOWN);
30 BIAS(in_pu, PIN_INPUT_PULLUP);
31 BIAS(in_pd, PIN_INPUT_PULLDOWN);
32 BIAS(out_lo, PIN_OUTPUT_LOW);
34 BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
35 BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
36 BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
38 /* These also force them into GPIO mode */
39 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
40 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
41 BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
42 BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
43 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
44 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
46 /* We use these to define hog settings that are always done on boot */
47 #define DB8500_MUX_HOG(group,func) \
48 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
49 #define DB8500_PIN_HOG(pin,conf) \
50 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
52 /* These are default states associated with device and changed runtime */
53 #define DB8500_MUX(group,func,dev) \
54 PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
55 #define DB8500_PIN(pin,conf,dev) \
56 PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
57 #define DB8500_PIN_IDLE(pin, conf, dev) \
58 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_IDLE, "pinctrl-db8500", \
60 #define DB8500_PIN_SLEEP(pin, conf, dev) \
61 PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
63 #define DB8500_MUX_STATE(group, func, dev, state) \
64 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func)
65 #define DB8500_PIN_STATE(pin, conf, dev, state) \
66 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
68 #define AB8500_MUX_HOG(group, func) \
69 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
70 #define AB8500_PIN_HOG(pin, conf) \
71 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
73 #define AB8500_MUX_STATE(group, func, dev, state) \
74 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
75 #define AB8500_PIN_STATE(pin, conf, dev, state) \
76 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
78 #define AB8505_MUX_HOG(group, func) \
79 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
80 #define AB8505_PIN_HOG(pin, conf) \
81 PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
83 #define AB8505_MUX_STATE(group, func, dev, state) \
84 PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
85 #define AB8505_PIN_STATE(pin, conf, dev, state) \
86 PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
88 static struct pinctrl_map __initdata ab8500_pinmap[] = {
90 AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
91 AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
92 /* sysclkreq2 disable, mux in gpio configured in input pulldown */
93 AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
94 AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
96 /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
97 AB8500_MUX_HOG("gpio2_a_1", "gpio"),
98 AB8500_PIN_HOG("GPIO2_T9", in_pd),
101 AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
102 AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
103 /* sysclkreq4 disable, mux in gpio configured in input pulldown */
104 AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
105 AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
107 /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
108 AB8500_MUX_HOG("gpio4_a_1", "gpio"),
109 AB8500_PIN_HOG("GPIO4_W2", in_pd),
112 * pins 6,7,8 and 9 are muxed in YCBCR0123
113 * configured in INPUT PULL UP
115 AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
116 AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
117 AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
118 AB8500_PIN_HOG("GPIO8_W18", in_nopull),
119 AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
122 * pins 10,11,12 and 13 are muxed in GPIO
123 * configured in INPUT PULL DOWN
125 AB8500_MUX_HOG("gpio10_d_1", "gpio"),
126 AB8500_PIN_HOG("GPIO10_U17", in_pd),
128 AB8500_MUX_HOG("gpio11_d_1", "gpio"),
129 AB8500_PIN_HOG("GPIO11_AA18", in_pd),
131 AB8500_MUX_HOG("gpio12_d_1", "gpio"),
132 AB8500_PIN_HOG("GPIO12_U16", in_pd),
134 AB8500_MUX_HOG("gpio13_d_1", "gpio"),
135 AB8500_PIN_HOG("GPIO13_W17", in_pd),
138 * pins 14,15 are muxed in PWM1 and PWM2
139 * configured in INPUT PULL DOWN
141 AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
142 AB8500_PIN_HOG("GPIO14_F14", in_pd),
144 AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
145 AB8500_PIN_HOG("GPIO15_B17", in_pd),
148 * pins 16 is muxed in GPIO
149 * configured in INPUT PULL DOWN
151 AB8500_MUX_HOG("gpio16_a_1", "gpio"),
152 AB8500_PIN_HOG("GPIO14_F14", in_pd),
155 * pins 17,18,19 and 20 are muxed in AUDIO interface 1
156 * configured in INPUT PULL DOWN
158 AB8500_MUX_HOG("adi1_d_1", "adi1"),
159 AB8500_PIN_HOG("GPIO17_P5", in_pd),
160 AB8500_PIN_HOG("GPIO18_R5", in_pd),
161 AB8500_PIN_HOG("GPIO19_U5", in_pd),
162 AB8500_PIN_HOG("GPIO20_T5", in_pd),
165 * pins 21,22 and 23 are muxed in USB UICC
166 * configured in INPUT PULL DOWN
168 AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
169 AB8500_PIN_HOG("GPIO21_H19", in_pd),
170 AB8500_PIN_HOG("GPIO22_G20", in_pd),
171 AB8500_PIN_HOG("GPIO23_G19", in_pd),
174 * pins 24,25 are muxed in GPIO
175 * configured in INPUT PULL DOWN
177 AB8500_MUX_HOG("gpio24_a_1", "gpio"),
178 AB8500_PIN_HOG("GPIO24_T14", in_pd),
180 AB8500_MUX_HOG("gpio25_a_1", "gpio"),
181 AB8500_PIN_HOG("GPIO25_R16", in_pd),
184 * pins 26 is muxed in GPIO
185 * configured in OUTPUT LOW
187 AB8500_MUX_HOG("gpio26_d_1", "gpio"),
188 AB8500_PIN_HOG("GPIO26_M16", out_lo),
191 * pins 27,28 are muxed in DMIC12
192 * configured in INPUT PULL DOWN
194 AB8500_MUX_HOG("dmic12_d_1", "dmic"),
195 AB8500_PIN_HOG("GPIO27_J6", in_pd),
196 AB8500_PIN_HOG("GPIO28_K6", in_pd),
199 * pins 29,30 are muxed in DMIC34
200 * configured in INPUT PULL DOWN
202 AB8500_MUX_HOG("dmic34_d_1", "dmic"),
203 AB8500_PIN_HOG("GPIO29_G6", in_pd),
204 AB8500_PIN_HOG("GPIO30_H6", in_pd),
207 * pins 31,32 are muxed in DMIC56
208 * configured in INPUT PULL DOWN
210 AB8500_MUX_HOG("dmic56_d_1", "dmic"),
211 AB8500_PIN_HOG("GPIO31_F5", in_pd),
212 AB8500_PIN_HOG("GPIO32_G5", in_pd),
215 * pins 34 is muxed in EXTCPENA
216 * configured INPUT PULL DOWN
218 AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
219 AB8500_PIN_HOG("GPIO34_R17", in_pd),
222 * pins 35 is muxed in GPIO
223 * configured in OUTPUT LOW
225 AB8500_MUX_HOG("gpio35_d_1", "gpio"),
226 AB8500_PIN_HOG("GPIO35_W15", in_pd),
229 * pins 36,37,38 and 39 are muxed in GPIO
230 * configured in INPUT PULL DOWN
232 AB8500_MUX_HOG("gpio36_a_1", "gpio"),
233 AB8500_PIN_HOG("GPIO36_A17", in_pd),
235 AB8500_MUX_HOG("gpio37_a_1", "gpio"),
236 AB8500_PIN_HOG("GPIO37_E15", in_pd),
238 AB8500_MUX_HOG("gpio38_a_1", "gpio"),
239 AB8500_PIN_HOG("GPIO38_C17", in_pd),
241 AB8500_MUX_HOG("gpio39_a_1", "gpio"),
242 AB8500_PIN_HOG("GPIO39_E16", in_pd),
245 * pins 40 and 41 are muxed in MODCSLSDA
246 * configured INPUT PULL DOWN
248 AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
249 AB8500_PIN_HOG("GPIO40_T19", in_pd),
250 AB8500_PIN_HOG("GPIO41_U19", in_pd),
253 * pins 42 is muxed in GPIO
254 * configured INPUT PULL DOWN
256 AB8500_MUX_HOG("gpio42_a_1", "gpio"),
257 AB8500_PIN_HOG("GPIO42_U2", in_pd),
260 static struct pinctrl_map __initdata ab8505_pinmap[] = {
262 AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
263 AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
264 /* sysclkreq2 disable, mux in gpio configured in input pulldown */
265 AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
266 AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
268 /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
269 AB8505_MUX_HOG("gpio2_a_1", "gpio"),
270 AB8505_PIN_HOG("GPIO2_R5", in_pd),
273 AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
274 AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
275 /* sysclkreq4 disable, mux in gpio configured in input pulldown */
276 AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
277 AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
279 AB8505_MUX_HOG("gpio10_d_1", "gpio"),
280 AB8505_PIN_HOG("GPIO10_B16", in_pd),
282 AB8505_MUX_HOG("gpio11_d_1", "gpio"),
283 AB8505_PIN_HOG("GPIO11_B17", in_pd),
285 AB8505_MUX_HOG("gpio13_d_1", "gpio"),
286 AB8505_PIN_HOG("GPIO13_D17", in_nopull),
288 AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
289 AB8505_PIN_HOG("GPIO14_C16", in_pd),
291 AB8505_MUX_HOG("adi2_d_1", "adi2"),
292 AB8505_PIN_HOG("GPIO17_P2", in_pd),
293 AB8505_PIN_HOG("GPIO18_N3", in_pd),
294 AB8505_PIN_HOG("GPIO19_T1", in_pd),
295 AB8505_PIN_HOG("GPIO20_P3", in_pd),
297 AB8505_MUX_HOG("gpio34_a_1", "gpio"),
298 AB8505_PIN_HOG("GPIO34_H14", in_pd),
300 AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
301 AB8505_PIN_HOG("GPIO40_J15", in_pd),
302 AB8505_PIN_HOG("GPIO41_J14", in_pd),
304 AB8505_MUX_HOG("gpio50_d_1", "gpio"),
305 AB8505_PIN_HOG("GPIO50_L4", in_nopull),
307 AB8505_MUX_HOG("resethw_d_1", "resethw"),
308 AB8505_PIN_HOG("GPIO52_D16", in_pd),
310 AB8505_MUX_HOG("service_d_1", "service"),
311 AB8505_PIN_HOG("GPIO53_D15", in_pd),
315 * The HREFv60 series of platforms is using available pins on the DB8500
316 * insteaf of the Toshiba I2C GPIO expander, reusing some pins like the SSP0
317 * and SSP1 ports (previously connected to the AB8500) as generic GPIO lines.
319 static struct pinctrl_map __initdata hrefv60_pinmap[] = {
320 /* Drive WLAN_ENA low */
321 DB8500_PIN_HOG("GPIO85_D5", gpio_out_lo), /* WLAN_ENA */
323 * XENON Flashgun on image processor GPIO (controlled from image
324 * processor firmware), mux in these image processor GPIO lines 0
325 * (XENON_FLASH_ID), 1 (XENON_READY) and there is an assistant
326 * LED on IP GPIO 4 (XENON_EN2) on altfunction C, that need bias
327 * from GPIO21 so pull up 0, 1 and drive 4 and GPIO21 low as output.
329 DB8500_MUX_HOG("ipgpio0_c_1", "ipgpio"),
330 DB8500_MUX_HOG("ipgpio1_c_1", "ipgpio"),
331 DB8500_MUX_HOG("ipgpio4_c_1", "ipgpio"),
332 DB8500_PIN_HOG("GPIO6_AF6", in_pu), /* XENON_FLASH_ID */
333 DB8500_PIN_HOG("GPIO7_AG5", in_pu), /* XENON_READY */
334 DB8500_PIN_HOG("GPIO21_AB3", gpio_out_lo), /* XENON_EN1 */
335 DB8500_PIN_HOG("GPIO64_F3", out_lo), /* XENON_EN2 */
336 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
337 DB8500_PIN_HOG("GPIO31_V3", gpio_in_pu), /* EN1 */
338 DB8500_PIN_HOG("GPIO32_V2", gpio_in_pd), /* DRDY */
340 * Display Interface 1 uses GPIO 65 for RST (reset).
341 * Display Interface 2 uses GPIO 66 for RST (reset).
342 * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset)
344 DB8500_PIN_HOG("GPIO65_F1", gpio_out_hi), /* DISP1 NO RST */
345 DB8500_PIN_HOG("GPIO66_G3", gpio_out_lo), /* DISP2 RST */
347 * Touch screen uses GPIO 143 for RST1, GPIO 146 for RST2 and
348 * GPIO 67 for interrupts. Pull-up the IRQ line and drive both
351 DB8500_PIN_HOG("GPIO143_D12", gpio_out_lo), /* TOUCH_RST1 */
352 DB8500_PIN_HOG("GPIO67_G2", gpio_in_pu), /* TOUCH_INT2 */
353 DB8500_PIN_HOG("GPIO146_D13", gpio_out_lo), /* TOUCH_RST2 */
355 * Drive D19-D23 for the ETM PTM trace interface low,
356 * (presumably pins are unconnected therefore grounded here,
357 * the "other alt C1" setting enables these pins)
359 DB8500_PIN_HOG("GPIO70_G5", gpio_out_lo),
360 DB8500_PIN_HOG("GPIO71_G4", gpio_out_lo),
361 DB8500_PIN_HOG("GPIO72_H4", gpio_out_lo),
362 DB8500_PIN_HOG("GPIO73_H3", gpio_out_lo),
363 DB8500_PIN_HOG("GPIO74_J3", gpio_out_lo),
364 /* NAHJ CTRL on GPIO 76 to low, CTRL_INV on GPIO216 to high */
365 DB8500_PIN_HOG("GPIO76_J2", gpio_out_lo), /* CTRL */
366 DB8500_PIN_HOG("GPIO216_AG12", gpio_out_hi), /* CTRL_INV */
367 /* NFC ENA and RESET to low, pulldown IRQ line */
368 DB8500_PIN_HOG("GPIO77_H1", gpio_out_lo), /* NFC_ENA */
369 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pd), /* NFC_IRQ */
370 DB8500_PIN_HOG("GPIO142_C11", gpio_out_lo), /* NFC_RESET */
371 DB8500_PIN_HOG("GPIO91_B6", gpio_in_pu), /* FORCE_SENSING_INT */
372 DB8500_PIN_HOG("GPIO92_D6", gpio_out_lo), /* FORCE_SENSING_RST */
373 DB8500_PIN_HOG("GPIO97_D9", gpio_out_lo), /* FORCE_SENSING_WU */
374 /* DiPro Sensor interrupt */
375 DB8500_PIN_HOG("GPIO139_C9", gpio_in_pu), /* DIPRO_INT */
376 /* Audio Amplifier HF enable */
377 DB8500_PIN_HOG("GPIO149_B14", gpio_out_hi), /* VAUDIO_HF_EN, enable MAX8968 */
378 /* GBF interface, pull low to reset state */
379 DB8500_PIN_HOG("GPIO171_D23", gpio_out_lo), /* GBF_ENA_RESET */
380 /* MSP : HDTV INTERFACE GPIO line */
381 DB8500_PIN_HOG("GPIO192_AJ27", gpio_in_pd),
382 /* Accelerometer interrupt lines */
383 DB8500_PIN_HOG("GPIO82_C1", gpio_in_pu), /* ACC_INT1 */
384 DB8500_PIN_HOG("GPIO83_D3", gpio_in_pu), /* ACC_INT2 */
387 static struct pinctrl_map __initdata u9500_pinmap[] = {
389 DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
391 DB8500_MUX_HOG("hsir_a_1", "hsi"),
392 DB8500_MUX_HOG("hsit_a_2", "hsi"),
393 DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
394 DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
395 DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
396 DB8500_PIN_HOG("GPIO222_AJ9", out_lo), /* TX FLA0 */
397 DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
398 DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
399 DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
400 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
403 static struct pinctrl_map __initdata u8500_pinmap[] = {
404 DB8500_PIN_HOG("GPIO226_AF8", gpio_out_lo), /* WLAN_PMU_EN */
405 DB8500_PIN_HOG("GPIO4_AH6", gpio_in_pu), /* WLAN_IRQ */
408 static struct pinctrl_map __initdata snowball_pinmap[] = {
409 /* Mux in SSP0 connected to AB8500, pull down RXD pin */
410 DB8500_MUX_HOG("ssp0_a_1", "ssp0"),
411 DB8500_PIN_HOG("GPIO145_C13", pd),
412 /* Mux in "SM" which is used for the SMSC911x Ethernet adapter */
413 DB8500_MUX_HOG("sm_b_1", "sm"),
415 DB8500_PIN_HOG("GPIO142_C11", gpio_out_hi),
416 /* Drive RSTn_LAN high */
417 DB8500_PIN_HOG("GPIO141_C12", gpio_out_hi),
418 /* Accelerometer/Magnetometer */
419 DB8500_PIN_HOG("GPIO163_C20", gpio_in_pu), /* ACCEL_IRQ1 */
420 DB8500_PIN_HOG("GPIO164_B21", gpio_in_pu), /* ACCEL_IRQ2 */
421 DB8500_PIN_HOG("GPIO165_C21", gpio_in_pu), /* MAG_DRDY */
423 DB8500_PIN_HOG("GPIO161_D21", gpio_out_lo), /* WLAN_PMU_EN */
424 DB8500_PIN_HOG("GPIO171_D23", gpio_out_hi), /* GBF_ENA */
425 DB8500_PIN_HOG("GPIO215_AH13", gpio_out_lo), /* WLAN_ENA */
426 DB8500_PIN_HOG("GPIO216_AG12", gpio_in_pu), /* WLAN_IRQ */
430 * passing "pinsfor=" in kernel cmdline allows for custom
431 * configuration of GPIOs on u8500 derived boards.
433 static int __init early_pinsfor(char *p)
435 pinsfor = PINS_FOR_DEFAULT;
437 if (strcmp(p, "u9500-21") == 0)
438 pinsfor = PINS_FOR_U9500;
442 early_param("pinsfor", early_pinsfor);
444 int pins_for_u9500(void)
446 if (pinsfor == PINS_FOR_U9500)
452 static void __init mop500_href_family_pinmaps_init(void)
456 pinctrl_register_mappings(u9500_pinmap,
457 ARRAY_SIZE(u9500_pinmap));
459 case PINS_FOR_DEFAULT:
460 pinctrl_register_mappings(u8500_pinmap,
461 ARRAY_SIZE(u8500_pinmap));
467 void __init mop500_pinmaps_init(void)
469 mop500_href_family_pinmaps_init();
470 if (machine_is_u8520())
471 pinctrl_register_mappings(ab8505_pinmap,
472 ARRAY_SIZE(ab8505_pinmap));
474 pinctrl_register_mappings(ab8500_pinmap,
475 ARRAY_SIZE(ab8500_pinmap));
478 void __init snowball_pinmaps_init(void)
480 pinctrl_register_mappings(snowball_pinmap,
481 ARRAY_SIZE(snowball_pinmap));
482 pinctrl_register_mappings(u8500_pinmap,
483 ARRAY_SIZE(u8500_pinmap));
484 pinctrl_register_mappings(ab8500_pinmap,
485 ARRAY_SIZE(ab8500_pinmap));
488 void __init hrefv60_pinmaps_init(void)
490 pinctrl_register_mappings(hrefv60_pinmap,
491 ARRAY_SIZE(hrefv60_pinmap));
492 mop500_href_family_pinmaps_init();
493 pinctrl_register_mappings(ab8500_pinmap,
494 ARRAY_SIZE(ab8500_pinmap));