arch/arm/mach-uniphier/sbc/sbc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2011-2015 Panasonic Corporation
   4  * Copyright (C) 2015-2017 Socionext Inc.
   5  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   6  */
   7
   8 #include <linux/io.h>
   9 #include <asm/global_data.h>
  10
  11 #include "../init.h"
  12 #include "sbc-regs.h"
  13
  14 /* slower but LED works */
  15 #define SBCTRL0_SAVEPIN_PERI_VALUE      0x55450000
  16 #define SBCTRL1_SAVEPIN_PERI_VALUE      0x07168d00
  17 #define SBCTRL2_SAVEPIN_PERI_VALUE      0x34000009
  18 #define SBCTRL4_SAVEPIN_PERI_VALUE      0x02110110
  19
  20 /* faster but LED does not work */
  21 #define SBCTRL0_SAVEPIN_MEM_VALUE       0x55450000
  22 #define SBCTRL1_SAVEPIN_MEM_VALUE       0x06057700
  23 #define SBCTRL2_SAVEPIN_MEM_VALUE       0x34000009
  24 #define SBCTRL4_SAVEPIN_MEM_VALUE       0x02110210
  25
  26 int uniphier_sbc_is_enabled(void)
  27 {
  28         DECLARE_GLOBAL_DATA_PTR;
  29         const void *fdt = gd->fdt_blob;
  30         int offset;
  31
  32         offset = fdt_node_offset_by_compatible(fdt, 0,
  33                                                "socionext,uniphier-system-bus");
  34         if (offset < 0)
  35                 return 0;
  36
  37         return fdtdec_get_is_enabled(fdt, offset);
  38 }
  39
  40 void uniphier_sbc_init_savepin(void)
  41 {
  42         /*
  43          * Only CS1 is connected to support card.
  44          * BKSZ[1:0] should be set to "01".
  45          */
  46         writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
  47         writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
  48         writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
  49         writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
  50
  51         if (uniphier_sbc_boot_is_swapped()) {
  52                 /*
  53                  * Boot Swap On: boot from external NOR/SRAM
  54                  * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  55                  *
  56                  * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  57                  * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  58                  */
  59                 writel(0x0000bc01, SBBASE0);
  60         } else {
  61                 /*
  62                  * Boot Swap Off: boot from mask ROM
  63                  * 0x40000000-0x41ffffff: mask ROM
  64                  * 0x42000000-0x43efffff: memory bank (31MB)
  65                  * 0x43f00000-0x43ffffff: peripherals (1MB)
  66                  */
  67                 writel(0x0000be01, SBBASE0); /* dummy */
  68                 writel(0x0200be01, SBBASE1);
  69         }
  70 }