arch/arm/mach-uniphier/pll/pll-init-pro4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10
  11 #include "../init.h"
  12 #include "../sc-regs.h"
  13 #include "../sg-regs.h"
  14
  15 #undef DPLL_SSC_RATE_1PER
  16
  17 static int dpll_init(unsigned int dram_freq)
  18 {
  19         u32 tmp;
  20
  21         /*
  22          * Set Frequency
  23          * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
  24          * to FOUT ( DPLLCTRL.bit[29:20] )
  25          */
  26         tmp = readl(SC_DPLLCTRL);
  27         tmp &= ~(0x000f0000);
  28         switch (dram_freq) {
  29         case 1333:
  30                 tmp |= 0x000d0000;
  31                 break;
  32         case 1600:
  33                 tmp |= 0x000c0000;
  34                 break;
  35         default:
  36                 pr_err("Unsupported frequency");
  37                 return -EINVAL;
  38         }
  39
  40         /*
  41          * Set Moduration rate
  42          * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
  43          */
  44 #if defined(DPLL_SSC_RATE_1PER)
  45         tmp &= ~0x00008000;
  46 #else
  47         tmp |= 0x00008000;
  48 #endif
  49         writel(tmp, SC_DPLLCTRL);
  50
  51         tmp = readl(SC_DPLLCTRL2);
  52         tmp |= SC_DPLLCTRL2_NRSTDS;
  53         writel(tmp, SC_DPLLCTRL2);
  54
  55         return 0;
  56 }
  57
  58 static void vpll_init(void)
  59 {
  60         u32 tmp, clk_mode_axosel;
  61
  62         /* Set VPLL27A &  VPLL27B */
  63         tmp = readl(SG_PINMON0);
  64         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
  65
  66         /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
  67         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
  68             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
  69                 return;
  70
  71         /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
  72         tmp = readl(SC_VPLL27ACTRL);
  73         tmp |= 0x00000001;
  74         writel(tmp, SC_VPLL27ACTRL);
  75         tmp = readl(SC_VPLL27BCTRL);
  76         tmp |= 0x00000001;
  77         writel(tmp, SC_VPLL27BCTRL);
  78
  79         /* Unset VPLA_K_LD and VPLB_K_LD bit */
  80         tmp = readl(SC_VPLL27ACTRL3);
  81         tmp &= ~0x10000000;
  82         writel(tmp, SC_VPLL27ACTRL3);
  83         tmp = readl(SC_VPLL27BCTRL3);
  84         tmp &= ~0x10000000;
  85         writel(tmp, SC_VPLL27BCTRL3);
  86
  87         /* Set VPLA_M and VPLB_M to 0x20 */
  88         tmp = readl(SC_VPLL27ACTRL2);
  89         tmp &= ~0x0000007f;
  90         tmp |= 0x00000020;
  91         writel(tmp, SC_VPLL27ACTRL2);
  92         tmp = readl(SC_VPLL27BCTRL2);
  93         tmp &= ~0x0000007f;
  94         tmp |= 0x00000020;
  95         writel(tmp, SC_VPLL27BCTRL2);
  96
  97         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
  98             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
  99                 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
 100                 tmp = readl(SC_VPLL27ACTRL3);
 101                 tmp &= ~0x000fffff;
 102                 tmp |= 0x00066666;
 103                 writel(tmp, SC_VPLL27ACTRL3);
 104                 tmp = readl(SC_VPLL27BCTRL3);
 105                 tmp &= ~0x000fffff;
 106                 tmp |= 0x00066666;
 107                 writel(tmp, SC_VPLL27BCTRL3);
 108         } else {
 109                 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
 110                 tmp = readl(SC_VPLL27ACTRL3);
 111                 tmp &= ~0x000fffff;
 112                 tmp |= 0x000f5800;
 113                 writel(tmp, SC_VPLL27ACTRL3);
 114                 tmp = readl(SC_VPLL27BCTRL3);
 115                 tmp &= ~0x000fffff;
 116                 tmp |= 0x000f5800;
 117                 writel(tmp, SC_VPLL27BCTRL3);
 118         }
 119
 120         /* wait 1 usec */
 121         udelay(1);
 122
 123         /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
 124         tmp = readl(SC_VPLL27ACTRL3);
 125         tmp |= 0x10000000;
 126         writel(tmp, SC_VPLL27ACTRL3);
 127         tmp = readl(SC_VPLL27BCTRL3);
 128         tmp |= 0x10000000;
 129         writel(tmp, SC_VPLL27BCTRL3);
 130
 131         /* Unset VPLA_SNRST and VPLB_SNRST bit */
 132         tmp = readl(SC_VPLL27ACTRL2);
 133         tmp |= 0x10000000;
 134         writel(tmp, SC_VPLL27ACTRL2);
 135         tmp = readl(SC_VPLL27BCTRL2);
 136         tmp |= 0x10000000;
 137         writel(tmp, SC_VPLL27BCTRL2);
 138
 139         /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
 140         tmp = readl(SC_VPLL27ACTRL);
 141         tmp &= ~0x00000001;
 142         writel(tmp, SC_VPLL27ACTRL);
 143         tmp = readl(SC_VPLL27BCTRL);
 144         tmp &= ~0x00000001;
 145         writel(tmp, SC_VPLL27BCTRL);
 146 }
 147
 148 int uniphier_pro4_pll_init(const struct uniphier_board_data *bd)
 149 {
 150         int ret;
 151
 152         ret = dpll_init(bd->dram_freq);
 153         if (ret)
 154                 return ret;
 155         vpll_init();
 156
 157         /*
 158          * Wait 500 usec until dpll get stable
 159          * We wait 1 usec in vpll_init() so 1 usec can be saved here.
 160          */
 161         udelay(499);
 162
 163         return 0;
 164 }