2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include "../sc-regs.h"
13 #include "../sg-regs.h"
15 #undef DPLL_SSC_RATE_1PER
17 static int dpll_init(unsigned int dram_freq)
23 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
24 * to FOUT ( DPLLCTRL.bit[29:20] )
26 tmp = readl(SC_DPLLCTRL);
36 pr_err("Unsupported frequency");
42 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
44 #if defined(DPLL_SSC_RATE_1PER)
49 writel(tmp, SC_DPLLCTRL);
51 tmp = readl(SC_DPLLCTRL2);
52 tmp |= SC_DPLLCTRL2_NRSTDS;
53 writel(tmp, SC_DPLLCTRL2);
58 static void vpll_init(void)
60 u32 tmp, clk_mode_axosel;
62 /* Set VPLL27A & VPLL27B */
63 tmp = readl(SG_PINMON0);
64 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
66 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
67 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
68 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
71 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
72 tmp = readl(SC_VPLL27ACTRL);
74 writel(tmp, SC_VPLL27ACTRL);
75 tmp = readl(SC_VPLL27BCTRL);
77 writel(tmp, SC_VPLL27BCTRL);
79 /* Unset VPLA_K_LD and VPLB_K_LD bit */
80 tmp = readl(SC_VPLL27ACTRL3);
82 writel(tmp, SC_VPLL27ACTRL3);
83 tmp = readl(SC_VPLL27BCTRL3);
85 writel(tmp, SC_VPLL27BCTRL3);
87 /* Set VPLA_M and VPLB_M to 0x20 */
88 tmp = readl(SC_VPLL27ACTRL2);
91 writel(tmp, SC_VPLL27ACTRL2);
92 tmp = readl(SC_VPLL27BCTRL2);
95 writel(tmp, SC_VPLL27BCTRL2);
97 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
98 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
99 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
100 tmp = readl(SC_VPLL27ACTRL3);
103 writel(tmp, SC_VPLL27ACTRL3);
104 tmp = readl(SC_VPLL27BCTRL3);
107 writel(tmp, SC_VPLL27BCTRL3);
109 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
110 tmp = readl(SC_VPLL27ACTRL3);
113 writel(tmp, SC_VPLL27ACTRL3);
114 tmp = readl(SC_VPLL27BCTRL3);
117 writel(tmp, SC_VPLL27BCTRL3);
123 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
124 tmp = readl(SC_VPLL27ACTRL3);
126 writel(tmp, SC_VPLL27ACTRL3);
127 tmp = readl(SC_VPLL27BCTRL3);
129 writel(tmp, SC_VPLL27BCTRL3);
131 /* Unset VPLA_SNRST and VPLB_SNRST bit */
132 tmp = readl(SC_VPLL27ACTRL2);
134 writel(tmp, SC_VPLL27ACTRL2);
135 tmp = readl(SC_VPLL27BCTRL2);
137 writel(tmp, SC_VPLL27BCTRL2);
139 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
140 tmp = readl(SC_VPLL27ACTRL);
142 writel(tmp, SC_VPLL27ACTRL);
143 tmp = readl(SC_VPLL27BCTRL);
145 writel(tmp, SC_VPLL27BCTRL);
148 int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
152 ret = dpll_init(bd->dram_freq);
158 * Wait 500 usec until dpll get stable
159 * We wait 1 usec in vpll_init() so 1 usec can be saved here.