arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/io.h>
   9 #include <mach/init.h>
  10 #include <mach/sc-regs.h>
  11 #include <mach/sg-regs.h>
  12
  13 static void dpll_init(void)
  14 {
  15         u32 tmp;
  16         /*
  17          * Set DPLL SSC parameters for DPLLCTRL3
  18          * [23]    DIVN_TEST    0x1
  19          * [22:16] DIVN         0x50
  20          * [10]    FREFSEL_TEST 0x1
  21          * [9:8]   FREFSEL      0x2
  22          * [4]     ICPD_TEST    0x1
  23          * [3:0]   ICPD         0xb
  24          */
  25         tmp = readl(SC_DPLLCTRL3);
  26         tmp &= ~0x00ff0717;
  27         tmp |= 0x00d0061b;
  28         writel(tmp, SC_DPLLCTRL3);
  29
  30         /*
  31          * Set DPLL SSC parameters for DPLLCTRL
  32          *                    <-1%>          <-2%>
  33          * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
  34          * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
  35          */
  36         tmp = readl(SC_DPLLCTRL);
  37         tmp &= ~0x3ff07fff;
  38 #ifdef CONFIG_DPLL_SSC_RATE_1PER
  39         tmp |= 0x084018bf;
  40 #else
  41         tmp |= 0x084031a6;
  42 #endif
  43         writel(tmp, SC_DPLLCTRL);
  44
  45         /*
  46          * Set DPLL SSC parameters for DPLLCTRL2
  47          * [31:29]  SSC_STEP     0
  48          * [27]     SSC_REG_REF  1
  49          * [26:20]  SSC_M        79     (0x4f)
  50          * [19:0]   SSC_K        964689 (0xeb851)
  51          */
  52         tmp = readl(SC_DPLLCTRL2);
  53         tmp &= ~0xefffffff;
  54         tmp |= 0x0cfeb851;
  55         writel(tmp, SC_DPLLCTRL2);
  56 }
  57
  58 static void upll_init(void)
  59 {
  60         u32 tmp, clk_mode_upll, clk_mode_axosel;
  61
  62         tmp = readl(SG_PINMON0);
  63         clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
  64         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
  65
  66         /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
  67         tmp = readl(SC_UPLLCTRL);
  68         tmp &= ~0x18000000;
  69         writel(tmp, SC_UPLLCTRL);
  70
  71         if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
  72                 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
  73                     clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
  74                         /* AXO: 25MHz */
  75                         tmp &= ~0x07ffffff;
  76                         tmp |= 0x0228f5c0;
  77                 } else {
  78                         /* AXO: default 24.576MHz */
  79                         tmp &= ~0x07ffffff;
  80                         tmp |= 0x02328000;
  81                 }
  82         }
  83
  84         writel(tmp, SC_UPLLCTRL);
  85
  86         /* set 1 to K_LD(UPLLCTRL.bit[27]) */
  87         tmp |= 0x08000000;
  88         writel(tmp, SC_UPLLCTRL);
  89
  90         /* wait 10 usec */
  91         udelay(10);
  92
  93         /* set 1 to SNRT(UPLLCTRL.bit[28]) */
  94         tmp |= 0x10000000;
  95         writel(tmp, SC_UPLLCTRL);
  96 }
  97
  98 static void vpll_init(void)
  99 {
 100         u32 tmp, clk_mode_axosel;
 101
 102         tmp = readl(SG_PINMON0);
 103         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
 104
 105         /* set 1 to VPLA27WP and VPLA27WP */
 106         tmp = readl(SC_VPLL27ACTRL);
 107         tmp |= 0x00000001;
 108         writel(tmp, SC_VPLL27ACTRL);
 109         tmp = readl(SC_VPLL27BCTRL);
 110         tmp |= 0x00000001;
 111         writel(tmp, SC_VPLL27BCTRL);
 112
 113         /* Set 0 to VPLA_K_LD and VPLB_K_LD */
 114         tmp = readl(SC_VPLL27ACTRL3);
 115         tmp &= ~0x10000000;
 116         writel(tmp, SC_VPLL27ACTRL3);
 117         tmp = readl(SC_VPLL27BCTRL3);
 118         tmp &= ~0x10000000;
 119         writel(tmp, SC_VPLL27BCTRL3);
 120
 121         /* Set 0 to VPLA_SNRST and VPLB_SNRST */
 122         tmp = readl(SC_VPLL27ACTRL2);
 123         tmp &= ~0x10000000;
 124         writel(tmp, SC_VPLL27ACTRL2);
 125         tmp = readl(SC_VPLL27BCTRL2);
 126         tmp &= ~0x10000000;
 127         writel(tmp, SC_VPLL27BCTRL2);
 128
 129         /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
 130         tmp = readl(SC_VPLL27ACTRL2);
 131         tmp &= ~0x0000007f;
 132         tmp |= 0x00000020;
 133         writel(tmp, SC_VPLL27ACTRL2);
 134         tmp = readl(SC_VPLL27BCTRL2);
 135         tmp &= ~0x0000007f;
 136         tmp |= 0x00000020;
 137         writel(tmp, SC_VPLL27BCTRL2);
 138
 139         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
 140             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
 141                 /* AXO: 25MHz */
 142                 tmp = readl(SC_VPLL27ACTRL3);
 143                 tmp &= ~0x000fffff;
 144                 tmp |= 0x00066664;
 145                 writel(tmp, SC_VPLL27ACTRL3);
 146                 tmp = readl(SC_VPLL27BCTRL3);
 147                 tmp &= ~0x000fffff;
 148                 tmp |= 0x00066664;
 149                 writel(tmp, SC_VPLL27BCTRL3);
 150         } else {
 151                 /* AXO: default 24.576MHz */
 152                 tmp = readl(SC_VPLL27ACTRL3);
 153                 tmp &= ~0x000fffff;
 154                 tmp |= 0x000f5800;
 155                 writel(tmp, SC_VPLL27ACTRL3);
 156                 tmp = readl(SC_VPLL27BCTRL3);
 157                 tmp &= ~0x000fffff;
 158                 tmp |= 0x000f5800;
 159                 writel(tmp, SC_VPLL27BCTRL3);
 160         }
 161
 162         /* Set 1 to VPLA_K_LD and VPLB_K_LD */
 163         tmp = readl(SC_VPLL27ACTRL3);
 164         tmp |= 0x10000000;
 165         writel(tmp, SC_VPLL27ACTRL3);
 166         tmp = readl(SC_VPLL27BCTRL3);
 167         tmp |= 0x10000000;
 168         writel(tmp, SC_VPLL27BCTRL3);
 169
 170         /* wait 10 usec */
 171         udelay(10);
 172
 173         /* Set 0 to VPLA_SNRST and VPLB_SNRST */
 174         tmp = readl(SC_VPLL27ACTRL2);
 175         tmp |= 0x10000000;
 176         writel(tmp, SC_VPLL27ACTRL2);
 177         tmp = readl(SC_VPLL27BCTRL2);
 178         tmp |= 0x10000000;
 179         writel(tmp, SC_VPLL27BCTRL2);
 180
 181         /* set 0 to VPLA27WP and VPLA27WP */
 182         tmp = readl(SC_VPLL27ACTRL);
 183         tmp &= ~0x00000001;
 184         writel(tmp, SC_VPLL27ACTRL);
 185         tmp = readl(SC_VPLL27BCTRL);
 186         tmp |= ~0x00000001;
 187         writel(tmp, SC_VPLL27BCTRL);
 188 }
 189
 190 int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
 191 {
 192         dpll_init();
 193         upll_init();
 194         vpll_init();
 195
 196         /*
 197          * Wait 500 usec until dpll get stable
 198          * We wait 10 usec in upll_init() and vpll_init()
 199          * so 20 usec can be saved here.
 200          */
 201         udelay(480);
 202
 203         return 0;
 204 }