arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <mach/init.h>
  11 #include <mach/sc-regs.h>
  12 #include <mach/sg-regs.h>
  13
  14 #undef DPLL_SSC_RATE_1PER
  15
  16 static int dpll_init(unsigned int dram_freq)
  17 {
  18         u32 tmp;
  19
  20         /*
  21          * Set Frequency
  22          * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
  23          * to FOUT ( DPLLCTRL.bit[29:20] )
  24          */
  25         tmp = readl(SC_DPLLCTRL);
  26         tmp &= ~(0x000f0000);
  27         switch (dram_freq) {
  28         case 1333:
  29                 tmp |= 0x000d0000;
  30                 break;
  31         case 1600:
  32                 tmp |= 0x000c0000;
  33                 break;
  34         default:
  35                 pr_err("Unsupported frequency");
  36                 return -EINVAL;
  37         }
  38
  39         /*
  40          * Set Moduration rate
  41          * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
  42          */
  43 #if defined(DPLL_SSC_RATE_1PER)
  44         tmp &= ~0x00008000;
  45 #else
  46         tmp |= 0x00008000;
  47 #endif
  48         writel(tmp, SC_DPLLCTRL);
  49
  50         tmp = readl(SC_DPLLCTRL2);
  51         tmp |= SC_DPLLCTRL2_NRSTDS;
  52         writel(tmp, SC_DPLLCTRL2);
  53
  54         return 0;
  55 }
  56
  57 static void vpll_init(void)
  58 {
  59         u32 tmp, clk_mode_axosel;
  60
  61         /* Set VPLL27A &  VPLL27B */
  62         tmp = readl(SG_PINMON0);
  63         clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
  64
  65         /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
  66         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
  67             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
  68                 return;
  69
  70         /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
  71         tmp = readl(SC_VPLL27ACTRL);
  72         tmp |= 0x00000001;
  73         writel(tmp, SC_VPLL27ACTRL);
  74         tmp = readl(SC_VPLL27BCTRL);
  75         tmp |= 0x00000001;
  76         writel(tmp, SC_VPLL27BCTRL);
  77
  78         /* Unset VPLA_K_LD and VPLB_K_LD bit */
  79         tmp = readl(SC_VPLL27ACTRL3);
  80         tmp &= ~0x10000000;
  81         writel(tmp, SC_VPLL27ACTRL3);
  82         tmp = readl(SC_VPLL27BCTRL3);
  83         tmp &= ~0x10000000;
  84         writel(tmp, SC_VPLL27BCTRL3);
  85
  86         /* Set VPLA_M and VPLB_M to 0x20 */
  87         tmp = readl(SC_VPLL27ACTRL2);
  88         tmp &= ~0x0000007f;
  89         tmp |= 0x00000020;
  90         writel(tmp, SC_VPLL27ACTRL2);
  91         tmp = readl(SC_VPLL27BCTRL2);
  92         tmp &= ~0x0000007f;
  93         tmp |= 0x00000020;
  94         writel(tmp, SC_VPLL27BCTRL2);
  95
  96         if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
  97             clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
  98                 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
  99                 tmp = readl(SC_VPLL27ACTRL3);
 100                 tmp &= ~0x000fffff;
 101                 tmp |= 0x00066666;
 102                 writel(tmp, SC_VPLL27ACTRL3);
 103                 tmp = readl(SC_VPLL27BCTRL3);
 104                 tmp &= ~0x000fffff;
 105                 tmp |= 0x00066666;
 106                 writel(tmp, SC_VPLL27BCTRL3);
 107         } else {
 108                 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
 109                 tmp = readl(SC_VPLL27ACTRL3);
 110                 tmp &= ~0x000fffff;
 111                 tmp |= 0x000f5800;
 112                 writel(tmp, SC_VPLL27ACTRL3);
 113                 tmp = readl(SC_VPLL27BCTRL3);
 114                 tmp &= ~0x000fffff;
 115                 tmp |= 0x000f5800;
 116                 writel(tmp, SC_VPLL27BCTRL3);
 117         }
 118
 119         /* wait 1 usec */
 120         udelay(1);
 121
 122         /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
 123         tmp = readl(SC_VPLL27ACTRL3);
 124         tmp |= 0x10000000;
 125         writel(tmp, SC_VPLL27ACTRL3);
 126         tmp = readl(SC_VPLL27BCTRL3);
 127         tmp |= 0x10000000;
 128         writel(tmp, SC_VPLL27BCTRL3);
 129
 130         /* Unset VPLA_SNRST and VPLB_SNRST bit */
 131         tmp = readl(SC_VPLL27ACTRL2);
 132         tmp |= 0x10000000;
 133         writel(tmp, SC_VPLL27ACTRL2);
 134         tmp = readl(SC_VPLL27BCTRL2);
 135         tmp |= 0x10000000;
 136         writel(tmp, SC_VPLL27BCTRL2);
 137
 138         /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
 139         tmp = readl(SC_VPLL27ACTRL);
 140         tmp &= ~0x00000001;
 141         writel(tmp, SC_VPLL27ACTRL);
 142         tmp = readl(SC_VPLL27BCTRL);
 143         tmp &= ~0x00000001;
 144         writel(tmp, SC_VPLL27BCTRL);
 145 }
 146
 147 int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
 148 {
 149         int ret;
 150
 151         ret = dpll_init(bd->dram_freq);
 152         if (ret)
 153                 return ret;
 154         vpll_init();
 155
 156         /*
 157          * Wait 500 usec until dpll get stable
 158          * We wait 1 usec in vpll_init() so 1 usec can be saved here.
 159          */
 160         udelay(499);
 161
 162         return 0;
 163 }