2 * Copyright (C) 2012-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/linkage.h>
10 #include <linux/sizes.h>
11 #include <asm/system.h>
13 #include <mach/arm-mpcore.h>
14 #include <mach/sbc-regs.h>
15 #include <mach/ssc-regs.h>
18 mov r8, lr @ persevere link reg across call
21 * The UniPhier Boot ROM loads SPL code to the L2 cache.
22 * But CPUs can only do instruction fetch now because start.S has
23 * cleared C and M bits.
24 * First we need to turn on MMU and Dcache again to get back
27 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
28 orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
29 mcr p15, 0, r0, c1, c0, 0
31 #ifdef CONFIG_DEBUG_LL
32 bl setup_lowlevel_debug
36 * Now we are using the page table embedded in the Boot ROM.
37 * It is not handy since it is not a straight mapped table for sLD3.
38 * What we need to do next is to switch over to the page table in SPL.
40 ldr r3, =init_page_table @ page table must be 16KB aligned
42 /* Disable MMU and Dcache before switching Page Table */
43 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
44 bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache
45 mcr p15, 0, r0, c1, c0, 0
49 #ifdef CONFIG_UNIPHIER_SMP
51 * ACTLR (Auxiliary Control Register) for Cortex-A9
53 * bit[8] Alloc in one way
54 * bit[7] EXCL (Exclusive cache bit)
56 * bit[3] Write full line of zeros mode
57 * bit[2] L1 Prefetch enable
58 * bit[1] L2 prefetch enable
59 * bit[0] FW (Cache and TLB maintenance broadcast)
61 mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register)
62 orr r0, r0, #0x41 @ enable SMP, FW bit
63 mcr p15, 0, r0, c1, c0, 1
65 /* branch by CPU ID */
66 mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register)
70 ldr r1, =ROM_BOOT_ROMRSV2
77 bx r0 @ r0: entry point of U-Boot main for the secondary CPU
79 ldr r1, =ROM_BOOT_ROMRSV2
80 ldr r0, =_start @ entry for the secondary CPU
82 ldr r0, [r1] @ make sure str is complete before sev
83 sev @ kick the sedoncary CPU
84 mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register
85 bfc r1, #0, #13 @ clear bit 12-0
87 str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register
88 mov r0, #1 @ SCU enable
89 str r0, [r1, #SCU_CTRL] @ SCU Control Register
92 bl setup_init_ram @ RAM area for temporary stack pointer
94 mov lr, r8 @ restore link
95 mov pc, lr @ back to my caller
96 ENDPROC(lowlevel_init)
99 mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
101 orr r0, r0, #0x20 @ disable TTBR1
102 mcr p15, 0, r0, c2, c0, 2
104 orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA
105 mcr p15, 0, r0, c2, c0, 0 @ TTBR0
108 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
110 mov r0, #-1 @ manager for all domains (No permission check)
111 mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
117 * TLBs was already invalidated in "../start.S"
118 * So, we don't need to invalidate it here.
120 mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register)
121 orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable
122 mcr p15, 0, r0, c1, c0, 0
128 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
129 * It is large enough for tmp RAM.
131 #define BOOT_RAM_SIZE (SZ_32K)
132 #define BOOT_WAY_BITS (0x00000100) /* way 8 */
134 ENTRY(setup_init_ram)
136 * Touch to zero for the boot way
140 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
142 ldr r0, = 0x00408006 @ touch to zero with address range
145 ldr r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE) @ base address
148 ldr r0, = BOOT_RAM_SIZE
151 ldr r0, = BOOT_WAY_BITS
156 cmp r0, #0 @ check if the command is successfully set
157 bne 0b @ try again if an error occurres
163 bne 1b @ wait until the operation is completed
164 str r0, [r1] @ clear the complete notification flag
167 ENDPROC(setup_init_ram)