arch/arm/mach-uniphier/dram/umc-ld11.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  */
   4
   5 #include <common.h>
   6 #include <linux/io.h>
   7 #include <linux/sizes.h>
   8 #include <asm/processor.h>
   9
  10 #include "../init.h"
  11 #include "umc64-regs.h"
  12
  13 #define CONFIG_DDR_FREQ         1866
  14
  15 #define DRAM_CH_NR      2
  16
  17 enum dram_freq {
  18         DRAM_FREQ_1600M,
  19         DRAM_FREQ_NR,
  20 };
  21
  22 enum dram_size {
  23         DRAM_SZ_256M,
  24         DRAM_SZ_512M,
  25         DRAM_SZ_NR,
  26 };
  27
  28 /* umc */
  29 static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
  30 static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
  31 static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
  32 static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
  33 static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
  34 static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
  35
  36 static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
  37 static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
  38 static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
  39 static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
  40 static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
  41 static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
  42 static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
  43 static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
  44
  45 static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
  46                        unsigned long size, int ch)
  47 {
  48         writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
  49         writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
  50         writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
  51         writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
  52         writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
  53         writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
  54
  55         writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
  56         writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
  57
  58         writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
  59         writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
  60
  61         writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
  62         writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
  63
  64         writel(0x00000003, dc_base + UMC_ACSSETA);
  65         writel(0x00000103, dc_base + UMC_FLOWCTLG);
  66         writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
  67         writel(0x02020200, dc_base + UMC_SPCSETB);
  68         writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
  69         writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
  70
  71         return 0;
  72 }
  73
  74 static int umc_ch_init(void __iomem *umc_ch_base,
  75                        enum dram_freq freq, unsigned long size, int ch)
  76 {
  77         void __iomem *dc_base  = umc_ch_base;
  78
  79         return umc_dc_init(dc_base, freq, size, ch);
  80 }
  81
  82 static void um_init(void __iomem *um_base)
  83 {
  84         writel(0x00000001, um_base + UMC_SIORST);
  85         writel(0x00000001, um_base + UMC_VO0RST);
  86         writel(0x00000001, um_base + UMC_VPERST);
  87         writel(0x00000001, um_base + UMC_RGLRST);
  88         writel(0x00000001, um_base + UMC_A2DRST);
  89         writel(0x00000001, um_base + UMC_DMDRST);
  90 }
  91
  92 int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
  93 {
  94         void __iomem *um_base = (void __iomem *)0x5B800000;
  95         void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
  96         enum dram_freq freq;
  97         int ch, ret;
  98
  99         switch (bd->dram_freq) {
 100         case 1600:
 101                 freq = DRAM_FREQ_1600M;
 102                 break;
 103         default:
 104                 pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
 105                 return -EINVAL;
 106         }
 107
 108         for (ch = 0; ch < bd->dram_nr_ch; ch++) {
 109                 unsigned long size = bd->dram_ch[ch].size;
 110                 unsigned int width = bd->dram_ch[ch].width;
 111
 112                 ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
 113                 if (ret) {
 114                         pr_err("failed to initialize UMC ch%d\n", ch);
 115                         return ret;
 116                 }
 117
 118                 umc_ch_base += 0x00200000;
 119         }
 120
 121         um_init(um_base);
 122
 123         return 0;
 124 }