arch/arm/mach-uniphier/dram/umc-ld11.c

   1 /*
   2  * Copyright (C) 2016 Socionext Inc.
   3  */
   4
   5 #include <common.h>
   6 #include <linux/io.h>
   7 #include <linux/sizes.h>
   8 #include <asm/processor.h>
   9
  10 #include "../init.h"
  11 #include "ddrphy-regs.h"
  12 #include "umc64-regs.h"
  13
  14 #define DDR_FREQ                1600
  15
  16 #define DRAM_CH_NR      2
  17 #define RANK_BLOCKS_TR  2
  18
  19 enum dram_freq {
  20         DRAM_FREQ_1600M,
  21         DRAM_FREQ_NR,
  22 };
  23
  24 enum dram_size {
  25         DRAM_SZ_256M,
  26         DRAM_SZ_512M,
  27         DRAM_SZ_NR,
  28 };
  29
  30 /* PHY */
  31 static const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
  32 static const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
  33 static const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
  34 static const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
  35 static const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
  36
  37 /* Register address */
  38 #define PHY_ZQ0CR1      0x00000184
  39 #define PHY_ZQ1CR1      0x00000194
  40 #define PHY_ZQ2CR1      0x000001A4
  41 #define PHY_DX0GCR      0x000001C0
  42 #define PHY_DX0GTR      0x000001F0
  43 #define PHY_DX1GCR      0x00000200
  44 #define PHY_DX1GTR      0x00000230
  45 #define PHY_DX2GCR      0x00000240
  46 #define PHY_DX2GTR      0x00000270
  47 #define PHY_DX3GCR      0x00000280
  48 #define PHY_DX3GTR      0x000002B0
  49
  50 #define PHY_DXMDLR(dx)          (0x000001EC + 0x40 * (dx))
  51 #define PHY_DXLCDLR0(dx)        (0x000001E0 + 0x40 * (dx))
  52 #define PHY_DXLCDLR1(dx)        (0x000001E4 + 0x40 * (dx))
  53 #define PHY_DXLCDLR2(dx)        (0x000001E8 + 0x40 * (dx))
  54 #define PHY_DXBDLR1(dx)         (0x000001D0 + 0x40 * (dx))
  55 #define PHY_DXBDLR2(dx)         (0x000001D4 + 0x40 * (dx))
  56
  57 /* MASK */
  58 #define PHY_ACBD_MASK           0x00FC0000
  59 #define PHY_CK0BD_MASK          0x0000003F
  60 #define PHY_CK1BD_MASK          0x00000FC0
  61 #define PHY_IPRD_MASK           0x000000FF
  62 #define PHY_WLD_MASK(rank)      (0xFF << (8 * (rank)))
  63 #define PHY_DQSGD_MASK(rank)    (0xFF << (8 * (rank)))
  64 #define PHY_DQSGX_MASK          BIT(6)
  65 #define PHY_DSWBD_MASK          0x3F000000      /* bit[29:24] */
  66 #define PHY_DSDQOE_MASK         0x00000FFF
  67
  68 static void ddrphy_maskwritel(u32 data, u32 mask, void __iomem *addr)
  69 {
  70         u32 value;
  71
  72         value = (readl(addr) & ~(mask)) | (data & mask);
  73         writel(value, addr);
  74 }
  75
  76 static u32 ddrphy_maskreadl(u32 mask, void __iomem *addr)
  77 {
  78         return readl(addr) & mask;
  79 }
  80
  81 /* step of 0.5T  for PUB-byte */
  82 static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
  83 {
  84         return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
  85 }
  86
  87 /* Calculating step for PUB-byte */
  88 static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
  89 {
  90         return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
  91 }
  92
  93 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
  94 {
  95         u32 tmp;
  96
  97         tmp = readl(phy_base + PHY_PGCR1);
  98
  99         if (enable)
 100                 tmp &= ~PHY_PGCR1_INHVT;
 101         else
 102                 tmp |= PHY_PGCR1_INHVT;
 103
 104         writel(tmp, phy_base + PHY_PGCR1);
 105
 106         if (!enable) {
 107                 while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
 108                         cpu_relax();
 109         }
 110 }
 111
 112 static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
 113                                         int delay_qoffset, int enable,
 114                                         void __iomem *phy_base)
 115 {
 116         u8 ck_step0, ck_step1;  /* ckoffset_step for clock */
 117         u8 q_step;      /*  qoffset_step for clock */
 118         int dx;
 119
 120         dx = 2; /* use dx2 in sLD11 */
 121
 122         ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base);     /* CK-Offset */
 123         ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base);     /* CK-Offset */
 124         q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base);     /*  Q-Offset */
 125
 126         ddrphy_vt_ctrl(phy_base, 0);
 127
 128         /* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
 129         if (enable == 1)
 130                 ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
 131                                   PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
 132                                   phy_base + PHY_ACBDLR);
 133
 134         ddrphy_vt_ctrl(phy_base, 1);
 135 }
 136
 137 static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
 138                                    int enable, void __iomem *phy_base)
 139 {
 140         int rank;
 141         int delay_wl[4];
 142         u32 wl_mask  = 0;   /* WriteLeveling's Mask  */
 143         u32 wl_value = 0;   /* WriteLeveling's Value */
 144
 145         delay_wl[0] = r0_delay & 0xfff;
 146         delay_wl[1] = r1_delay & 0xfff;
 147         delay_wl[2] = 0;
 148         delay_wl[3] = 0;
 149
 150         ddrphy_vt_ctrl(phy_base, 0);
 151
 152         for (rank = 0; rank < 4; rank++) {
 153                 wl_mask  |= PHY_WLD_MASK(rank);
 154                 /*  WriteLeveling's delay */
 155                 wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
 156         }
 157
 158         if (enable == 1)
 159                 ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
 160
 161         ddrphy_vt_ctrl(phy_base, 1);
 162 }
 163
 164 static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
 165                                      int enable, void __iomem *phy_base)
 166 {
 167         int rank;
 168         int delay_dqsg[4];
 169         u32 dqsg_mask  = 0;   /* DQSGating_LCDL_delay's Mask  */
 170         u32 dqsg_value = 0;   /* DQSGating_LCDL_delay's Value */
 171
 172         delay_dqsg[0] = r0_delay;
 173         delay_dqsg[1] = r1_delay;
 174         delay_dqsg[2] = 0;
 175         delay_dqsg[3] = 0;
 176
 177         ddrphy_vt_ctrl(phy_base, 0);
 178
 179         for (rank = 0; rank < 4; rank++)  {
 180                 dqsg_mask  |= PHY_DQSGD_MASK(rank);
 181                  /* DQSGating's delay */
 182                 dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
 183         }
 184
 185         if (enable == 1)
 186                 ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
 187
 188         ddrphy_vt_ctrl(phy_base, 1);
 189 }
 190
 191 static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
 192 {
 193         u8 dswb_step;
 194
 195         ddrphy_vt_ctrl(phy_base, 0);
 196
 197         dswb_step = ddrphy_hpstep(delay, dx, phy_base);     /* DQS-BDL's delay */
 198
 199         if (enable == 1)
 200                 ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
 201
 202         ddrphy_vt_ctrl(phy_base, 1);
 203 }
 204
 205 static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
 206                                    int enable, void __iomem *phy_base)
 207 {
 208         u8 dqs_oe_step, dq_oe_step;
 209         u32 wdata;
 210
 211         ddrphy_vt_ctrl(phy_base, 0);
 212
 213         /* OE(DQS,DQ) */
 214         dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base);     /* DQS-oe's delay */
 215         dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base);     /* DQ-oe's delay */
 216         wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
 217
 218         if (enable == 1)
 219                 ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
 220
 221         ddrphy_vt_ctrl(phy_base, 1);
 222 }
 223
 224 static void ddrphy_ext_dqsgt(void __iomem *phy_base)
 225 {
 226         /* Extend DQSGating_window   min:+1T  max:+1T */
 227         ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
 228 }
 229
 230 static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
 231 {
 232         int dx, block, byte;
 233         u32 lcdlr1, wdqd;
 234
 235         ddrphy_vt_ctrl(phy_base, 0);
 236
 237         for (block = 0; block < RANK_BLOCKS_TR; block++) {
 238                 for (byte = 0; byte < 2; byte++) {
 239                         dx = block * 2 + byte;
 240                         lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
 241                         wdqd = lcdlr1 & 0xff;
 242                         wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
 243                                      0U, 0xffU);
 244                         lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
 245                         writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
 246                         readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
 247                 }
 248         }
 249
 250         ddrphy_vt_ctrl(phy_base, 1);
 251 }
 252
 253 static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
 254                                  const int neg_shift[][2])
 255 {
 256         int dx, block, byte;
 257         u32 lcdlr1, rdqsd, rdqnsd;
 258
 259         ddrphy_vt_ctrl(phy_base, 0);
 260
 261         for (block = 0; block < RANK_BLOCKS_TR; block++) {
 262                 for (byte = 0; byte < 2; byte++) {
 263                         dx = block * 2 + byte;
 264                         lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
 265
 266                         /*  DQS LCDL  RDQNSD->[23:16]  RDQSD->[15:8] */
 267                         rdqsd  = (lcdlr1 >> 8) & 0xff;
 268                         rdqnsd = (lcdlr1 >> 16) & 0xff;
 269                         rdqsd  = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
 270                                        0U, 0xffU);
 271                         rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
 272                                        0U, 0xffU);
 273                         lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
 274                         writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
 275                         readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
 276                 }
 277         }
 278
 279         ddrphy_vt_ctrl(phy_base, 1);
 280 }
 281
 282 static void ddrphy_boot_run_hws(void __iomem *phy_base)
 283 {
 284         /* Hard Training for DIO */
 285         writel(0x0000f401, phy_base + PHY_PIR);
 286         while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
 287                 cpu_relax();
 288 }
 289
 290 static void ddrphy_training(void __iomem *phy_base)
 291 {
 292         /* DIO roffset shift before hard training */
 293         ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
 294
 295         /* Hard Training for each CH */
 296         ddrphy_boot_run_hws(phy_base);
 297
 298         /* DIO toffset shift after training */
 299         ddrphy_shift_tof_hws(phy_base, tof_shift);
 300
 301         /* DIO roffset shift after training */
 302         ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
 303
 304         /* Extend DQSGating window  min:+1T  max:+1T */
 305         ddrphy_ext_dqsgt(phy_base);
 306 }
 307
 308 static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
 309 {
 310         writel(0x40000000, phy_base + PHY_PIR);
 311         writel(0x0300C4F1, phy_base + PHY_PGCR1);
 312         writel(0x0C807D04, phy_base + PHY_PTR0);
 313         writel(0x27100578, phy_base + PHY_PTR1);
 314         writel(0x00083DEF, phy_base + PHY_PTR2);
 315         writel(0x12061A80, phy_base + PHY_PTR3);
 316         writel(0x08027100, phy_base + PHY_PTR4);
 317         writel(0x9D9CBB66, phy_base + PHY_DTPR0);
 318         writel(0x1a878400, phy_base + PHY_DTPR1);
 319         writel(0x50025200, phy_base + PHY_DTPR2);
 320         writel(0xF004641A, phy_base + PHY_DSGCR);
 321         writel(0x0000040B, phy_base + PHY_DCR);
 322         writel(0x00000d71, phy_base + PHY_MR0);
 323         writel(0x00000006, phy_base + PHY_MR1);
 324         writel(0x00000098, phy_base + PHY_MR2);
 325         writel(0x00000000, phy_base + PHY_MR3);
 326
 327         while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
 328                 cpu_relax();
 329
 330         writel(0x00000059, phy_base + PHY_ZQ0CR1);
 331         writel(0x00000019, phy_base + PHY_ZQ1CR1);
 332         writel(0x00000019, phy_base + PHY_ZQ2CR1);
 333         writel(0x30FC6C20, phy_base + PHY_PGCR2);
 334
 335         ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
 336         ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
 337         ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
 338         ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
 339         ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
 340         ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
 341         ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
 342         ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
 343         ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
 344         ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
 345         ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
 346         ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
 347         ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
 348         ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
 349         ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
 350         ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
 351         ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
 352
 353         writel(0x44000E81, phy_base + PHY_DX0GCR);
 354         writel(0x44000E81, phy_base + PHY_DX1GCR);
 355         writel(0x44000E81, phy_base + PHY_DX2GCR);
 356         writel(0x44000E81, phy_base + PHY_DX3GCR);
 357         writel(0x00055002, phy_base + PHY_DX0GTR);
 358         writel(0x00055002, phy_base + PHY_DX1GTR);
 359         writel(0x00055010, phy_base + PHY_DX2GTR);
 360         writel(0x00055010, phy_base + PHY_DX3GTR);
 361         writel(0x930035C7, phy_base + PHY_DTCR);
 362         writel(0x00000003, phy_base + PHY_PIR);
 363         readl(phy_base + PHY_PIR);
 364         while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
 365                 cpu_relax();
 366
 367         writel(0x00000181, phy_base + PHY_PIR);
 368         readl(phy_base + PHY_PIR);
 369         while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
 370                 cpu_relax();
 371
 372         writel(0x44181884, phy_base + PHY_DXCCR);
 373         writel(0x00000001, phy_base + PHY_GPR1);
 374 }
 375
 376 /* UMC */
 377 static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
 378 static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
 379 static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
 380 static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
 381 static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
 382 static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
 383
 384 static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
 385 static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
 386 static const u32 umc_odtctl[DRAM_FREQ_NR]   = {0x02000002};
 387 static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
 388
 389 static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
 390
 391 static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
 392                        unsigned long size, int ch)
 393 {
 394         /* Wait for PHY Init Complete */
 395         writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
 396         writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
 397         writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
 398         writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
 399         writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
 400         writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
 401
 402         writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
 403         writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
 404
 405         writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
 406         writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
 407
 408         writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
 409         writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
 410
 411         writel(0x00000003, dc_base + UMC_ACSSETA);
 412         writel(0x00000103, dc_base + UMC_FLOWCTLG);
 413         writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
 414         writel(0x02020200, dc_base + UMC_SPCSETB);
 415         writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
 416         writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
 417
 418         return 0;
 419 }
 420
 421 static int umc_ch_init(void __iomem *umc_ch_base,
 422                        enum dram_freq freq, unsigned long size, int ch)
 423 {
 424         void __iomem *dc_base  = umc_ch_base;
 425
 426         return umc_dc_init(dc_base, freq, size, ch);
 427 }
 428
 429 static void um_init(void __iomem *um_base)
 430 {
 431         writel(0x00000001, um_base + UMC_SIORST);
 432         writel(0x00000001, um_base + UMC_VO0RST);
 433         writel(0x00000001, um_base + UMC_VPERST);
 434         writel(0x00000001, um_base + UMC_RGLRST);
 435         writel(0x00000001, um_base + UMC_A2DRST);
 436         writel(0x00000001, um_base + UMC_DMDRST);
 437 }
 438
 439 int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
 440 {
 441         void __iomem *um_base = (void __iomem *)0x5B800000;
 442         void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
 443         void __iomem *phy_base = (void __iomem *)0x5BC01000;
 444         enum dram_freq freq;
 445         int ch, ret;
 446
 447         switch (bd->dram_freq) {
 448         case 1600:
 449                 freq = DRAM_FREQ_1600M;
 450                 break;
 451         default:
 452                 pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
 453                 return -EINVAL;
 454         }
 455
 456         writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
 457         while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
 458                 cpu_relax();
 459
 460         writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
 461         writel(0x00000001, umc_ch_base + UMC_DEBUGC);
 462         writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
 463
 464         writel(0x00000100, umc_ch_base + UMC_INITSET);
 465         while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
 466                 cpu_relax();
 467
 468         writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
 469         while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
 470                 cpu_relax();
 471
 472         ddrphy_init(phy_base, freq);
 473
 474         for (ch = 0; ch < DRAM_CH_NR; ch++) {
 475                 unsigned long size = bd->dram_ch[ch].size;
 476                 unsigned int width = bd->dram_ch[ch].width;
 477
 478                 ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
 479                 if (ret) {
 480                         pr_err("failed to initialize UMC ch%d\n", ch);
 481                         return ret;
 482                 }
 483
 484                 umc_ch_base += 0x00200000;
 485         }
 486         ddrphy_training(phy_base);
 487
 488         um_init(um_base);
 489
 490         return 0;
 491 }