2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/kernel.h>
11 #include <linux/errno.h>
13 #include <linux/sizes.h>
18 #define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
19 #define SC_PLLCTRL_SSC_EN BIT(31)
20 #define SC_PLLCTRL2_NRSTDS BIT(28)
21 #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
22 #define SC_PLLCTRL3_REGI_SHIFT 16
23 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
25 /* PLL type: VPLL27 */
26 #define SC_VPLL27CTRL_WP BIT(0)
27 #define SC_VPLL27CTRL3_K_LD BIT(28)
30 #define SC_DSPLLCTRL2_K_LD BIT(28)
32 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
33 unsigned int ssc_rate, unsigned int divn)
38 base = ioremap(reg_base, SZ_16);
42 if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
43 tmp = readl(base); /* SSCPLLCTRL */
44 tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
45 tmp |= DIV_ROUND_CLOSEST(487UL * freq * ssc_rate, divn * 512) &
46 SC_PLLCTRL_SSC_DK_MASK;
49 tmp = readl(base + 4);
50 tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
51 tmp |= DIV_ROUND_CLOSEST(21431887UL * freq, divn * 512) &
52 SC_PLLCTRL2_SSC_JK_MASK;
53 writel(tmp, base + 4);
58 tmp = readl(base + 4); /* SSCPLLCTRL2 */
59 tmp |= SC_PLLCTRL2_NRSTDS;
60 writel(tmp, base + 4);
67 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
72 base = ioremap(reg_base, SZ_16);
76 tmp = readl(base); /* SSCPLLCTRL */
77 tmp |= SC_PLLCTRL_SSC_EN;
85 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
90 base = ioremap(reg_base, SZ_16);
94 tmp = readl(base + 8); /* SSCPLLCTRL3 */
95 tmp &= ~SC_PLLCTRL3_REGI_MASK;
96 tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
97 writel(tmp, base + 8);
104 int uniphier_ld20_vpll27_init(unsigned long reg_base)
109 base = ioremap(reg_base, SZ_16);
113 tmp = readl(base); /* VPLL27CTRL */
114 tmp |= SC_VPLL27CTRL_WP; /* write protect off */
117 tmp = readl(base + 8); /* VPLL27CTRL3 */
118 tmp |= SC_VPLL27CTRL3_K_LD;
119 writel(tmp, base + 8);
121 tmp = readl(base); /* VPLL27CTRL */
122 tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
130 int uniphier_ld20_dspll_init(unsigned long reg_base)
135 base = ioremap(reg_base, SZ_16);
139 tmp = readl(base + 4); /* DSPLLCTRL2 */
140 tmp |= SC_DSPLLCTRL2_K_LD;
141 writel(tmp, base + 4);