arch/arm/mach-uniphier/board_init.c

   1 /*
   2  * Copyright (C) 2012-2015 Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <libfdt.h>
  11 #include <linux/io.h>
  12
  13 #include "init.h"
  14 #include "micro-support-card.h"
  15 #include "sg-regs.h"
  16 #include "soc-info.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static void uniphier_setup_xirq(void)
  21 {
  22         const void *fdt = gd->fdt_blob;
  23         int soc_node, aidet_node;
  24         const fdt32_t *val;
  25         unsigned long aidet_base;
  26         u32 tmp;
  27
  28         soc_node = fdt_path_offset(fdt, "/soc");
  29         if (soc_node < 0)
  30                 return;
  31
  32         aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
  33         if (aidet_node < 0)
  34                 return;
  35
  36         val = fdt_getprop(fdt, aidet_node, "reg", NULL);
  37         if (!val)
  38                 return;
  39
  40         aidet_base = fdt32_to_cpu(*val);
  41
  42         tmp = readl(aidet_base + 8);    /* AIDET DETCONFR2 */
  43         tmp |= 0x00ff0000;              /* Set XIRQ0-7 low active */
  44         writel(tmp, aidet_base + 8);
  45
  46         tmp = readl(0x55000090);        /* IRQCTL */
  47         tmp |= 0x000000ff;
  48         writel(tmp, 0x55000090);
  49 }
  50
  51 #ifdef CONFIG_ARCH_UNIPHIER_LD11
  52 static void uniphier_ld11_misc_init(void)
  53 {
  54         sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0    -> XIRQ0 */
  55         sg_set_iectrl(149);
  56         sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4    -> XIRQ4 */
  57         sg_set_iectrl(153);
  58 }
  59 #endif
  60
  61 #ifdef CONFIG_ARCH_UNIPHIER_LD20
  62 static void uniphier_ld20_misc_init(void)
  63 {
  64         sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0    -> XIRQ0 */
  65         sg_set_iectrl(149);
  66         sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4    -> XIRQ4 */
  67         sg_set_iectrl(153);
  68
  69         /* ES1 errata: increase VDD09 supply to suppress VBO noise */
  70         if (uniphier_get_soc_revision() == 1) {
  71                 writel(0x00000003, 0x6184e004);
  72                 writel(0x00000100, 0x6184e040);
  73                 writel(0x0000b500, 0x6184e024);
  74                 writel(0x00000001, 0x6184e000);
  75         }
  76 #ifdef CONFIG_ARMV8_MULTIENTRY
  77         cci500_init(2);
  78 #endif
  79 }
  80 #endif
  81
  82 struct uniphier_initdata {
  83         unsigned int soc_id;
  84         bool nand_2cs;
  85         void (*sbc_init)(void);
  86         void (*pll_init)(void);
  87         void (*clk_init)(void);
  88         void (*misc_init)(void);
  89 };
  90
  91 static const struct uniphier_initdata uniphier_initdata[] = {
  92 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
  93         {
  94                 .soc_id = UNIPHIER_SLD3_ID,
  95                 .nand_2cs = true,
  96                 .sbc_init = uniphier_sbc_init_admulti,
  97                 .pll_init = uniphier_sld3_pll_init,
  98                 .clk_init = uniphier_ld4_clk_init,
  99         },
 100 #endif
 101 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 102         {
 103                 .soc_id = UNIPHIER_LD4_ID,
 104                 .nand_2cs = true,
 105                 .sbc_init = uniphier_ld4_sbc_init,
 106                 .pll_init = uniphier_ld4_pll_init,
 107                 .clk_init = uniphier_ld4_clk_init,
 108         },
 109 #endif
 110 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
 111         {
 112                 .soc_id = UNIPHIER_PRO4_ID,
 113                 .nand_2cs = false,
 114                 .sbc_init = uniphier_sbc_init_savepin,
 115                 .pll_init = uniphier_pro4_pll_init,
 116                 .clk_init = uniphier_pro4_clk_init,
 117         },
 118 #endif
 119 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
 120         {
 121                 .soc_id = UNIPHIER_SLD8_ID,
 122                 .nand_2cs = true,
 123                 .sbc_init = uniphier_ld4_sbc_init,
 124                 .pll_init = uniphier_ld4_pll_init,
 125                 .clk_init = uniphier_ld4_clk_init,
 126         },
 127 #endif
 128 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 129         {
 130                 .soc_id = UNIPHIER_PRO5_ID,
 131                 .nand_2cs = true,
 132                 .sbc_init = uniphier_sbc_init_savepin,
 133                 .clk_init = uniphier_pro5_clk_init,
 134         },
 135 #endif
 136 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
 137         {
 138                 .soc_id = UNIPHIER_PXS2_ID,
 139                 .nand_2cs = true,
 140                 .sbc_init = uniphier_pxs2_sbc_init,
 141                 .clk_init = uniphier_pxs2_clk_init,
 142         },
 143 #endif
 144 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 145         {
 146                 .soc_id = UNIPHIER_LD6B_ID,
 147                 .nand_2cs = true,
 148                 .sbc_init = uniphier_pxs2_sbc_init,
 149                 .clk_init = uniphier_pxs2_clk_init,
 150         },
 151 #endif
 152 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
 153         {
 154                 .soc_id = UNIPHIER_LD11_ID,
 155                 .nand_2cs = false,
 156                 .sbc_init = uniphier_ld11_sbc_init,
 157                 .pll_init = uniphier_ld11_pll_init,
 158                 .clk_init = uniphier_ld11_clk_init,
 159                 .misc_init = uniphier_ld11_misc_init,
 160         },
 161 #endif
 162 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 163         {
 164                 .soc_id = UNIPHIER_LD20_ID,
 165                 .nand_2cs = false,
 166                 .sbc_init = uniphier_ld11_sbc_init,
 167                 .pll_init = uniphier_ld20_pll_init,
 168                 .clk_init = uniphier_ld20_clk_init,
 169                 .misc_init = uniphier_ld20_misc_init,
 170         },
 171 #endif
 172 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
 173         {
 174                 .soc_id = UNIPHIER_PXS3_ID,
 175                 .nand_2cs = false,
 176                 .sbc_init = uniphier_pxs2_sbc_init,
 177                 .pll_init = uniphier_pxs3_pll_init,
 178                 .clk_init = uniphier_pxs3_clk_init,
 179         },
 180 #endif
 181 };
 182 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
 183
 184 int board_init(void)
 185 {
 186         const struct uniphier_initdata *initdata;
 187         int ret;
 188
 189         led_puts("U0");
 190
 191         initdata = uniphier_get_initdata();
 192         if (!initdata) {
 193                 pr_err("unsupported SoC\n");
 194                 return -EINVAL;
 195         }
 196
 197         initdata->sbc_init();
 198
 199         support_card_init();
 200
 201         led_puts("U0");
 202
 203         if (IS_ENABLED(CONFIG_NAND_DENALI)) {
 204                 ret = uniphier_pin_init(initdata->nand_2cs ?
 205                                         "nand2cs_grp" : "nand_grp");
 206                 if (ret)
 207                         pr_err("failed to init NAND pins\n");
 208         }
 209
 210         led_puts("U1");
 211
 212         if (initdata->pll_init)
 213                 initdata->pll_init();
 214
 215         led_puts("U2");
 216
 217         if (initdata->clk_init)
 218                 initdata->clk_init();
 219
 220         led_puts("U3");
 221
 222         if (initdata->misc_init)
 223                 initdata->misc_init();
 224
 225         led_puts("U4");
 226
 227         uniphier_setup_xirq();
 228
 229         led_puts("U5");
 230
 231         support_card_late_init();
 232
 233         led_puts("U6");
 234
 235 #ifdef CONFIG_ARMV8_MULTIENTRY
 236         uniphier_smp_kick_all_cpus();
 237 #endif
 238
 239         led_puts("Uboo");
 240
 241         return 0;
 242 }