2 * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
4 * Copyright (C) 2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
12 #include <linux/sizes.h>
16 #define CCI500_BASE 0x5FD00000
17 #define CCI500_SLAVE_OFFSET 0x1000
19 #define CCI500_SNOOP_CTRL
20 #define CCI500_SNOOP_CTRL_EN_DVM BIT(1)
21 #define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0)
23 void cci500_init(unsigned int nr_slaves)
25 unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
28 for (i = 0; i < nr_slaves; i++) {
32 base = ioremap(slave_base, SZ_4K);
35 tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
40 slave_base += CCI500_SLAVE_OFFSET;