arch/arm/mach-u300/timer.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/timer.c
   4  *
   5  *
   6  * Copyright (C) 2007-2009 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Timer COH 901 328, runs the OS timer interrupt.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/interrupt.h>
  12 #include <linux/time.h>
  13 #include <linux/timex.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/types.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20 #include <linux/irq.h>
  21 #include <linux/delay.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24
  25 #include <mach/hardware.h>
  26 #include <mach/irqs.h>
  27
  28 /* Generic stuff */
  29 #include <asm/sched_clock.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/time.h>
  32
  33 #include "timer.h"
  34
  35 /*
  36  * APP side special timer registers
  37  * This timer contains four timers which can fire an interrupt each.
  38  * OS (operating system) timer @ 32768 Hz
  39  * DD (device driver) timer @ 1 kHz
  40  * GP1 (general purpose 1) timer @ 1MHz
  41  * GP2 (general purpose 2) timer @ 1MHz
  42  */
  43
  44 /* Reset OS Timer 32bit (-/W) */
  45 #define U300_TIMER_APP_ROST                                     (0x0000)
  46 #define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  47 /* Enable OS Timer 32bit (-/W) */
  48 #define U300_TIMER_APP_EOST                                     (0x0004)
  49 #define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  50 /* Disable OS Timer 32bit (-/W) */
  51 #define U300_TIMER_APP_DOST                                     (0x0008)
  52 #define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  53 /* OS Timer Mode Register 32bit (-/W) */
  54 #define U300_TIMER_APP_SOSTM                                    (0x000c)
  55 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  56 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  57 /* OS Timer Status Register 32bit (R/-) */
  58 #define U300_TIMER_APP_OSTS                                     (0x0010)
  59 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  60 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  61 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  62 #define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  63 #define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  64 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  65 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  66 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  67 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  68 /* OS Timer Current Count Register 32bit (R/-) */
  69 #define U300_TIMER_APP_OSTCC                                    (0x0014)
  70 /* OS Timer Terminal Count Register 32bit (R/W) */
  71 #define U300_TIMER_APP_OSTTC                                    (0x0018)
  72 /* OS Timer Interrupt Enable Register 32bit (-/W) */
  73 #define U300_TIMER_APP_OSTIE                                    (0x001c)
  74 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  75 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  76 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  77 #define U300_TIMER_APP_OSTIA                                    (0x0020)
  78 #define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  79
  80 /* Reset DD Timer 32bit (-/W) */
  81 #define U300_TIMER_APP_RDDT                                     (0x0040)
  82 #define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  83 /* Enable DD Timer 32bit (-/W) */
  84 #define U300_TIMER_APP_EDDT                                     (0x0044)
  85 #define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  86 /* Disable DD Timer 32bit (-/W) */
  87 #define U300_TIMER_APP_DDDT                                     (0x0048)
  88 #define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  89 /* DD Timer Mode Register 32bit (-/W) */
  90 #define U300_TIMER_APP_SDDTM                                    (0x004c)
  91 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  92 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  93 /* DD Timer Status Register 32bit (R/-) */
  94 #define U300_TIMER_APP_DDTS                                     (0x0050)
  95 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  96 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  97 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  98 #define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  99 #define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
 100 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
 101 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
 102 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
 103 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
 104 /* DD Timer Current Count Register 32bit (R/-) */
 105 #define U300_TIMER_APP_DDTCC                                    (0x0054)
 106 /* DD Timer Terminal Count Register 32bit (R/W) */
 107 #define U300_TIMER_APP_DDTTC                                    (0x0058)
 108 /* DD Timer Interrupt Enable Register 32bit (-/W) */
 109 #define U300_TIMER_APP_DDTIE                                    (0x005c)
 110 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 111 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 112 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 113 #define U300_TIMER_APP_DDTIA                                    (0x0060)
 114 #define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 115
 116 /* Reset GP1 Timer 32bit (-/W) */
 117 #define U300_TIMER_APP_RGPT1                                    (0x0080)
 118 #define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 119 /* Enable GP1 Timer 32bit (-/W) */
 120 #define U300_TIMER_APP_EGPT1                                    (0x0084)
 121 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 122 /* Disable GP1 Timer 32bit (-/W) */
 123 #define U300_TIMER_APP_DGPT1                                    (0x0088)
 124 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 125 /* GP1 Timer Mode Register 32bit (-/W) */
 126 #define U300_TIMER_APP_SGPT1M                                   (0x008c)
 127 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 128 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 129 /* GP1 Timer Status Register 32bit (R/-) */
 130 #define U300_TIMER_APP_GPT1S                                    (0x0090)
 131 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 132 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 133 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 134 #define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 135 #define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 136 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 137 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 138 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 139 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 140 /* GP1 Timer Current Count Register 32bit (R/-) */
 141 #define U300_TIMER_APP_GPT1CC                                   (0x0094)
 142 /* GP1 Timer Terminal Count Register 32bit (R/W) */
 143 #define U300_TIMER_APP_GPT1TC                                   (0x0098)
 144 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 145 #define U300_TIMER_APP_GPT1IE                                   (0x009c)
 146 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 147 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 148 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 149 #define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 150 #define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 151
 152 /* Reset GP2 Timer 32bit (-/W) */
 153 #define U300_TIMER_APP_RGPT2                                    (0x00c0)
 154 #define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 155 /* Enable GP2 Timer 32bit (-/W) */
 156 #define U300_TIMER_APP_EGPT2                                    (0x00c4)
 157 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 158 /* Disable GP2 Timer 32bit (-/W) */
 159 #define U300_TIMER_APP_DGPT2                                    (0x00c8)
 160 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 161 /* GP2 Timer Mode Register 32bit (-/W) */
 162 #define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 163 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 164 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 165 /* GP2 Timer Status Register 32bit (R/-) */
 166 #define U300_TIMER_APP_GPT2S                                    (0x00d0)
 167 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 168 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 169 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 170 #define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 171 #define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 172 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 173 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 174 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 175 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 176 /* GP2 Timer Current Count Register 32bit (R/-) */
 177 #define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 178 /* GP2 Timer Terminal Count Register 32bit (R/W) */
 179 #define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 180 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 181 #define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 182 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 183 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 184 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 185 #define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 186 #define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 187
 188 /* Clock request control register - all four timers */
 189 #define U300_TIMER_APP_CRC                                      (0x100)
 190 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 191
 192 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 193 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 194
 195 static void __iomem *u300_timer_base;
 196
 197 /*
 198  * The u300_set_mode() function is always called first, if we
 199  * have oneshot timer active, the oneshot scheduling function
 200  * u300_set_next_event() is called immediately after.
 201  */
 202 static void u300_set_mode(enum clock_event_mode mode,
 203                           struct clock_event_device *evt)
 204 {
 205         switch (mode) {
 206         case CLOCK_EVT_MODE_PERIODIC:
 207                 /* Disable interrupts on GPT1 */
 208                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 209                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 210                 /* Disable GP1 while we're reprogramming it. */
 211                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 212                        u300_timer_base + U300_TIMER_APP_DGPT1);
 213                 /*
 214                  * Set the periodic mode to a certain number of ticks per
 215                  * jiffy.
 216                  */
 217                 writel(TICKS_PER_JIFFY,
 218                        u300_timer_base + U300_TIMER_APP_GPT1TC);
 219                 /*
 220                  * Set continuous mode, so the timer keeps triggering
 221                  * interrupts.
 222                  */
 223                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 224                        u300_timer_base + U300_TIMER_APP_SGPT1M);
 225                 /* Enable timer interrupts */
 226                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 227                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 228                 /* Then enable the OS timer again */
 229                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 230                        u300_timer_base + U300_TIMER_APP_EGPT1);
 231                 break;
 232         case CLOCK_EVT_MODE_ONESHOT:
 233                 /* Just break; here? */
 234                 /*
 235                  * The actual event will be programmed by the next event hook,
 236                  * so we just set a dummy value somewhere at the end of the
 237                  * universe here.
 238                  */
 239                 /* Disable interrupts on GPT1 */
 240                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 241                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 242                 /* Disable GP1 while we're reprogramming it. */
 243                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 244                        u300_timer_base + U300_TIMER_APP_DGPT1);
 245                 /*
 246                  * Expire far in the future, u300_set_next_event() will be
 247                  * called soon...
 248                  */
 249                 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
 250                 /* We run one shot per tick here! */
 251                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 252                        u300_timer_base + U300_TIMER_APP_SGPT1M);
 253                 /* Enable interrupts for this timer */
 254                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 255                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 256                 /* Enable timer */
 257                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 258                        u300_timer_base + U300_TIMER_APP_EGPT1);
 259                 break;
 260         case CLOCK_EVT_MODE_UNUSED:
 261         case CLOCK_EVT_MODE_SHUTDOWN:
 262                 /* Disable interrupts on GP1 */
 263                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 264                        u300_timer_base + U300_TIMER_APP_GPT1IE);
 265                 /* Disable GP1 */
 266                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 267                        u300_timer_base + U300_TIMER_APP_DGPT1);
 268                 break;
 269         case CLOCK_EVT_MODE_RESUME:
 270                 /* Ignore this call */
 271                 break;
 272         }
 273 }
 274
 275 /*
 276  * The app timer in one shot mode obviously has to be reprogrammed
 277  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 278  * the interrupt disable + timer disable commands with a reset command,
 279  * it will fail miserably. Apparently (and I found this the hard way)
 280  * the timer is very sensitive to the instruction order, though you don't
 281  * get that impression from the data sheet.
 282  */
 283 static int u300_set_next_event(unsigned long cycles,
 284                                struct clock_event_device *evt)
 285
 286 {
 287         /* Disable interrupts on GPT1 */
 288         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 289                u300_timer_base + U300_TIMER_APP_GPT1IE);
 290         /* Disable GP1 while we're reprogramming it. */
 291         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 292                u300_timer_base + U300_TIMER_APP_DGPT1);
 293         /* Reset the General Purpose timer 1. */
 294         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 295                u300_timer_base + U300_TIMER_APP_RGPT1);
 296         /* IRQ in n * cycles */
 297         writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
 298         /*
 299          * We run one shot per tick here! (This is necessary to reconfigure,
 300          * the timer will tilt if you don't!)
 301          */
 302         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 303                u300_timer_base + U300_TIMER_APP_SGPT1M);
 304         /* Enable timer interrupts */
 305         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 306                u300_timer_base + U300_TIMER_APP_GPT1IE);
 307         /* Then enable the OS timer again */
 308         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 309                u300_timer_base + U300_TIMER_APP_EGPT1);
 310         return 0;
 311 }
 312
 313
 314 /* Use general purpose timer 1 as clock event */
 315 static struct clock_event_device clockevent_u300_1mhz = {
 316         .name           = "GPT1",
 317         .rating         = 300, /* Reasonably fast and accurate clock event */
 318         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 319         .set_next_event = u300_set_next_event,
 320         .set_mode       = u300_set_mode,
 321 };
 322
 323 /* Clock event timer interrupt handler */
 324 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 325 {
 326         struct clock_event_device *evt = &clockevent_u300_1mhz;
 327         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 328
 329         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 330                 u300_timer_base + U300_TIMER_APP_GPT1IA);
 331         evt->event_handler(evt);
 332         return IRQ_HANDLED;
 333 }
 334
 335 static struct irqaction u300_timer_irq = {
 336         .name           = "U300 Timer Tick",
 337         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 338         .handler        = u300_timer_interrupt,
 339 };
 340
 341 /*
 342  * Override the global weak sched_clock symbol with this
 343  * local implementation which uses the clocksource to get some
 344  * better resolution when scheduling the kernel. We accept that
 345  * this wraps around for now, since it is just a relative time
 346  * stamp. (Inspired by OMAP implementation.)
 347  */
 348
 349 static u32 notrace u300_read_sched_clock(void)
 350 {
 351         return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 352 }
 353
 354 static unsigned long u300_read_current_timer(void)
 355 {
 356         return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 357 }
 358
 359 static struct delay_timer u300_delay_timer;
 360
 361 /*
 362  * This sets up the system timers, clock source and clock event.
 363  */
 364 static void __init u300_timer_setup(void __iomem *base, int irq)
 365 {
 366         struct clk *clk;
 367         unsigned long rate;
 368
 369         u300_timer_base = base;
 370         pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
 371
 372         /* Clock the interrupt controller */
 373         clk = clk_get_sys("apptimer", NULL);
 374         BUG_ON(IS_ERR(clk));
 375         clk_prepare_enable(clk);
 376         rate = clk_get_rate(clk);
 377
 378         setup_sched_clock(u300_read_sched_clock, 32, rate);
 379
 380         u300_delay_timer.read_current_timer = &u300_read_current_timer;
 381         u300_delay_timer.freq = rate;
 382         register_current_timer_delay(&u300_delay_timer);
 383
 384         /*
 385          * Disable the "OS" and "DD" timers - these are designed for Symbian!
 386          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 387          */
 388         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 389                 u300_timer_base + U300_TIMER_APP_CRC);
 390         writel(U300_TIMER_APP_ROST_TIMER_RESET,
 391                 u300_timer_base + U300_TIMER_APP_ROST);
 392         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 393                 u300_timer_base + U300_TIMER_APP_DOST);
 394         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 395                 u300_timer_base + U300_TIMER_APP_RDDT);
 396         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 397                 u300_timer_base + U300_TIMER_APP_DDDT);
 398
 399         /* Reset the General Purpose timer 1. */
 400         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 401                 u300_timer_base + U300_TIMER_APP_RGPT1);
 402
 403         /* Set up the IRQ handler */
 404         setup_irq(irq, &u300_timer_irq);
 405
 406         /* Reset the General Purpose timer 2 */
 407         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 408                 u300_timer_base + U300_TIMER_APP_RGPT2);
 409         /* Set this timer to run around forever */
 410         writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
 411         /* Set continuous mode so it wraps around */
 412         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 413                u300_timer_base + U300_TIMER_APP_SGPT2M);
 414         /* Disable timer interrupts */
 415         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 416                 u300_timer_base + U300_TIMER_APP_GPT2IE);
 417         /* Then enable the GP2 timer to use as a free running us counter */
 418         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 419                 u300_timer_base + U300_TIMER_APP_EGPT2);
 420
 421         /* Use general purpose timer 2 as clock source */
 422         if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
 423                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 424                 pr_err("timer: failed to initialize U300 clock source\n");
 425
 426         /* Configure and register the clockevent */
 427         clockevents_config_and_register(&clockevent_u300_1mhz, rate,
 428                                         1, 0xffffffff);
 429
 430         /*
 431          * TODO: init and register the rest of the timers too, they can be
 432          * used by hrtimers!
 433          */
 434 }
 435
 436
 437 void __init u300_timer_init()
 438 {
 439         u300_timer_setup(U300_TIMER_APP_VBASE, IRQ_U300_TIMER_APP_GP1);
 440 }
 441
 442 #ifdef CONFIG_OF
 443
 444 static void __init u300_timer_init_of(struct device_node *np)
 445 {
 446         void __iomem *base;
 447         struct resource irq_res;
 448         int irq;
 449
 450         base = of_iomap(np, 0);
 451         /* Get the IRQ for the GP1 timer */
 452         irq = of_irq_to_resource(np, 2, &irq_res);
 453         u300_timer_setup(base, irq);
 454 }
 455
 456 CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
 457                        u300_timer_init_of);
 458
 459 #endif